Sample Questions

Dept: Electronics & Communication Engineering

Sub: VLSI CIRCUITS AND SYSYTEMS, Code: EC-604
Sem: 6th session: 2010
Full Marks- 70 Time- 3 Hours
Group-A
(Multiple choice Type Questions)
1. Choose the correct alternatives for any ten of the following: 10*1=10
i. Current mirrors are drifted from its ideal situation due t
o
(a) Channel length modulation effect
(b) Threshold offset among transistors
(c) Geometrical mismatch between transistors
(d) Any one of them.
ii. In stick diagram METAL1 represents which color?
(a) Green
(b) Red
(c) Blue
(d) Black
iii. The unit of trans-conductance parameter of MOSFET is
(a) mA2/V2 (b) mA/ V2 (c) mA2/V (d) mA/V
iv. For a N-input Domino CMOS logic the number of transistors
will be
(a) N+1
(b) N+4
(c) 2N
(d) 2N+2
v. For a NAND2 gate to obtain the threshold voltage of VDD/2
, the condition is a) Kp=4Kn, (b) 4KP=Kn, (c) Kp=Kn, (d) 2Kp=Kn
vi. Which DRAM i/p buffer has lowest power consumption and fa
stest in operation?
(a) Inverter type buffer,
(b) Latch-type buffer,
(c) Differential amplifier type buffer
(d) Both (b) & (c)
vii. The disadvantages of flash memory is
(a) High electrical voltage required to erase data
(b) Total block of memory is erased at a time
(c) Very slow writing speed
(d) Large space required
viii. Dynamic logic circuits require periodic clock signals in
order to
(e) Improve performance
(f) Control charge refreshing
(g) Increase density
(h) Reduce Silicon Area
ix. For a Pseudo NMOS Logic, a PMOS load is connected which a
cts as
(a) Constant current source
(b) Constant voltage source
(c) Inductor
(d) Reference voltage
x. For a CMOS inverter if the ratio of bn/bp is increased th
e transition region
(a) Shift from right to left
(b) Shift from left to right
(c) Remain constant
(d) None of these
xi. Frequency compensation of OPAMP using MOS technology is d
one by
(a) Decreasing the number of stages
(b) Minimizing the number of pole in single path
(c) Achieving low voltage gain
(d) All of the above
xii. In an ideal CMOS inverter the threshold voltage is
 (a) Vdd/2,
(b) 2*Vdd
(c) 0.5*Vdd
(d) (i & iii)
Group-B
(Short Answer Type Questions)
Answer any Three of the following questions
: 3*5=15
2. What is current source and current sink in VLSI circuit?
Design a current sink using VDD= -VSS=2.5V to sink a current of 10mA. Estimate
the minimum voltage across the current source and the output resistance. Assume
KP=50mA/V2, L=5mm, VTHN=0.83V, l=0.06 2+3=5

3. Draw and explain the operation of MOS Switched Capacitor Int

egrator and also find the expression for output voltage?
5
4. Design a half adder using standard CMOS AOI logic. If the Pr
echarge-Evaluate (PE) logic is used to design the same circuit, how many transis
tors will be required? In the Industrial view, which technology is preferable?
2.5+1.5+1=5
5. Compare between static logic and dynamic logic. Explain the
operation of Domino-logic to design any CMOS circuit.
2+3=5
6. What is Transmission Gate (TG)? Explain the operation of Edg
e Triggered D Flip-Flop using CMOS TG gates. Implement the expression using CMOS
TG logic. Z=XY +X Y. (X =complement of X) 1+2+
2=5
7. Design a CMOS 4:1 MUX using standard CMOS AOI logic.
Derive the expression for Dynamic Power Dissipati
on of a CMOS inverter?

(3+2=5)
8. Derive the expression for Trans-conductance (gm) of MOSFET a
nd also draw the characteristic graph of i. gm Vs (VGS-VT) when W/L is constant
ii. gm Vs (V
GS-VT) when ID is constant . iii. gm Vs ID when W/L is constant 5
Group-C
(Long Answer Type Questions)
Answer any three questions:
3*15=45
9. (a) What is an ideal op-amp?
2
(b) Draw the block diagram of two stage CMOS OPAMP. 3
(c) Find the Input common mode rang & Output swing of a two-stage CMOS OMPAMP?
5
(d) In a two stage CMOS OPAMP is fabricate in a process for which V/An=ç V/Apç=20 V/
mm. find A1, A2 & Av. if all devices are 1mm long. V0v1 =0.2v & V0v6 =0.5v. Als
o find the OPAMP output resistance obtained when the 2nd stage is biased at 0.5m
A. 5
10. (a) Draw the Voltage Transfer Curve of CMOS inverter circ
uit. Explain the different characteristic of a symmetric CMOS inverter. Prove th
at NMH=NML=VIL for an ideal inverter? 3+2+2=7
(a) Consider a CMOS inverter circuit with the following parameters: VDD=3.3V
VTo,n=0.6V VTo,p=-0.7V, Kn=200mA/V2 Kp=80mA/V2. Calculate the noise margins of t
he circuits. 4
(b) Estimate the intrinsic propagation delays tPHL+tPLH of a three input NAND
gate made using minimum size transistor. Also estimate the delay when the gate i
s driving a load capacitance of 100fF. Assume that inputs are tied together and
RP=24KW RN=8KW Cout,p=4.8fF Cout,n=4.8fF. 4
11. Write the short note on: (any three) 3*5=
15
(A) FPGA
(B) Array Multiplier
(C) Full custom Design
(D) Programmable Logic Array
(E) CMOS n-well process
(F) Floor Planning methods
(G) Carry Save Adder
12. a) Draw the layout of CMOS inverter (not to scale).
4
b) Distinguish between l based rules and micron rules. 5
(c) Realized the Boolean expression, Z=(D .E A )+(B .C ) using Standard CMOS and a
lso find the equivalent CMOS inverter circuit, assuming that (W/L)p=10 for all P
MOS transistors and (W/L)n=5 for all NMOS transistors. 4
(d) What are the utilities of Pseudo-NMOS in VLSI technology? 2
13. a) Briefly describe the VLSI Design Flow. 5
b)
What do you mean by Flash Memory. 5
c) Write the operation of six transistors SRAM. 5

14. a) Explain the operation of CMOS differential amplifier?

 5
b) How a MOS device can be used as a voltage reference?
5
c) What do you mean by hierarchy, Regularity, Modularity & Locality of a
ny ASIC design.