34349 Integrated Broadband Electronics

Journal: Ethernet Frame

Check Sequence
Kim Tja Xin Guo Du - s052329@student.dtu.dk

September 29, 2009

DTU Fotonik, Department of Photonics Engineering
DTU, Technical University of Denmark
 1

1 Introduction
In this exercise the task was to create a Ethernet frame checker using the generator polyno-
mial: G(x) = x3 2 + x2 6 + x2 3 + x2 2 + x1 6 + x1 2 + x1 1 + x1 0 + x8 + x7 + x5 + x4 + x2 + x + 1.
In the first part the received frame is loaded into the register bit-wise so to calculate if a
frame is correct it would take around 512 clock cycles.
The second part was to implement the same system just by reading 8 bits at the time
instead a single bit. This will limit the amount of clock cycles used to calculate the frame
to around 64 clock cycles.
To test if the correct output is given when a error occurs the first byte is set to 1 instead
of 0.
To synthesize the implementation a Stratix II model number EP2S15F484C3 has been
used. The achieved speed can be seen in the timing tables.

2 fcs check serial

It should be noted that there are an implementation error in the serial frame checker.
fcs error is high all the time unless there is an error in the Ethernet frame then it will go
low (see Figure 3). So for correct implementation this needs to be inverted.

Type Slack Required Actual From To From To Failed

time time clock clock paths
Worst-case N/A None 4.410 start of frame count[0] – clk 0
tsu ns
Worst-case N/A None 5.440 fcs error reg0 fcs error clk – 0
tco ns
Worst-case N/A None -2.778 end of frame end frame – clk 0
th ns
Clock Setup: N/A None 403.06 count[12] data clk clk 0
’clk’ MHz (
period
= 2.481
ns )
Total num- 0
ber of failed
paths

Table 1: Summary of timing for the serial synthesis.

2.1 Place & route report

Fitter Status Successful - Mon Sep 28 22:50:22 2009
Quartus II Version 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name fcs_check_serial
Top-level Entity Name fcs_check_serial
Family Stratix II
Device EP2S15F484C3
Timing Models Final
2.1 Place & route report 2

Logic utilization < 1 %

Combinational ALUTs 66 / 12,480 ( < 1 % )
Dedicated logic registers 68 / 12,480 ( < 1 % )
Total registers 68
Total pins 6 / 343 ( 2 % )
Total virtual pins 0
Total block memory bits 0 / 419,328 ( 0 % )
DSP block 9-bit elements 0 / 96 ( 0 % )
Total PLLs 0 / 6 ( 0 % )
Total DLLs 0 / 2 ( 0 % )

Figure 1: The start of reading the Ethernet frame.

Figure 2: The end of reading the Ethernet frame (without error).

 2.2 VHDL code for serial 3

2.2 VHDL code for serial

1 library i e e e ;
2 use i e e e . s t d l o g i c 1 1 6 4 . a l l ;
3
4 entity f c s c h e c k s e r i a l i s
5 port (
6 clk : in s t d l o g i c ; −− s y s t e m c l o c k
7 reset : in s t d l o g i c ; −− a s y n c h r o n o u s r e s e t
8 s t a r t o f f r a m e : in s t d l o g i c ; −− a r r i v a l o f t h e f i r s t b i t .
9 e n d o f f r a m e : in s t d l o g i c ; −− a r r i v a l o f t h e f i r s t b i t i n FCS .
10 data in : in s t d l o g i c ; −− s e r i a l i n p u t d a t a .
11 fcs error : out s t d l o g i c −− i n d i c a t e s an e r r o r .
12 );
13 end f c s c h e c k s e r i a l ;
14
15 architecture f c s c h e c k of f c s c h e c k s e r i a l i s
16 signal reg : s t d l o g i c v e c t o r ( 3 1 downto 0 ) ;
17 s i g n a l data : std logic ;
18 signal end frame : s t d l o g i c ;
19 s i g n a l count : i n t e g e r := 0 ;
20 signal s t a r t : s t d l o g i c ;
21 begin
22
23 i n v e r t : process ( c l k , r e s e t , e n d o f f r a m e ) i s
24
25 begin
26 i f r e s e t = ’ 1 ’ then
27 data <= ’ 0 ’ ;
28 e n d f r a m e <= ’ 0 ’ ;
29 count <= 0 ;
30 s t a r t <= ’ 0 ’ ;
31 e l s i f r i s i n g e d g e ( c l k ) then

Figure 3: The end of reading the Ethernet frame (with error).

 2.2 VHDL code for serial 4

32 i f s t a r t o f f r a m e = ’ 1 ’ then
33 count <= 0 a f t e r 2 ns ;
34 e n d f r a m e <= ’ 0 ’ a f t e r 2 ns ;
35 s t a r t <= ’ 1 ’ ;
36 e l s i f e n d o f f r a m e = ’ 1 ’ then
37 count <= 0 a f t e r 2 ns ;
38 e n d f r a m e <= ’ 1 ’ a f t e r 2 ns ;
39 data <= not d a t a i n a f t e r 5 ns ;
40 else
41 count <= count + 1 a f t e r 2 ns ;
42 end i f ;
43 i f count < 31 then
44 data <= not d a t a i n a f t e r 5 ns ;
45 else
46 i f e n d o f f r a m e = ’0 ’ then
47 data <= d a t a i n a f t e r 5 ns ;
48 end i f ;
49 end i f ;
50 end i f ;
51 end process i n v e r t ;
52
53 s e t r e g : process ( c l k , r e s e t ) i s
54 begin
55 i f r e s e t = ’ 1 ’ then
56 r e g <= (OTHERS => ’ 0 ’ ) ;
57 f c s e r r o r <= ’ 1 ’ ;
58 e l s i f r i s i n g e d g e ( c l k ) then
59 i f e n d f r a m e = ’ 1 ’ then
60 i f r e g ( 3 1 downto 0 ) = x” 00000000 ” then
61 f c s e r r o r <= ’ 0 ’ a f t e r 5 ns ;
62 else
63 f c s e r r o r <= ’ 1 ’ a f t e r 5 ns ;
64 end i f ;
65 end i f ;
66 i f s t a r t = ’ 1 ’ then
67 r e g ( 0 ) <= r e g ( 3 1 ) xor data a f t e r 10 ns ;
68 r e g ( 1 ) <= r e g ( 3 1 ) xor r e g ( 0 ) a f t e r 10 ns ;
69 r e g ( 2 ) <= r e g ( 3 1 ) xor r e g ( 1 ) a f t e r 10 ns ;
70 r e g ( 3 ) <= r e g ( 2 ) a f t e r 10 ns ;
71 r e g ( 4 ) <= r e g ( 3 1 ) xor r e g ( 3 ) a f t e r 10 ns ;
72 r e g ( 5 ) <= r e g ( 3 1 ) xor r e g ( 4 ) a f t e r 10 ns ;
73 r e g ( 6 ) <= r e g ( 5 ) a f t e r 10 ns ;
74 r e g ( 7 ) <= r e g ( 3 1 ) xor r e g ( 6 ) a f t e r 10 ns ;
75 r e g ( 8 ) <= r e g ( 3 1 ) xor r e g ( 7 ) a f t e r 10 ns ;
76 r e g ( 9 ) <= r e g ( 8 ) a f t e r 10 ns ;
77 r e g ( 1 0 ) <= r e g ( 3 1 ) xor r e g ( 9 ) a f t e r 10 ns ;
78 r e g ( 1 1 ) <= r e g ( 3 1 ) xor r e g ( 1 0 ) a f t e r 10 ns ;
79 r e g ( 1 2 ) <= r e g ( 3 1 ) xor r e g ( 1 1 ) a f t e r 10 ns ;
80 r e g ( 1 3 ) <= r e g ( 1 2 ) a f t e r 10 ns ;
81 r e g ( 1 4 ) <= r e g ( 1 3 ) a f t e r 10 ns ;
82 r e g ( 1 5 ) <= r e g ( 1 4 ) a f t e r 10 ns ;
83 r e g ( 1 6 ) <= r e g ( 3 1 ) xor r e g ( 1 5 ) a f t e r 10 ns ;
84 r e g ( 1 7 ) <= r e g ( 1 6 ) a f t e r 10 ns ;
 2.2 VHDL code for serial 5

85 r e g ( 1 8 ) <= r e g ( 1 7 ) a f t e r 10 ns ;
86 r e g ( 1 9 ) <= r e g ( 1 8 ) a f t e r 10 ns ;
87 r e g ( 2 0 ) <= r e g ( 1 9 ) a f t e r 10 ns ;
88 r e g ( 2 1 ) <= r e g ( 2 0 ) a f t e r 10 ns ;
89 r e g ( 2 2 ) <= r e g ( 3 1 ) xor r e g ( 2 1 ) a f t e r 10 ns ;
90 r e g ( 2 3 ) <= r e g ( 3 1 ) xor r e g ( 2 2 ) a f t e r 10 ns ;
91 r e g ( 2 4 ) <= r e g ( 2 3 ) a f t e r 10 ns ;
92 r e g ( 2 5 ) <= r e g ( 2 4 ) a f t e r 10 ns ;
93 r e g ( 2 6 ) <= r e g ( 3 1 ) xor r e g ( 2 5 ) a f t e r 10 ns ;
94 r e g ( 2 7 ) <= r e g ( 2 6 ) a f t e r 10 ns ;
95 r e g ( 2 8 ) <= r e g ( 2 7 ) a f t e r 10 ns ;
96 r e g ( 2 9 ) <= r e g ( 2 8 ) a f t e r 10 ns ;
97 r e g ( 3 0 ) <= r e g ( 2 9 ) a f t e r 10 ns ;
98 r e g ( 3 1 ) <= r e g ( 3 0 ) a f t e r 10 ns ;
99 end i f ;
100 end i f ;
101 end process s e t r e g ;
102 end architecture f c s c h e c k ;
 2.3 Test bench for serial 6

2.3 Test bench for serial

1 LIBRARY i e e e ;
2 USE i e e e . s t d l o g i c 1 1 6 4 . a l l ;
3 use i e e e . s t d l o g i c a r i t h . a l l ;
4
5 ENTITY t e s t b e n c h IS END;
6
7 ARCHITECTURE a r c h OF t e s t b e n c h IS
8
9 COMPONENT f c s c h e c k s e r i a l
10 PORT(
11 clk : in s t d l o g i c ; −− s y s t e m c l o c k
12 reset : in s t d l o g i c ; −− a s y n c h r o n o u s r e s e t
13 s t a r t o f f r a m e : in s t d l o g i c ; −− a r r i v a l o f t h e f i r s t b i t .
14 e n d o f f r a m e : in s t d l o g i c ; −− a r r i v a l o f t h e f i r s t b i t i n FCS .
15 data in : in s t d l o g i c ; −− s e r i a l i n p u t d a t a .
16 fcs error : out s t d l o g i c −− i n d i c a t e s an e r r o r .
17 );
18 END COMPONENT;
19
20 SIGNAL start of frame , end of frame , data in , f c s e r r o r : s t d l o g i c ;
21 SIGNAL data , data1 : s t d l o g i c v e c t o r ( 0 to 5 1 1 ) ;
22 SIGNAL clk : s t d l o g i c := ’ 0 ’ ;
23 SIGNAL reset : s t d l o g i c := ’ 1 ’ ;
24 SIGNAL count : i n t e g e r range 0 to 1024 := 0 ;
25
26 BEGIN
27 −− VARIABLE c o u n t : i n t e g e r := 0 ;
28 data <= x” 0010
A47BEA8000123456789008004500002EB3FE000080110540C0A8002CC0A8000404000400001A2DE8000102
”;
29 −−d a t a (0 t o 31) <= n o t d a t a 1 (0 t o 31) ;
30 −−d a t a (32 t o 479) <= d a t a 1 (32 t o 479) ;
31 −−d a t a (480 t o 511) <= n o t d a t a 1 (480 t o 511) ;
32
33 uut : f c s c h e c k s e r i a l
34 PORT MAP(
35 c l k => c l k ,
36 r e s e t => r e s e t ,
37 s t a r t o f f r a m e => s t a r t o f f r a m e ,
38 e n d o f f r a m e => e n d o f f r a m e ,
39 d a t a i n => d a t a i n ,
40 f c s e r r o r => f c s e r r o r
41 );
42
43 c l k <= not c l k a f t e r 10 ns ;
44 r e s e t <= ’ 0 ’ a f t e r 25 ns ;
45
46 t e s t : PROCESS ( c l k , r e s e t ) IS
47
48 BEGIN
49 IF r e s e t = ’ 1 ’ THEN
 7

50 count <= 0 ;
51 d a t a i n <= ’ 0 ’ ;
52 s t a r t o f f r a m e <= ’ 0 ’ ;
53 e n d o f f r a m e <= ’ 0 ’ ;
54 ELSIF r i s i n g e d g e ( c l k ) THEN
55 IF count = 0 THEN
56 s t a r t o f f r a m e <= ’ 1 ’ a f t e r 2 ns ;
57 d a t a i n <= data ( count ) a f t e r 2 ns ;
58 ELSIF count = 480 THEN
59 e n d o f f r a m e <= ’ 1 ’ a f t e r 2 ns ;
60 d a t a i n <= data ( count ) a f t e r 2 ns ;
61 ELSIF count > 511 THEN
62 d a t a i n <= ’ 0 ’ a f t e r 5 ns ;
63 ELSE
64 e n d o f f r a m e <= ’ 0 ’ a f t e r 2 ns ;
65 s t a r t o f f r a m e <= ’ 0 ’ a f t e r 2 ns ;
66 d a t a i n <= data ( count ) a f t e r 2 ns ;
67 END IF ;
68 count <= count + 1 a f t e r 5 ns ;
69 END IF ;
70 END PROCESS;
71
72
73 END ARCHITECTURE a r c h ;

3 fcs check parallel

Type Slack Required Actual From To From To Failed

time time clock clock paths
Worst-case N/A None 3.179 data in[0] data reg[0] – clk 0
tsu ns
Worst-case N/A None 6.013 fcs error reg0 fcs error clk – 0
tco ns
Worst-case N/A None -2.503 start of frame start frame – clk 0
th ns
Clock Setup: N/A None 448.03 reg[10] fcs error reg0 clk clk 0
’clk’ MHz (
period
= 2.232
ns )
Total num- 0
ber of failed
paths

Table 2: Summary of timing for the parallel synthesis.

3.1 Place & route report

Fitter Status Successful - Mon Sep 28 22:56:20 2009
3.1 Place & route report 8

Quartus II Version 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition

Revision Name parallel
Top-level Entity Name fcs_check_parallel
Family Stratix II
Device EP2S15F484C3
Timing Models Final
Logic utilization < 1 %
Combinational ALUTs 72 / 12,480 ( < 1 % )
Dedicated logic registers 53 / 12,480 ( < 1 % )
Total registers 53
Total pins 13 / 343 ( 4 % )

Figure 4: The start of reading the Ethernet frame.

Figure 5: The end of reading the Ethernet frame (without error).

3.2 Matlab program for equations 9

Total virtual pins 0

Total block memory bits 0 / 419,328 ( 0 % )
DSP block 9-bit elements 0 / 96 ( 0 % )
Total PLLs 0 / 6 ( 0 % )
Total DLLs 0 / 2 ( 0 % )

3.2 Matlab program for equations

To calculate the dependencies for each of the 32 bits a Matlab program has been used. The
matrix below is multiplied with itself 8 times to find the dependencies after 8 clock cycles.
Each row corresponds to a bit in the 32 bit register where top row is the first bit R(0) (see
Figure 7). The code does not include the input bits so this needs to manually be added for
the first 8 bits in the register.
2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3
6 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 7
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
6 7
6 7
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6 7
6 7
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
6 7
6 7
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
6 7
6 7
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6 7
6 7
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
6 7
6 7
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
6 7
6 7
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6 7
6 7
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
6 7
6 7
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
6 7
6 7
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
6 7
6 7
0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6 7
6 7
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6 7
6 7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6 7
6 7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
6 7
6 7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6 7
6 7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6 7
6 7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
6 7
6 7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
6 7
6 7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
6 7
6 7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1
6 7
6 7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1
6 7
6 7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
6 7
6 7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
6 7
6 7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1
6 7
6 7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
6 7
6 7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
6 7
6 7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
6 7
6 7
4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 5
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

Figure 6: The end of reading the Ethernet frame (with error).

 By adding R(X) on both sides of this equation we obtain (remember we are using modulo 2 algebra, which
means that R(X) + R(X) = 0):

M(X)*x^32 + R(X) = P(X)*G(X).

We notice that M(X)*x^32 + R(X) is divisible by G(X). In other words, the packet is considered error free
if the remainder from dividing M(X)*x^32 + R(X) with G(X) is zero.

The remainder is stored in the 32 registers R(31)..R(0). The generating polynomial is generally defined as:
3.2 Matlab program for equations 10
G(X) = g32*X^32 + g31*X^31 ........ g2*X^2 + g1*X^1 + g0

The circuit for the computation of R(X) (and P(X)) is given below.

g0 g1 g2 g3 g30 g31

R(0) R(1) R(2) R(3) R(30) R(31)

M(X)

Figure The
7: packet
Enumeration of the +32
bit stream, M(X)*x^32 bitis fed
R(X), register. ImageThe
into the calculator. taken from
Registers exercise
must contain document.
“0” before
the calculation is initiated. The last 32 bits that enter the circuit is the FCS (Remember to complement to
convert to the CRC value). The data bits are error free if all the registers contain “0”.

1 c l e a r a l lExample
; Ethernet packet with valid checksum (B3 31 88 1B):
2 n = 3 1 ; 00 10 A4 7B EA 80 00 12 34 56 78 90 08 00 45 00 00 2E B3 FE 00 00 80 11
05 40 C0 A8 00 2C C0 A8 00 04 04 00 04 00 00 1A 2D E8 00 01 02 03 04 05
3 % B i t s i n06 s e 07
r t e08 d 09t o0At h0Be 0Cr e0Dg i0Es t e0Fr 10a t11t h
E6e C5time
3D B2
4 cycles = 8;
5 % Generator p o l y n o m i a l
6 G = [ 0 0 Tasks 0 0 0 1 0 0 1 1 0 0 0 0 0 1 0 0 0 1 1 1 0 1 1 0 1 1 0 1 1 1];
7 A = [ zeros ( 1 , n ) ; eye ( n ) ] ;
Task 1
8 A = [A f lGenerate i p l r (G) ’];
VHDL code that checks an Ethernet packet for bit errors. Assume that the packet is received as a
9 B = mod(Aˆ c ybitc lstream.
serial e s , 2That
) ; is, the circuit above can be used directly. The module “fcs_check_serial” should con-
10 f i d = fopen tain the
( ’following
r e g i s IO
t esignals:
r . t x t ’ , ’w ’ ) ;
11 f o r i =1:32
12 r e g = find (B( i , : ) ==1) ;
13 text = [ ’ r e g ( ’ num2str ( i −1) ’ ) <= ’ ] ;
14 i f ( ˜ isempty ( r e g ) )
15 f o r j =1: length ( r e g )
16 text = [ text ’ r e g ( ’ num2str ( r e g ( j ) −1) ’ ) ’ ] ;
17 i f ( j ˜= length ( r e g ) )
18 text = [ text ’ xor ’ ] ;
19 end
20 end
21 end
22 text = [ text ’ a f t e r 10 ns ; \ r \n ’ ] ;
23 f p r i n t f ( f i d , text , c h a r ) ;
24 end
25 f c l o s e ( f i d ) ;
 3.3 VHDL code for parallel 11

3.3 VHDL code for parallel

1 LIBRARY i e e e ;
2 USE i e e e . s t d l o g i c 1 1 6 4 . a l l ;
3
4 ENTITY f c s c h e c k p a r a l l e l IS
5 PORT (
6 clk : in s t d l o g i c ; −− s y s t e m c l o c k
7 reset : in s t d l o g i c ; −− a s y n c h r o n o u s r e s e t
8 start of frame : in s t d l o g i c ; −− a r r i v a l o f t h e f i r s t b i t .
9 end of frame : in s t d l o g i c ; −− a r r i v a l o f t h e f i r s t b i t i n FCS .
10 data in : in s t d l o g i c v e c t o r ( 7 downto 0 ) ; −− i n p u t d a t a .
11 fcs error : out s t d l o g i c −− i n d i c a t e s an e r r o r .
12 );
13 END f c s c h e c k p a r a l l e l ;
14
15 ARCHITECTURE B e h a v i o r OF f c s c h e c k p a r a l l e l IS
16 SIGNAL r e g : s t d l o g i c v e c t o r ( 3 1 downto 0 ) ;
17 SIGNAL d a t a r e g : s t d l o g i c v e c t o r ( 7 downto 0 ) ;
18 SIGNAL count : i n t e g e r range 0 to 1023 := 0 ;
19 SIGNAL s t a r t f r a m e : s t d l o g i c ; −− I n d i c a t e s when t o l o a d d a t a .
20 SIGNAL e n d f r a m e : std logic ;
21 BEGIN
22
23 frame : PROCESS ( c l k , r e s e t , s t a r t o f f r a m e , e n d o f f r a m e )
24 BEGIN
25 IF r e s e t = ’ 1 ’ THEN
26 e n d f r a m e <= ’ 0 ’ AFTER 10 ns ;
27 s t a r t f r a m e <= ’ 0 ’ AFTER 10 ns ;
28 ELSIF r i s i n g e d g e ( c l k ) THEN
29 IF e n d o f f r a m e = ’ 1 ’ THEN
30 e n d f r a m e <= ’ 1 ’ AFTER 10 ns ;
31 s t a r t f r a m e <= ’ 0 ’ AFTER 90 ns ;
32 ELSIF s t a r t o f f r a m e = ’ 1 ’ THEN
33 s t a r t f r a m e <= ’ 1 ’ AFTER 10 ns ;
34 END IF ;
35 END IF ;
36 END PROCESS frame ;
37
38 r e g i s : PROCESS ( c l k , r e s e t )
39 BEGIN
40 IF r e s e t = ’ 1 ’ THEN
41 r e g <= (OTHERS => ’ 0 ’ ) AFTER 10 ns ;
42 d a t a r e g <= (OTHERS => ’ 0 ’ ) AFTER 10 ns ;
43 f c s e r r o r <= ’ 0 ’ AFTER 10 ns ;
44 count <= 0 AFTER 10 ns ;
45 ELSIF r i s i n g e d g e ( c l k ) THEN
46 IF count = 1 OR count = 2 OR count = 3 OR count = 4 THEN
47 d a t a r e g ( 7 downto 0 ) <= not d a t a i n ( 7 downto 0 ) a f t e r 10 ns ;
48 ELSIF count = 61 OR count = 62 OR count = 63 OR count = 64 THEN
49 d a t a r e g ( 7 downto 0 ) <= not d a t a i n ( 7 downto 0 ) a f t e r 10 ns ;
50 ELSE
51 d a t a r e g ( 7 downto 0 ) <= d a t a i n ( 7 downto 0 ) a f t e r 10 ns ;
52 END IF ;
 3.3 VHDL code for parallel 12

53 IF s t a r t f r a m e = ’ 1 ’ THEN
54 r e g ( 0 ) <= d a t a r e g ( 0 ) xor r e g ( 2 4 ) xor r e g ( 3 0 ) a f t e r 10 ns ;
55 r e g ( 1 ) <= d a t a r e g ( 1 ) xor r e g ( 2 4 ) xor r e g ( 2 5 ) xor r e g ( 3 0 ) xor r e g
( 3 1 ) a f t e r 10 ns ;
56 r e g ( 2 ) <= d a t a r e g ( 2 ) xor r e g ( 2 4 ) xor r e g ( 2 5 ) xor r e g ( 2 6 ) xor r e g
( 3 0 ) xor r e g ( 3 1 ) a f t e r 10 ns ;
57 r e g ( 3 ) <= d a t a r e g ( 3 ) xor r e g ( 2 5 ) xor r e g ( 2 6 ) xor r e g ( 2 7 ) xor r e g
( 3 1 ) a f t e r 10 ns ;
58 r e g ( 4 ) <= d a t a r e g ( 4 ) xor r e g ( 2 4 ) xor r e g ( 2 6 ) xor r e g ( 2 7 ) xor r e g
( 2 8 ) xor r e g ( 3 0 ) a f t e r 10 ns ;
59 r e g ( 5 ) <= d a t a r e g ( 5 ) xor r e g ( 2 4 ) xor r e g ( 2 5 ) xor r e g ( 2 7 ) xor r e g
( 2 8 ) xor r e g ( 2 9 ) xor r e g ( 3 0 ) xor r e g ( 3 1 ) a f t e r 10 ns ;
60 r e g ( 6 ) <= d a t a r e g ( 6 ) xor r e g ( 2 5 ) xor r e g ( 2 6 ) xor r e g ( 2 8 ) xor r e g
( 2 9 ) xor r e g ( 3 0 ) xor r e g ( 3 1 ) a f t e r 10 ns ;
61 r e g ( 7 ) <= d a t a r e g ( 7 ) xor r e g ( 2 4 ) xor r e g ( 2 6 ) xor r e g ( 2 7 ) xor r e g
( 2 9 ) xor r e g ( 3 1 ) a f t e r 10 ns ;
62 r e g ( 8 ) <= r e g ( 0 ) xor r e g ( 2 4 ) xor r e g ( 2 5 ) xor r e g ( 2 7 ) xor r e g ( 2 8 )
a f t e r 10 ns ;
63 r e g ( 9 ) <= r e g ( 1 ) xor r e g ( 2 5 ) xor r e g ( 2 6 ) xor r e g ( 2 8 ) xor r e g ( 2 9 )
a f t e r 10 ns ;
64 r e g ( 1 0 ) <= r e g ( 2 ) xor r e g ( 2 4 ) xor r e g ( 2 6 ) xor r e g ( 2 7 ) xor r e g ( 2 9 )
a f t e r 10 ns ;
65 r e g ( 1 1 ) <= r e g ( 3 ) xor r e g ( 2 4 ) xor r e g ( 2 5 ) xor r e g ( 2 7 ) xor r e g ( 2 8 )
a f t e r 10 ns ;
66 r e g ( 1 2 ) <= r e g ( 4 ) xor r e g ( 2 4 ) xor r e g ( 2 5 ) xor r e g ( 2 6 ) xor r e g ( 2 8 )
xor r e g ( 2 9 ) xor r e g ( 3 0 ) a f t e r 10 ns ;
67 r e g ( 1 3 ) <= r e g ( 5 ) xor r e g ( 2 5 ) xor r e g ( 2 6 ) xor r e g ( 2 7 ) xor r e g ( 2 9 )
xor r e g ( 3 0 ) xor r e g ( 3 1 ) a f t e r 10 ns ;
68 r e g ( 1 4 ) <= r e g ( 6 ) xor r e g ( 2 6 ) xor r e g ( 2 7 ) xor r e g ( 2 8 ) xor r e g ( 3 0 )
xor r e g ( 3 1 ) a f t e r 10 ns ;
69 r e g ( 1 5 ) <= r e g ( 7 ) xor r e g ( 2 7 ) xor r e g ( 2 8 ) xor r e g ( 2 9 ) xor r e g ( 3 1 )
a f t e r 10 ns ;
70 r e g ( 1 6 ) <= r e g ( 8 ) xor r e g ( 2 4 ) xor r e g ( 2 8 ) xor r e g ( 2 9 ) a f t e r 10 ns ;
71 r e g ( 1 7 ) <= r e g ( 9 ) xor r e g ( 2 5 ) xor r e g ( 2 9 ) xor r e g ( 3 0 ) a f t e r 10 ns ;
72 r e g ( 1 8 ) <= r e g ( 1 0 ) xor r e g ( 2 6 ) xor r e g ( 3 0 ) xor r e g ( 3 1 ) a f t e r 10 ns ;
73 r e g ( 1 9 ) <= r e g ( 1 1 ) xor r e g ( 2 7 ) xor r e g ( 3 1 ) a f t e r 10 ns ;
74 r e g ( 2 0 ) <= r e g ( 1 2 ) xor r e g ( 2 8 ) a f t e r 10 ns ;
75 r e g ( 2 1 ) <= r e g ( 1 3 ) xor r e g ( 2 9 ) a f t e r 10 ns ;
76 r e g ( 2 2 ) <= r e g ( 1 4 ) xor r e g ( 2 4 ) a f t e r 10 ns ;
77 r e g ( 2 3 ) <= r e g ( 1 5 ) xor r e g ( 2 4 ) xor r e g ( 2 5 ) xor r e g ( 3 0 ) a f t e r 10 ns ;
78 r e g ( 2 4 ) <= r e g ( 1 6 ) xor r e g ( 2 5 ) xor r e g ( 2 6 ) xor r e g ( 3 1 ) a f t e r 10 ns ;
79 r e g ( 2 5 ) <= r e g ( 1 7 ) xor r e g ( 2 6 ) xor r e g ( 2 7 ) a f t e r 10 ns ;
80 r e g ( 2 6 ) <= r e g ( 1 8 ) xor r e g ( 2 4 ) xor r e g ( 2 7 ) xor r e g ( 2 8 ) xor r e g ( 3 0 )
a f t e r 10 ns ;
81 r e g ( 2 7 ) <= r e g ( 1 9 ) xor r e g ( 2 5 ) xor r e g ( 2 8 ) xor r e g ( 2 9 ) xor r e g ( 3 1 )
a f t e r 10 ns ;
82 r e g ( 2 8 ) <= r e g ( 2 0 ) xor r e g ( 2 6 ) xor r e g ( 2 9 ) xor r e g ( 3 0 ) a f t e r 10 ns ;
83 r e g ( 2 9 ) <= r e g ( 2 1 ) xor r e g ( 2 7 ) xor r e g ( 3 0 ) xor r e g ( 3 1 ) a f t e r 10 ns ;
84 r e g ( 3 0 ) <= r e g ( 2 2 ) xor r e g ( 2 8 ) xor r e g ( 3 1 ) a f t e r 10 ns ;
85 r e g ( 3 1 ) <= r e g ( 2 3 ) xor r e g ( 2 9 ) a f t e r 10 ns ;
86 END IF ;
87 IF e n d f r a m e = ’ 1 ’ THEN
88 IF count = 66 THEN
 3.3 VHDL code for parallel 13

89 IF r e g ( 3 1 downto 0 ) = X” 00000000 ” THEN

90 f c s e r r o r <= ’ 0 ’ a f t e r 10 ns ;
91 ELSE
92 f c s e r r o r <= ’ 1 ’ a f t e r 10 ns ;
93 END IF ;
94 END IF ;
95 END IF ;
96 count <= count + 1 AFTER 10 ns ;
97 END IF ;
98 END PROCESS r e g i s ;
99
100 END B e h a v i o r ;
 3.4 Test bench for parallel 14

3.4 Test bench for parallel

1 LIBRARY i e e e ;
2 USE i e e e . s t d l o g i c 1 1 6 4 . a l l ;
3 USE i e e e . s t d l o g i c a r i t h . a l l ;
4
5 ENTITY t e s t b e n c h IS END;
6
7 ARCHITECTURE a r c h OF t e s t b e n c h IS
8 COMPONENT f c s c h e c k p a r a l l e l
9 PORT (
10 clk : in s t d l o g i c ; −− s y s t e m c l o c k
11 reset : in s t d l o g i c ; −− a s y n c h r o n o u s r e s e t
12 start of frame : in s t d l o g i c ; −− a r r i v a l o f t h e f i r s t b i t .
13 end of frame : in s t d l o g i c ; −− a r r i v a l o f t h e f i r s t b i t
i n FCS .
14 data in : in s t d l o g i c v e c t o r ( 7 downto 0 ) ; −− i n p u t
data .
15 fcs error : out s t d l o g i c −− i n d i c a t e s an e r r o r .
16 );
17 END COMPONENT;
18
19 SIGNAL start of frame : std logic ;
20 SIGNAL end of frame : std logic ;
21 SIGNAL fcs error : std logic ;
22 SIGNAL data : s t d l o g i c v e c t o r ( 0 to 5 1 1 ) ;
23 SIGNAL data in : s t d l o g i c v e c t o r ( 7 downto 0 ) ;
24 SIGNAL clk : s t d l o g i c := ’ 0 ’ ;
25 SIGNAL reset : s t d l o g i c := ’ 1 ’ ;
26 SIGNAL count : i n t e g e r range 0 to 1024 := 0 ;
27
28 BEGIN
29 data <= x” 0010
A47BEA8000123456789008004500002EB3FE000080110540C0A8002CC0A8000404000400001A2DE8000102
”;
30 −− FFEF5B84
31 −− d a t a (0 t o 31) <= n o t d a t a 1 (0 t o 31) ;
32 −− d a t a (32 t o 479) <= d a t a 1 (32 t o 479) ;
33 −− d a t a (480 t o 511) <= n o t d a t a 1 (480 t o 511) ;
34 uut : f c s c h e c k p a r a l l e l
35 PORT MAP(
36 c l k => c l k ,
37 r e s e t => r e s e t ,
38 s t a r t o f f r a m e => s t a r t o f f r a m e ,
39 e n d o f f r a m e => e n d o f f r a m e ,
40 d a t a i n => d a t a i n ( 7 downto 0 ) ,
41 f c s e r r o r => f c s e r r o r
42 );
43
44 c l k <= not c l k a f t e r 10 ns ;
45 r e s e t <= ’ 0 ’ a f t e r 30 ns ;
46
47 t e s t : PROCESS ( c l k , r e s e t ) IS
48 BEGIN
 3.4 Test bench for parallel 15

49 IF r e s e t = ’ 1 ’ THEN
50 count <= 0 AFTER 10 ns ;
51 d a t a i n <= ” 00000000 ” AFTER 10 ns ;
52 s t a r t o f f r a m e <= ’ 0 ’ AFTER 10 ns ;
53 e n d o f f r a m e <= ’ 0 ’ AFTER 10 ns ;
54 ELSIF r i s i n g e d g e ( c l k ) THEN
55 IF count = 0 THEN
56 s t a r t o f f r a m e <= ’ 1 ’ AFTER 10 ns ;
57 d a t a i n <= data ( count ∗8 to ( count ∗ 8 ) +7) AFTER 10 ns ;
58 ELSIF count = 60 THEN −− L a s t 32 b i t s i s b e i n g s e n t
59 e n d o f f r a m e <= ’ 1 ’ AFTER 10 ns ;
60 d a t a i n <= data ( count ∗8 to ( count ∗ 8 ) +7) AFTER 10 ns ;
61 ELSIF count > 63 THEN −− No more d a t a send z e r o e s
62 e n d o f f r a m e <= ’ 0 ’ AFTER 10 ns ;
63 d a t a i n <= ” 00000000 ” AFTER 10 ns ;
64 ELSE
65 e n d o f f r a m e <= ’ 0 ’ AFTER 10 ns ;
66 s t a r t o f f r a m e <= ’ 0 ’ AFTER 10 ns ;
67 d a t a i n <= data ( count ∗8 to ( count ∗ 8 ) +7) AFTER 10 ns ;
68 END IF ;
69 count <= count + 1 AFTER 10 ns ;
70 END IF ;
71 END PROCESS;
72 END ARCHITECTURE a r c h ;