Design of Current Limiting Circuit in Low
Dropout Linear Voltage Regulator
LIN Chuan, FENG Quan-yuan
Microelectronics Institute, Southwest Jiaotong University, Chengdu, 610031, China
Email: lin_langai@163.com; TEL: 028-86466365, 028-86466028
Abstract- A current limiting circuit applied in low dropout linear
voltage regulator is designed and simulated. It can limit the
maximum output current and the output short current of the
regulator within 320mA and 30mA, respectively, and well realize
the purpose of overcurrent protection. Prototype of the circuit
can be fabricated using the 0.5µm CMOS process.
Index Terms- Current Limiting; Foldback; LDO; Linear Voltage
Regulator
1. INTRODUCTION
Nowadays, LDO (Low Drop-out) linear voltage regulator
has been widely used in portable equipments. In order to
prevent damage to the IC when an overload is placed or the
output of the regulator is shorted, current limiting circuits are
usually included in LDO linear voltage regulator [1~3]. So far,
there are few papers published about the design of current
limiting circuit, especially foldback current limiting circuits in
LDO linear voltage regulator. It is, however, discussed in
many patents [4~5]. A current limiting circuit used in LDO
linear voltage regulator is designed and simulated in this
paper. This circuit can be fabricated using 0.5µm CMOS
process and can be easily adjusted. The simulation results
show that the circuit can well realize the purpose of
overcurrent protection. It can limit the maximum rated output
current and the output short current within 320mA and 30mA,
respectively.
2. DESIGN OF CURRENT LIMITING CIRCUIT
2.1 Design Requirement of Current Limiting Circuit
A current limiting circuit used in LDO linear voltage
regulator should at least meet the requirements as follows:
This work was supported by National Science Foundation of P. R. China.
Grant No. 60371017
0-7803-9433-X/05/$20.00 ©2005 IEEE.
1. When overcurrent hasn’t taken place, the voltage
regulator should regulate the output voltage UO normally,
and the current limiting circuit should have little effect on
it.
2. A current limiting circuit should first include output
current detecting devices or block to detect if output
current IO has exceeded the maximum rated value.
3. After the current limiting circuit starts up, it should cut
off the negative feedback loop of the regulator. Then the
regulator cannot regulate the output voltage any more.
4. After foldback current limiting circuit starts up, IO will
decrease as UO decreases. As the output is shorted, IO will
be limited to a value much less than the maximum rated
value.
Besides, a good current limiting circuit should take some
other factors into consideration, such as: low quiescent
current and power consumption, few devices, low cost, and so
on.
2.2 Design Principle of Current Limiting Circuit
The current limiting circuit presented in the paper is
showed in Fig. 1. It comprises output current sampling circuit,
constant current limiting circuit and foldback current limiting
circuit. Signals VB1 and VB2 are generated by the
self-biasing circuit of the error amplifier (We only give the
second stage of the amplifier in Fig. 1). The potential of VB2
is constant, and VSG_MP3＝VDD－VB1 holds constant as well.
MN1 and MP2 make up of the second stage of the error
amplifier. AO1 is its input as well as the output of the first
stage and AMP_OUT is its output as well as the output of the
error amplifier. MPW is pass element. LCE is the enable
control signal. When it is at high potential, MP1 is off and the
circuit works normally.
APMC2005 Proceedings
 Fig 1 A current limiting circuit in a LDO linear voltage regulator

2.2.1 Output Current Sampling Circuit decreases, UO drops, and the sampling voltage fed from the
Output current IO is sampled by MP5, whose source and output to the error amplifier is less than the reference voltage
gate are connected with source and gate of the pass element, any more. Thus the output of the first stage of the amplifier
respectively. In addition, we have VD_MP5=VSG_MP7+VOUT. If AO1 is at high potential, and MP2 is cut off, so the negative
the W/L rate of MP7 is designed to be quite large, then feedback in the linear voltage regulator is cut off and the
VSG_MP7 ≈ Vth_MP7，and less difference of VD_MP5 and VOUT will regulator cannot regulate the output normally any longer.
reduce the effect of channel modulation and enable MP5 to
2.2.3 Foldback Current Limiting Circuit
sample output current accurately. The relation of the sampling
According to the relationship of output current ID and VGS
current IS and IO is as follows:
of a MOS transistor, we have:
I S (W / L ) MP 5 VGS _ MN 4 = VGS _ MN 3 + I S R2 − U O
= (1)
I O (W / L ) MPW (2)
2 I S LMN 3 1/ 2
=( ) + Vth _ MN 3 + I S R2 − U O
Therefore, if we make the rate of W/L of MP5 very small, we µ C oxW MN 3
can obtain a small current IS which is proportional to IO.
Make
2.2.2 Constant Current Limiting Circuit
IS (W / L ) M P 5 2 k1 LMN 3 1/ 2
Suppose when the output current is at its maximal rated k1 = = , k2 = ( )
I0 (W / L ) M P W µ C oxWMN 3
value, the corresponding VG_MN2 is V0G_MN2 and the sampling
current is I0S. MN2 and MP3 compose an inverting amplifier, and we get：
whose input and output are the gate of MN2 and INVO,
VGS _ MN 4 = k2 IO1/ 2 + Vth _ MN 3 + k1R2 IO − U O (3)
respectively. When output current is under maximal rated
value, sampling current IS< I0S, VG_MN2< V0G_MN2. At this time,
VGS _ MN 4 = k2 IO1/ 2 + Vth _ MN 3 + k1 R2 IO − RL IO (4)
INVO is at high potential and MP4 is off, so constant current
limiting circuit has no control on the gate of the pass element. If MN4 is on, as VGS_MN4 increases, IMN4 and VSG_MP6= IMN4R1
When the output current exceeds the maximal rated value, IS> will increase as well. If MP6 is on, VAMP_OUT will be lifted up,
I0S, VG_MN2> V0G_MN2, INVO is at relatively low potential, and which causes IO to decrease. So IO is a degressive function of
MP4 is on, which lifts VAMP_OUT up and hence reduces output VGS_MN4 as long as MN4 and MP6 are on. It can be simply
current IO. So IO is limited to a constant value. As load resistor expressed as:
I O = f (VSG _ MP 6 ) = f o g (VGS _ MN 4 ) = h(VGS _ MN 4 )
When output current is under its maximal rated value,
VGS_MN4< VTH_MN4, MN4 is off, IMN4=0, VG_MP6=VDD, so
MP6 is off and foldback current limiting circuit has no control
on the gate of the pass element. When overcurrent takes place,
constant current limiting circuit works first and limits IO to a
constant value. As load RL decreases, UO will also decrease.
From equation (3), we know that MN4 will become on when
UO drops to some value, and as UO drops further, IMN4 will
increase further. When VSG_MP6= IMN4R1> VTH_MP6, MP6 is on,
then foldback current limiting circuit starts to work and lifts
VAMP_OUT up, which causes IO to decrease. Then INVO is at
high potential and MP4 is off again. If RL decreases further,
according to equation (4), VGS_MN4 will increase and cause IO
to decrease. And at last, equation (4) and (5) will be in
balance. In a word, IO will decrease as RL and UO decreases,
so we achieve the purpose of foldback current limiting. When
the output is shorted, the value of IO is minimal.
3. SIMULATION RESULTS AND DISCUSSION
The designed current limiting circuit is applied in a LDO
linear voltage regulator, for which the regulated output
voltage is 1.8V, the maximal rated value of IO is 320mA and
the output short current is 30mA. The simulation results by
HSPICE are showed in Fig. 2 and Fig. 3.
Fig. 2 The relationship of output voltage and output current
(5)
Fig. 3 The relationship of quiescent current and output current
Fig. 2 shows the relationship of UO and IO in LDO linear
regulator. From Fig. 2, we can see that when overcurrent takes
place, constant current limiting circuit works first and limits
IO to 320mA. Then UO drops as RL decreases. As UO drops to
about 1.4V, foldback current limiting circuit starts up and
reduces IO further. The short output current is 30mA. Fig. 3
shows the relationship of quiescent current Iq of the current
limiting circuit and output current IO. The circuit has only two
current limbs which are both proportional to sampling current
IS. So very low Iq which is proportional to IO is achieved. We
can see from Fig. 3 that Iq is less than 8.5µA when IO is less
than 200mA. Besides, the circuit has some extra advantages
as follows:
1. Few devices and low cost. The current limiting circuit
comprises only 8 MOS transistor and 2 resistors, which
can reduce the size of the chip and hence reduce the cost.
2. The circuit is easy to adjust. By adjusting W/L rate of
MN2, MN3 and MP3, the maximal rated output current
can be adjusted; by adjusting W/L rate of MN3,
MN4, MP6 and R1, R2, output short current can be
easily adjusted.
4. CONCLUSION
The circuit designed in the paper has solved some
critical techniques in current limiting circuit. When used
in a LDO linear regulator, it can well realize the purpose
of overcurrent protection.
REFERENCES
[1] Bang S. Lee, “Understanding the Terms and Definitions of LDO Voltage
Regulators,” Texas Instruments Application Report，Oct. 1999
[2] Bang S. Lee, “Technical Review of Low Dropout Voltage Regulator

Operation and Performance,” Texas Instruments Application Report，Aug.

1999
[3] Chester Simpson, “Linear and Switching Voltage Regulator
Fundamentals,” National Semiconductor Application Note. 1999
[4] Wen Li Luo, “Current Limit Protection Circuit for a Voltage Regulator,”
United States Patent, 6466422 B2, Oct.15, 2002
[5] Robert M. Paterno. “Booster circuit for foldback current limited power
supplies,” United States Patent, 5994884, Nov.30, 1999