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Using a Personal Computer to Program the

AT89C51/C52/LV51/LV52/C1051/C2051

8-Bit
Introduction one or two, respectively. If the parallel
This application note describes a per- port is not specified, the program will
respond with an error message. The
Microcontroller
sonal computer-based programmer for
the AT89C51/C52/LV51/LV52/C1051/C2051 control programs are menu-driven, and
provide the following functions:
with Flash
Flash-based Microcontrollers. The pro-
grammer supports all flash memory Chip Erase
microcontroller functions, including code Clear code memory to all ones. The suc-
read, code write, chip erase, signature cessful operation of this function is not Application
read, and lock bit write. When used with automatically verified.
the AT89C51/C52/ LV51/LV52, code
Program from File
Note
write, chip erase, and lock bit write may
be performed at either five or twelve Write the contents of the specified file
volts, as required by the device. into device memory. The user is
prompted for the file name, which may
Devices sporting a “-5” suffix are
require path and extension.
intended for operation at five volts, while
devices lacking the suffix operate at the The file is expected to contain binary
standard twelve volts. data; hex files are not accepted. The first
byte in the file is programmed into the
The programmer connects to an IBM
first location in the device. Successive
PC-compatible host computer through
bytes are programmed into successive
one of the host's parallel ports. Required
locations until the last location in the
operating voltages are produced by an
device has been programmed or until
integral power supply and external, wall-
the data in the file has been exhausted.
mounted transformer.
Programming occurs regardless of the
Software existing contents of device memory; a
Software for the programmer is available blank check is not automatically per-
by downloading it from the Atmel BBS at formed. After programming, the contents
408-436-4309. of device memory are not automatically
The programmer is controlled by soft- verified against the file data.
ware running on the host. The Each programmed location in the device
AT89C51/C52 and C1051/C2051 have receives the maximum programming
dedicated control programs, which were time specified in the data sheet. This is
written in Microsoft C. Programs dedi- done because timing is enforced by soft-
cated to the AT89LV51/LV52 do not ware; the programming status informa-
exist; these devices are supported by the tio n p ro vi ded by DATA po ll in g a nd
programs for the AT89C51/C52, respec- RDY/BSY is not utilized.
tively. In the text below, all references to The control program provides no visual
the AT89C51/C52 may be assumed to indication that programming is in
apply to the AT89LV51/LV52 as well. progress. The main menu is redisplayed
All programmer control programs are when programming is complete.
invoked from the DOS command line by
entering the program name followed by 0285D-B–12/97
“LPT1” or “LPT2” to specify parallel port

5-3
Verify against File invoked and restored to its original state before the pro-
Compare the contents of code memory against the con- gram terminates. In order to guarantee that the program is
tents of the specified file. The user is prompted for the file not exited before the timer configuration is restored, the
name, which may require path and extension. CTRL-C and CTRL-BREAK keys are disabled. This means
The file is expected to contain binary data; hex files are not that the program cannot be aborted except by specifying
accepted. The first byte in the file is compared to the first the exit option at the main menu or by rebooting the sys-
location in the device. Successive bytes are compared to tem.
successive locations until the last location in the device has The timer control code is provided as an 8086 assembly
been compared or until the data in the file has been language module, which is linked with the compiled control
exhausted. program. The granularity of the timer is 0.838 microsec-
Locations which fail to compare are displayed by address, onds, but the minimum practical delay is system- and soft-
with the expected and actual byte contents. If there are no ware-dependent. The timer code ensures that the delay
compare failures, nothing is displayed. produced will not be of shorter duration than requested.
The control programs provided for the AT89C1051/C2051
Save to File
are system independent.
Copy the contents of device memory to the specified file.
The user is prompted for the file name, which may require Programmer
path and extension. The number of bytes in the resulting The programmer circuitry (see Figures 1 and 2) consists of
file is the same as the number of memory locations in the the host interface and switchable power supplies. The sig-
device. nal sequencing and timing required for programming is
Blank Check generated by the host under software control. A 40-pin ZIF
Verify that the contents of device memory are all ones. socket is provided for programming the AT89C51/C52; the
Only pass or fail is reported; the addresses and contents of 20-pin ZIF socket accommodates the AT89C1051/C2051.
failing locations are not displayed. Note that the power and ground connections and bypass
capacitors required by the TTL devices are not shown on
Read Signature the schematic.
Read and display the contents of the signature bytes. The
number of signature bytes and their expected contents var- Power for the programmer circuitry and the AT89C51/C52/
ies between devices. Refer to the device data sheet for C1051/C2051 is provided by a fixed five volt supply. A sec-
additional information. ond supply provides either five or twelve volts, selectable,
for use during programming. The addition of a transistor to
Write Lock Bit 1 the output of the variable supply provides a third level,
Write Lock Bit 2 ground, for use when programming the AT89C1051/C2051.
Write Lock Bit 3 The resistor values utilized in the variable power supply cir-
Set the indicated lock bit. Note that the AT89C1051/C2051 cuit were determined using the equations presented in the
contain only two lock bits, while the AT89C51/LV51 and LM317 voltage regulator data sheet. Power supply ramp
AT89C52/LV52 contain three lock bits. The state of the lock rates are accommodated by the host software. For 5 V-
bits cannot be verified by direct observation. VPP programming, the devices must be ordered from the
Exit factory as an AT89CX-XX-5 (not available with the
Quit the programmer control program. AT89C1051/2051).
The programmer is connected to the host with a 25-con-
System Dependency
ductor ribbon cable. To minimize the effect on signal integ-
The control programs for the AT89C51 and AT89C52 come
rity, the length of the cable should be as short as possible,
in two flavors: host system-dependent and host system-
preferably not exceeding three feet.
independent. System-dependency results from the use of
software timing loops to enforce required delays, the dura- Parallel Interface
tion of which will vary between host systems running at dif- The original parallel interface provided by IBM was proba-
ferent speeds. The code provided was tested on an 80386- bly not intended to support bidirectional data transfers.
based system running at 33 MHz, and may require modifi- However, due to the way in which the interface was imple-
cation for use on other systems. This method was chosen mented, bidirectional transfers are possible. Over the
for its simplicity. years, many products have appeared which exploit this
Host system-independence is achieved by using the Pro- capability.
grammable Interval Timer embedded in the system hard- Unfortunately, many system and interface card manufactur-
ware to enforce time delays independent of system speed. ers have not faithfully cloned the IBM design, resulting in
The timer is reconfigured when the control program is bus contention when the peripheral attempts to drive return

5-4 Microcontroller
Microcontroller

data into the interface. Usually the peripheral drivers can control feature. As a result, parallel interfaces utilizing
overpower the interface drivers and the peripheral works, these chips cannot be assumed to be bidirectional.
though this is not considered a good design practice. If the programmer writes devices, but fails to verify, or the
Most parallel interfaces are now implemented in a single signal levels at the interface don't meet TTL specifications,
chip, such as the 82C411 or 16C452. These chips allow the parallel interface may be incompatible with the pro-
their output drivers to be disabled under software control, grammer. A design is provided (see Figure 4 and Figure 5)
providing true bidirectional operation. The programmer for a parallel interface which supports bidirectional opera-
software automatically enables bidirectional operation tion and is compatible with the programmer. This design is
when used with parallel interfaces utilizing the 82C411, simple, requiring only six ICs. The interface can be
16C452, or similar chips. strapped to appear as LPT1 (addresses 378-37F hex) or
Note that these chips also possess a mode control pin LPT2 (278-27F hex) and will be recognized by the POST
which must be at the correct level to enable the directional when the host system is powered up. Due to its simplicity,
the parallel interface CANNOT be used as a printer inter-
face.

5-5
Figure 1. AT89 Series Programmer Interface

Note: 0.1 µF bypass caps on all ICs

5-6 Microcontroller
Microcontroller

Figure 2. Power Supply for AT89 Series Programmer

5-7
Figure 3. AT89 Series Programmer Socket Wiring

5-8 Microcontroller
A3 A28 1 U?
A4 A27 2
A5 A26 3
A6 A25 4 U?A
8 2 A Y0 4
5 3 DRD*
U?B Y1 5
B 6
6 Y2
A24 3 4 11 1 G Y3 7
A7
12 74LS139
74LS30
74LS04

U?C U?B
JP? 14 A Y0 12 DWR*
LPT2
A23 5 6 1 13 B Y1 11
A8
2 15 G Y2 10 CWR*
3 Y3 9
74LS04 LPT1 74LS139
HEADER 3

A22
A9

U?D

A11 9 8
AEN

74LS04
Figure 4. A Parallel Interface Supporting Bidirectional Operation

A30
A1

B14
IORD* B13
IOWR*

ISA bus
connections
Note: 0.1-µF bypass caps on all ICs.
U?E

11 10

74LS04

U?F

13 12

74LS04
Microcontroller

5-9
Figure 5.
5-10

U?A
Microcontroller

B2 1 2
RSTDRV

74LS04
R?
SD0 A9 3 D0 Q0 2 1 16 D0
A8 4 5 2 15 D1
SD1 D1 Q1
A7 7 Q2 6 3 14 D2
SD2 A6 8 D2 9 4 13 D3
SD3 D3 Q3 12
A5 13 Q4 12 5 D4
SD4 D4 6 11
SD5 A4 14 Q5 15 D5
A3 17 D5 16 7 10 D6
SD6 D6 Q6 8 9
A2 18 Q7 19 D7
SD7 D7
1 0C 8 x 120 ohm
11 >CLK
ISA bus
connections P?

1
14
U? 2
18 2 15
Y1 A1 3
17 Y2 A2 3
16 4 16
15 Y3 A3 4
Y4 A4 5
14 6 17
Y5 A5 7 5
13 Y6 A6
12 8 18
Y7 A7 6
11 Y8 9
A8 19
7
G1 1 20
G2 19 8
21
74LS541
9
DWR* 22
10
DRD* 23
11
24
12
25
U? R? 13
4 2
D1 Q1 3 1 16 STROBE*
Q1 2 15 AUTOFD*
5 7
D2 Q2 3 14 INIT* DB25-S
Q2 6
4 13 SLCTIN*
12 D3 Q3 10 5 12
Q3 11 6 11
13 D4 15
Q4 14 7 10
Q4 8 9
CWR* 9 >CLK
1 8 x 120 OHM
CLR
74LS175

Note: 0.1-µF bypass caps on all ICs.

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