Limitation of NMOS
inverter
Example 16.3
N-Channel Depletion-Mode
MOSFET
• In n- channel depletion
mode MOSFET, an n-
channel region or
inversion layer exists
under the gate oxide
layer even at zero gate
voltage and hence term
depletion mode.
• A negative voltage
must be applied to the
gate to turn the device
off.
• The threshold voltage
is always negative for
this kind of device.
NMOS Inverter with Depletion Load
• This is an alternate form of
the NMOS inverter that uses
an enhancement-depletion
MOSFET load device with gate
and source terminal connected.
• This inverter has the
advantage of VO= VDD, as well
as more abrupt VTC transition
region even though the W/L
ratio for the output MOSFET
is small.
• The term depletion mode
means that a channel exists
even with zero gate voltage.
NMOS Inverter with Depletion Load
With the gate and source
are connected, VGSL=0.
Since the threshold voltage
of load transistor is
negative, we have
VGSL=0>VTNL= -(VTNL)
This implies that load
MOSFET is always active.
For an active device we can
write
VDSL≥VGSL – VTNL= -VTNL=VTNL
becauseVGSL=0.
1

NMOS Inverter with Depletion Load (cont.)
Case I: when VI<VTND (drive is
cutoff): No drain current conduct in
either transistor. That means the
load transistor must be in the linear
region of the operation and the
output current can be expressed as
fellows
iDL(linear)=KL[2(VGSL - VTNL)VDSL -
VDSL2]
Since VGSL=0, and iDL=0
0=-KL[2VTNLVDSL + VDSL2]
Which gives VDSL=0 thus
VO= VDD
This is the advantage of the depletion
load inverter over the
enhancement load inverter.
Two transition points for NMOS depletion
load inverter
In the Figure the point B and C are
corresponding the two transition points: one
for the load and one for the driver.
The transition point for the load is given by,
VDSL=VDD-VOt
Also VDSL=VGSL-VTNL
By equating the relations we get
VDD-VOt=VGSL-VTNL
Since VGSL=0
V0t=VDD+VTNL
As we know VTNL is negative. This implies that
Vot<VDD
The transition point for the driver is given by
VDSD=VGSD-VTND
Or in terms of input and output voltage we can
write
VOt=VIt-VTND
NMOS Inverter with Depletion Load
(Cont.)
Case II: When VI>VTND (driver turns
on)
and is biased in the saturation region;
however, the load is biased in the
nonsaturation region.
Under the condition we can write
iDD=IDDL
KD(VGSD-VTND)2 =KL[2(VGSL - VTNL)VDSL
- VDSL2]
Substituting VGSD=VI, VGSL=0, and
VDSL=VDD-VO
Yields
• KD(VI-VTND)2 =KL[2(-VTNL)(VDD -
VO)-VDD – VO)2]
Which relates the input and output
voltage as long as the driver is
biased in saturation region and load
is biased in nosaturation region.
When both devices (driver and load) are in
saturation region
When both devices are biased in saturation
region the Q point lies between point B
and C on the load curve, and
K (V -VTND) 2 = KL(VGSL-VTNL)2
OrD GSD
√KD/KL(VI-VTND)=-VTNL
Implies that input voltage is constant as
the Q-point passes this region.
If we further increased the input voltage,
the drive is biased in the nosaturation
region while load is in saturation region.
The Q-point moves between C and D on
the load curve. For the input/output
characteristics we equate two drain
current equation
KD[2(VGSD - VTND)VDSD - VDSD2] = KL(VDSL -
VTNL)2
Which becomes
KD/KL[2(VI-VTND)VO-Vo2]=-(-VTNL)2
Implies that input and output voltages are
not linear in this region.
2
VT Characteristics of NMOS Inverter with
Depletion Load

The Figure demonstrate in present configuration more abrupt

VTC transition region can be achieved even though the W/L
ratio for the output MOSFET is small.

3
 Transient Analysis of NMOS inverters Transient Analysis of NMOS inverters (cont.)

• The source of capacitance • The fall time relatively

CT2 and CT3 are the
transistor input short, because the load
capacitances and parasitic capacitor discharges
capacitances due to
interconnect lines between through the large drive
the inverter stages. transistor.
• The constant current over (W/L)L=1
a wide range of VDS • The raise time is longer (W/L)D=4
provided by the depletion
load implies that this type because the load F-0.5pF
of inverter switch a capacitor is charged by
capacitive load more
rapidly than the other two
the current through the
types inverter smaller load transistor.
configurations.

The rate at

enhancement load depletion load

4
1160µW 825µW 200µW

5

16.2: NMOS Logic Circuit
NMOS logic circuits are constructed by
connecting driver transistor in parallel,
series or series-parallel combinations
to produce required output logic
function
NMOS NOR gate
• NMOS NOR gate can be constructed by
connecting an additional driver transistor in
parallel with a depletion load inverter.
• The output of a NOR gate is only high when
both inputs are at logic 0(low)i.e.
• If A=B=logic 0,
Then both driver transistors MDA and MDB are
in cut off mode and
V0=VDD (logic 1)
For all other possible inputs V0= 0 (logic 0).
For example,
If A=high (logic1) and B=low (logic0)
Then MDB is in cut off mode and remaining
circuit behave as depletion load inverter.
However, when both driver transistors are
in active mode the value of the output
voltage logic 0) is changed.

NMOS NOR gate: Special case when all

inputs are at logic 1 Concept of effective width to length ratios
When A=B=logic 1 Parallel combination
Both driver transistors are switched into nonsaturation region Series combination
and load transistor is biased in saturation region. We have
iDL=iDA+iDB
By substituting the values of current equation we can write as,

KL(VGSL-VTNL)2 = KDA[2(VGSA - VTNA)VDSA - VDSA2] + KDB[2(VGSB

-VTNB)VDSB - VDSB2]

Suppose two driver transister are identical, which implies that,

KDA=KDB=KD
VTNA=VTNB=VTND
As we know VGSL=0
Also from figure VGSA=VGSB=VDD
VDSA=VDSB=V0
By substituting all these parameters we can write above equation as,

(-VTNL)2 = 2(K /K )[2(V

D L DD-VTND)V0-VO
2)

Conclusion: The above equation suggested that when the both the
driver are in conducting mode, the effective aspect ratio of the
NOR gate is double. This further suggested that output voltage
becomes slightly smaller when both inputs are high. Because For the NAND gate the effective
higher the aspect ratio lower the output.
For the NOR gate the effective
width of the drivers transistors length of the driver transistors
doubles. That means the effective doubles. That means the effective
aspect ratio is increased. aspect ratio is decreased.
.

6
 Next Lecture

• Next lecture
– CMOS inverter – a static view
• Reading assignment – Neamen, 16.3, 16.3.1,
16.3.2