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AD7170/AD7171 Features
• RMS noise: 6.9 μV Applications
• Weigh scales • Industrial process control
• INL: ±0.1 LSB at 12 bits (AD7170),
• Pressure measurement • Portable instrumentation
±0.4 LSB at 16 bits (AD7171)
• Power consumption:
110 μA (5 μA in power-down mode)
• Ease of use, fixed sampling rate,
no programming required
• 3 mm × 3 mm LFCSP
• Pricing:
• AD7170 — $0.95
• AD7171 — $1.15
www.analog.com/v10DataConverters
Continuous Time ∑-∆ ADC Architecture Offers a Number of Benefits for Wider
Bandwidth Applications
∑-∆ ADCs have long been the architecture of choice for applications requiring both high resolution and high accuracy. The standard
product implementation of this converter architecture has been within a discrete time domain and limited to a few MHz of bandwidth.
However, the continuous-time ∑-∆ (CTSD) architecture can provide the advantages of its discrete time counterpart, in addition to a
wider bandwidth, inherent antialiasing, and an easy to drive input structure.
Solution
A key benefit of the CTSD architecture, utilized in the AD926x family of converters from ADI, is the inherent alias immunity that it
offers. Since the sampling operation of a CTSD-based ADC occurs at the output of the internal loop filter, which is the same point
where quantization noise is injected into the loop, aliases are attenuated by a similar mechanism, which attenuates quantization
noise. This process, coupled with a 640 MSPS high speed modulator and a 32× oversampling ratio (OSR) for a 10 MHz input signal,
ultimately eliminates the need for antialiasing filters. In addition, the continuous time loop filter architecture enables a passive
1 kΩ input impedance and results in a –3 dBm input power requirement for a 2 V peak-to-peak input voltage swing that significantly
relaxes the requirements of the ADC driver amplifier. This feature contrasts with a typical switched capacitor input structure that
represents a significant challenge to filter and drive.
The AD926x CTSD ADCs achieve a high dynamic range of 86 dB and an SNR of 84.5 dBFS up to a 10 MHz analog input bandwidth.
The ADC provides an extremely low 15 dB noise figure, which is nearly a 7 dB improvement over current state-of-the-art wideband
converters. The low noise figure reduces the front-end gain, thereby relaxing linearity requirements in an RF system. In addition, the
high dynamic range makes it possible to eliminate the automatic gain control commonly employed in many communication systems.
In emerging applications, such as wireless communications, medical imaging, and radar systems, accurate and high speed
signal conversion is a key requirement. High SNR and wide bandwidth, in addition to a reduction in requirements of system level
components, make CTSD-based ADCs an ideal fit for these applications. An example of this is illustrated by using the AD9262 in
combination with ADI’s high performance ADL5382 quadrature demodulator and AD9520 clock generation and distribution products
to implement a 20 MHz bandwidth, high
performance, low part count 700 MHz to
AD9262 Dual ADC in I/Q Downconverter Application
2.7 GHz direct conversion receiver.
ADL5382 AD9262
I/Q DEMODULATOR 16-BIT CTSD ADC
AD9262 Features
ADC
• SNR: 83 dB (85 dBFS) to 10 MHz input
FPGA DIGITAL
PROCESSING
AMP AMP 90° PHASE
• SFDR: 87 dBc to 10 MHz input MAIN Rx
SHIFTER
Webcast Series
Solution
The AD9148 DAC is designed to provide support for multiantenna wireless
communications standards requiring the large bandwidths demanded by digital
predistortion (DPD) transmit systems. This 4-channel, 16-bit DAC has a
1 gigasample per second (GSPS) data rate that is 25% faster than competing dual
channel devices. Additionally, the new highly integrated converter cuts component
count in half relative to dual channel DACs. Its 12 mm × 12 mm BGA package
size allows designers of W-DCMA, CDMA2000, TD-SCDMA, GSM, and WiMAX
infrastructure equipment and other wireless applications to reduce printed circuit
board space by 20%. For more information, visit www.analog.com/pr/AD9148.
Applications
• Wireless infrastructure • Digital high or low IF synthesis
AD9148 Features • MIMO/transmit diversity • LTE, TD-SCDMA, WiMAX, W-CDMA,
CDMA2000, GSM
• Single carrier W-CDMA ACLR: 80 dBc @ 150 MHz IF
• Channel-to-channel isolation: >90 dB
• Novel 2×, 4×, and 8× interpolator eases data interface
• On-chip fine complex NCO allows carrier placement
anywhere in DAC bandwidth
• Pricing:
• AD9148 — $58.60
Solution
To achieve fast digital-to-analog conversion, current output DACs are the solution of choice for mixed-signal board designers.
This DAC architecture minimizes the output resistance, allowing faster settling time. Led by communications requirements, current
DACs have achieved the required high update rates without compromising static accuracy.
The AD9726 is a true 16-bit accurate current output DAC with a maximum update rate of 400 MSPS, combining a single or double
data rate LVDS data interface with a factory calibrated 20 mA differential current output for improved INL and DNL performance.
The AD9726 operates from 2.5 V and 3.3 V power supplies.
The dual AD9117 features two 14-bit accurate current output DACs operating up to 125 MSPS update rate, integrating a double
data rate CMOS digital interface with internally calibrated 20 mA differential current outputs. The AD9117 can operate with supplies
between 1.8 V and 3.3 V.
Webcast Series
Solution
Now in full production, ADI’s newest family of high voltage DACs AD5501 DAC Block Diagram
addresses these concerns with the introduction of the AD5501
VLOGIC VDD
(single) and AD5504 (quad) devices, which integrate a 12-bit
DAC, an on-chip high voltage output amplifier, and a precision
reference. In addition, a temperature sensor with alarm function PRECISION AD5501
REFERENCE
and power saving features are also incorporated on chip. The POWER-ON
RESET 1713k𝛀
AD5501/AD5504 provide a pin-selectable 0 V to 30 V or 0 V to 122.36k𝛀
VFB
–0.5 V. The low power, high speed serial interface with readback SYNC
capability can handle clock speeds up to 30 MHz. The AD5501/ SCLK
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
AD5504 operate over a wide temperature range of −40°C to SDI INPUT
CONTROL
SDO LOGIC
+105°C and are available in a 16-lead TSSOP. ALARM
TEMPERATURE
SENSOR
Understanding Sampled Data Systems (Parts I & II) Complementary components for AD5501/AD5504
at www.analog.com/webcasts. high voltage output DACs:
• ADSP-BF531 DSP
• ADCLK846 clock buffer for low clock jitter
Tested Circuits from the Lab Design Resource Provides Faster Time
to Market and Lowers Risks
Featured Circuits from the Lab
Circuit Note CN-0149, 40 Channels of Programmable Industrial Level Output 15V 5V
Span Using the AD5370 16-Bit Voltage Output DAC 0.1𝛍F
10𝛍F 0.1𝛍F
This circuit is a multichannel DAC configuration with different output spans on 5V
ADR435
groups of channels. It utilizes the AD5370 to provide 40 DAC channels with VDD DVCC
16 bits of resolution. The AD5370 is configured to have eight channels with an 0.1𝛍F
VREF0
VOUT0
±10V
output span of ±10 V and 24 channels with an output span of −4 V to +8 V. ADR423
3V VOUT7
AD5370
The AD5370 is the industry’s only 40-channel DAC offering these industrial signal VOUT8
–4V TO +8V
VREF1
level outputs and the flexibility of multiple output spans with 16-bit resolution. 0.1𝛍F
VOUT39
The figure shows a typical configuration for the AD5370 using two external VSS SIGGND AGND DGND
references. The nominal output span for the AD5370 is four times the reference 0.1𝛍F
voltage. The default offset DAC register values for the AD5370 allow for an output 10𝛍F
Solution
Analog Devices has developed a broad portfolio of clock buffers that have been designed to help designers solve this clock integrity
challenge. With a clock buffer inserted between the converter and the system clock tree, jitter figures on the order of 50 fs to 75 fs
for LVPECL fanout buffers and extremely low skew on the order of 9 ps (picoseconds) are achieved. These buffer ICs also provide up to
12 channels of low jitter clock fanout.
Typical Low Jitter ADC Clock Tree
The ideal clock signal for a data converter features not only
low phase noise/jitter, but also very sharp rise and fall edges. LVPECL
AD9262 ADC
As clocking speeds continue to increase, the challenge to
LVPECL
achieve a high quality square wave clock signal grows along AD9523/AD9524
AD9262 ADC
ADCLK9xx
with that speed. The ADCLK9xx family can provide very fast AD9520
edges with extremely little impact on the noise of the clock LVPECL
AD9262 ADC
signal when located in close proximity to the converter.
To view the complete ADCLK9xx clock buffer family, visit OTHER ADCs,
FPGA, SERDES, ETC.
www.analog.com/ADCLK9xxFamily.
ADC Driver Amplifier Dissipates Just 7.5 mW, Enabling Low Power SAR Applications
DC converter technology has continued to steadily advance in noise and distortion performance while simultaneously lowering power
dissipation. Converters such as ADI’s AD7986, an 18-bit SAR ADC sampling at 2 MSPS, can digitize up to 1 MHz of input bandwidth
and operate on just 15 mW of power. A challenge faced by many designers today is finding a driver amplifier that is capable of
delivering adequate noise performance at a correspondingly low power point.
Solution
Analog Devices has developed the ADA4940, an ultralow distortion ADC driver amplifier to provide the solution. Dissipating just
7.5 mW, this device is capable of delivering true 18-bit ENOB performance over a dc to 2 MHz bandwidth. With THD greater than
100 dB and RTO noise of just 9.5 nV/√Hz, the ADA4940 enables full ADC performance at a power point commensurate with the class
of SAR converters that it is intended to drive. Fully differential and balanced, the ADA4940 is also capable of dc level translation to
interface between sensors and ADC cores.
The ADA4940-1 is a single-channel device in an 8-lead SOIC and a 3 mm × 3 mm, 16-lead LFCSP. The ADA4940-2 is a dual-channel
device in a 4 mm × 4 mm, 24-lead LFCSP.
Driver Amplifier and 18-Bit SAR ADC Application
10k𝛀 10k𝛀
ADA4940-1 Features VREF
5V 10𝛍F
• Extremely low harmonic distortion: 1k𝛀 2.5V
–95 dBc @ 2 MHz
• Low input noise: 3 nV/√Hz VIN
1k𝛀
+ REF VDD
IN+
VOCM
• Very low power consumption: ADA4940-x AD7356
DIGITAL
OUTPUT
7.5 mW (5 V supply) 100nF IN–
– GND
1k𝛀
• Single-ended-to-differential or differential-
to-differential operation
1k𝛀
• Pricing:
Applications
• ADA4940-1 — $1.79 • Low power ADC drivers • Industrial process controls
• ADA4940-2 — $2.99 • Single-ended-to-differential converters • Portable electronics
• Medical imaging