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flops with various CMOS logic families, GDI and adiabatic low
power design techniques.
I. INTRODUCTION The Clk-Q delay is the delay measured from the active clock
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Power consumption has become a critical concern in both
high performance and portable applications. There are three
major sources of power dissipation in a CMOS circuit.
edge to the output. Setup and hold times are defined as the
amount of time the synchronous input (D) must be stable
before and after active edge of clock (Figure.1). The flip-flop
environment in a digital system, Figure.2 has to satisfy
Ptotal = Pswitching + PSC + Pleakage (1) equation (2) for correct operation. The clock period (T) must
be greater or equal to the sum of worst-case Clk-Q delay, tClk-
Ptotal is the total power dissipation of a CMOS circuit, Pswitching Q, flip-flop setup time (tsetup), maximum combinational logic
is the switching power, PSC is the short circuit power, and delay (tlogic) and relative clock skew (tskew). The flip-flop delay
Pleakage is the leakage power. has to satisfy maximum delay restriction given by equation
Paper [1] discusses about the power consumption in the (2).
digital circuits which is proportional to the square of supply D =1.05.tClk-Q + tsetup < T – tlogic – tskew (2)
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voltage. Technology scaling can be used to reduce power
consumption in which the threshold voltage is scaled in
proportion to the supply voltage. Due to this scaling, leakage
currents have become one of the main power consumers and
this leads to substantial increase in sub-threshold leakage
power.
In paper [2], S. Kang discusses about the elements of low
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Figure 3.
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Transmission gate flip-flop
Flip-Flop Power
No. of transistors
Type (µW)
SDFF 23 262
HLFF 20 250
CCFF 26 185
LSDFF 28 132
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additional high power-supply voltage to reduce the leakage 1) High speed, due to small node capacitances.
current. A single-clock flip-flop for half-swing clocking 2) Low power dissipation, as a result of reduced
doesn‟t need high power-supply voltage but has a long number of transistors.
latency. HLFF and SDFF consume large amounts of power 3) Lower interconnection effect, due to smaller
due to redundant transitions at internal nodes. To reduce the area.
redundant power consumption in internal nodes of high-
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performance flip-flops a Conditional capture flip-flop has been
introduced. However, HLFF, SDFF and CCFF use full-swing
clock signals that cause significant power consumption in the
clock tree. A low-swing clock double-edge triggered flip-flop
In spite of these advantages of PTL, there are two main
drawbacks. First, the threshold voltage across the single
channel pass transistors result in reduced drive and hence
slower operation at reduced voltages. Second, since the high
(LSDFF) is discussed and is as shown in Figure.9. input voltage level is not VDD the PMOS device in inverter is
not fully turned off. In order to overcome these problems some
sort of PTL techniques have been discussed [5].
Transmission gate CMOS (TG) uses transmission gate logic to
realize complex logic functions using less number of
transistors. It solves the problem of low logic level swing by
using PMOS as well as NMOS.
Complementary pass transistor logic (CPL) uses NMOS pass
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transistor logic with CMOS output inverters. Small stack
height and internal node low swing are important features but
it suffers from static power consumption due to the low swing
at the gates of the output inverters.
Double pass transistor logic (DPL) uses complementary
Figure 9. LSDFF transistors to keep full swing operation and reduce the dc
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Figure 10. Basic GDI cell Figure 11. D – Flip flop implementation in GDI technique
Table II shows how various logic functions implemented with Paper [7] discusses about the operation of Flip-Flops
GDI cell. It enables simpler gates, transistor count and lower implemented in GDI Technique in sub-threshold region. When
power dissipation. the supply voltage is decreased to reduce power consumption
then, this leads to increase in sub-threshold leakage power.
TABLE II. LOGIC FUNCTIONS IMPLEMENTED WITH GDI CELL
Therefore to reduce the energy we go for sub-threshold
N P G D Function circuits.
Sub-threshold current of an MOSFET transistor occurs
„0‟ B A A‟B F1 when gate-source voltage (VGS) of transistor is lower than the
B „1‟ A A‟+B F2 threshold voltage (VTH). When VGS is greater than VTH,
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majority carriers are repelled from the gate area of the
„1‟ B A A+B OR transistor and a minority carrier channel is created. This is
called as strong inversion. When VGS is lower than VTH
B „0‟ A AB AND
there are less minority carriers, but their presence comprises a
C B A A‟B+AC MUX current and the state is known as weak inversion.
Operation of digital circuits in the sub-threshold region,
„0‟ „1‟ A A‟ NOT utilizes this current, minimizing power consumption in low-
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Most of these functions are complex (6 – 12 transistors) in
CMOS as well as in PTL implementations but very simple
(only 2 transistors per function) in GDI design method. Table
frequency systems. Sub-threshold circuit operation is driven
by currents much weaker than standard strong-inversion
circuits, characterized by longer propagation delays and
limited to lower frequencies.
3 shows the implementations of AND, OR and XOR gates in A block diagram of the basic GDI flip-flop in sub-threshold
GDI, CMOS and PTL. region is as shown in Figure.13. The design is composed of
pair of latches comprising a GDI multiplexer (see Figure.12)
TABLE III. AND, OR , XOR GATES IN GDI ,CMOS AND PTL and cross-coupled pair of inverters. GDI multiplexers are
composed of a single pair of transistors thus reducing area,
power consumption and clock load.
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The required setup time (tsu) is the path delay of the input There are two types of energy loss in quasi-adiabatic circuits,
signal (D) to the feedback port of Mux1. Accordingly, the adiabatic loss and non-adiabatic loss. The adiabatic loss occurs
setup time is given as when current flows through un-ideal switch, which is
tsetup = tP1+ tinv1+ tinv2 (3) proportional to the frequency of the power-clock. If any
A modification can be implemented to this basic voltage difference between the two terminals of a switch exists
architecture to improve the setup time and reduce area. The when it is turned on, non-adiabatic loss occurs. The non-
architecture is as shown in Fig.14. This can be achieved by adiabatic loss, which is independent of the frequency of the
removing the first stage feed back inverter and passing it to power-clock, is proportional to the node capacitance and the
second stage. square of the voltage difference. But CPAL circuits have
internal dissipation to charge and discharge nodes. It also has
adiabatic dissipation to charge the output load capacitance.
Paper [11] presents the adiabatic CPL circuits that consists
of pure NMOS transistors and use CPL blocks for evaluation
and bootstrapped NMOS switches for driving output loads, so
that non-adiabatic loss of output nodes is eliminated. A CPL
inverter using DC power supply is as shown in Figure.15.
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This design comprises of 10 transistors plus a delay element
that can be implemented with a resistor or a transistor. This
architecture takes the advantage of the feedback in second
stage making first stage redundant. This way the transistor
count is reduced achieving smaller area and the setup time can
be reduced by the addition of inverter. The new setup time is
given as,
tsetup = tP1 + tInv1 + tN3 + tInv2 - tDelay
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In other words, tsetup can be reduced by adding larger delay. To
eliminate glitching a minimum setup time of t P1 + tInv1 should
Figure 15. CPL inverter using DC power supply
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Adiabatic CPL hasn‟t non-adiabatic loss on output nodes
because its operation for output loads is a full adiabatic loss
therefore adiabatic CPL circuits consume less power than TABLE IV. COMPARISON RESULTS
other techniques.
The implementation of two-input AND/NAND, OR/NOR Sequential
GDI (Sub
and XOR/XNOR gates and multiplexer using Adiabatic Circuits (D GDI ACPL
threshold)
Flip-Flop)
VI. CONCLUSION
In this paper different flip-flop topologies has been reviewed
and evaluated based on the performance metrics like area,
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power, delay and transistor count. But the proposed flip-flops
have the disadvantages of transistor count, delay and power
dissipation. So a new technique, Gate-Diffusion-Input (GDI)
technique is adopted for reducing the transistor count. To
reduce the power dissipation, adiabatic low power techniques
Figure 17. Adiabatic CPL two-input gates (a) AND (b) OR (c) XOR and (d) have been presented. ACPL can be used in flip-flops because
multiplexer of fewer transistors and for high performance. The GDI
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and Communication Engineering from Malineni Lakshmaih Engineering
College Ongole, India in 2008. She is now pursuing her Master of Technology
(M.Tech) in VLSI Design at VIT University, Vellore, Tamil Nadu, India. Her
interest includes Digital Design, ASIC Design, Low Power IC Design and
ES RFIC Design.