IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO.

4, APRIL 2010 943

High-Efficient Multilevel Half-Bridge Converter

In-Ho Cho, Student Member, IEEE, Kang-Hyun Yi, Member, IEEE, Kyu-Min Cho, Member, IEEE,
and Gun-Woo Moon, Member, IEEE

Abstract—A new high-efficient multilevel half-bridge converter

is proposed in this paper. The proposed converter regulates the
output voltage by adjusting applied voltage on the main trans-
former with an auxiliary circuit while main switches are operated
at both fixed duty ratio and switching frequency. Therefore, no
magnetizing dc offset current exists on the main transformer and
all switches can be operated with zero voltage switching condition.
Furthermore, multilevel voltage shown at the output filter reduces
the output inductance significantly. To verify these features of the
proposed circuit, operational principle and experimental results
will be presented with the 700 W prototype.
Index Terms—Half-bridge converter, multilevel converter, zero
voltage switching (ZVS).

I. INTRODUCTION
ECENTLY, the efficiency problem in server power sup-
R plies has become an important issue because of its elec-
tricity consumption growth and cooling cost increase [1]–[5].
Especially, the necessity of a high-efficient server power system
is emphasized in the medium power (600–800 W) supplies since
the server infrastructure has spread to small companies these
days. For this purpose, several techniques have been proposed
to reduce the switching losses and component stresses [6]–[24].
Among the proposed techniques, the conventional phase-shifted
full-bridge (PSFB) converter [6]–[8], the active-clamp forward
converter [21], and the asymmetric control half-bridge con-
verter [23], [24] are chosen as promising candidates for their
zero voltage switching (ZVS) operation, relatively lower cur-
rent stress, and simple configuration. However, the usage of the
PSFB converter is limited to medium power supplies since it
adopts large number of main switches on the primary side. The
PSFB converter increases the cost and decreases the power den-
sity of the converter. The active clamp forward converter has
simple structure, but it is also suffered from high-voltage rat-
ing of the main switch. The voltage stress of the active clamp
forward converter is the highest among three ZVS topologies,
which increases the cost and degrades the performance of the
converter. The asymmetric half-bridge converter shown in Fig. 1
is the most attractive topology among three different techniques
mentioned earlier. It has simple structure and wide ZVS range.
Manuscript received May 8, 2009; revised July 14, 2009. Current version
published April 9, 2010. This paper was presented at the Proceedings of the 6th
IEEE International Power Electronics and Motion Control Conference, Wuhan,
China, May 17– 20, 2009. Recommended for publication by Associate Editor
H. S. H. Chung.
The authors are with the Department of Electrical Engineering, Korea Ad-
vanced Institute of Science and Technology, Daejeon 305-701, Korea (e-mail:
ihnara@angel.kaist.ac.kr; philoman@angel.kaist.ac.kr; negative@angel.kaist.
ac.kr; gwmoon@ee.kaist.ac.kr).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2009.2029549
Fig. 1. Schematic diagram of the conventional asymmetric half-bridge
converter.
Also, the voltage stress of the switches is clamped at its input
voltage level. As a result, it has been chosen as the most suitable
topology for the server system in middle power range. However,
the asymmetric half-bridge converter also contains following
drawbacks. The remained dc offset current at the magnetizing
inductor decreases the transformer utilization, and the unbal-
anced voltage-/current stress degrades the performance of the
rectifier stage. Furthermore, its nonlinear dc conversion charac-
teristic requires higher duty variation for the same input variation
compared to other linear converters. It makes the converter oper-
ated beyond the optimum operating point at high-input voltage
specifications.
A number of different techniques have been proposed to
overcome the drawbacks of the asymmetric half-bridge con-
verter [25]–[27]. Employing an auxiliary transformer has been
suggested [25]. With the auxiliary transformer, the converter
extended its nominal duty ratio, but the offset problem of the
magnetizing current is still remained in the transformers. As a
result, power density and core utilization are severely deterio-
rated in the converter. Duty cycle shifted pulsewidth modulation
(PWM) control technique proposed in [26] is very simple and
able to eliminate magnetizing current offset of the converter.
However, one of the two switches in the converter is still op-
erated in hard switching condition, and large ripple current is
shown in the rectifier. Adopting an auxiliary switch ON the sec-
ondary side of the asymmetric half-bridge converter has been
proposed as another solution [27]. The dc offset of magnetizing
current problem could be solved effectively with this solution.

0885-8993/$26.00 © 2010 IEEE

Authorized licensed use limited to: Guru Anandan Saminathan. Downloaded on June 14,2010 at 08:06:45 UTC from IEEE Xplore. Restrictions apply.
944
Fig. 2. Schematic diagram of the proposed converter.
However, its nominal duty ratio is still limited, and the control
scheme is difficult to realize.
In order to overcome all these drawbacks, a new high-efficient
multilevel half-bridge converter is proposed, as shown in Fig. 2.
The proposed converter employs an auxiliary circuit for the out-
put regulation. The auxiliary circuit supplies additional voltage
to the main transformer when input voltage decreases. Thus,
the main switches can be operated at 50% duty ratio and fixed
switching frequency. Since the main switches are always oper-
ated at 50% duty ratio, their ZVS operation is easily achieved,
and the transformer is effectively utilized with no dc offset of
the magnetizing current. Moreover, the ZVS operation of the
auxiliary switches is easily realized by output inductor energy,
and the doubled switching frequency shown at the output filter
reduces the output ripple current significantly.
II. FEATURES OF THE PROPOSED CONVERTER
Fig. 2 shows a circuit diagram of the proposed dc/dc con-
verter. It is based on the conventional half-bridge converter,
and the auxiliary circuit is employed on the primary side of
the converter. The auxiliary circuit is composed of an auxiliary
transformer (T2 ) and two auxiliary switches (S1 and S2 ). Fig. 3
represents the basic operation of the proposed converter. The
main switches are always operated at 50% duty ratio, while the
output voltage is regulated by controlling the phase differences
Deff between the main switches and auxiliary switches. When
the input voltage decreases, Deff is extended and additional volt-
age is increased to compensate the decreased input voltage, as
shown in Fig. 3. As the auxiliary circuit is used only for the reg-
ulation, the magnetic size of the auxiliary transformer is much
smaller than that of the main transformer, and the core loss in
the auxiliary transformer is negligible at nominal operating con-
dition. Also, the current which flows into the auxiliary circuit
Authorized licensed use limited to: Guru Anandan Saminathan. Downloaded on June 14,2010 at 08:06:45 UTC from IEEE Xplore. Restrictions apply.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 4, APRIL 2010
Fig. 3. Applied voltages on transformers: (a) at nominal input voltage and
(b) at minimum input voltage.
is decreased in proportion with the turn ratio of the auxiliary
transformer, thus the current rating of the auxiliary switches is
much smaller than that of the main switches. In addition, the
symmetric operation of the proposed converter makes the pri-
mary current be optimized on the conduction loss and increases
the utilization of the transformers.
III. OPERATIONAL PRINCIPLES
For the convenience of the mode analysis in steady state,
several assumptions are made as follows.
1) The switches M1 , M2 , S1 , and S2 are ideal components
except for their output capacitors and body diodes.
2) The capacitors C1 and C2 are large enough to be consid-
ered as constant voltage sources, (1/2)Vin .
3) Turn ratio of the main transformer (T1 ) is n1 = NP 1 /NS 1
and n2 = NP 2 /NS 2 for the auxiliary transformer (T2 ).
4) The primary current is constant during the very short pe-
riod; t1 –t2 , t2 –t3 , and t4 –t5 .
5) The output inductor LO is operated in constant conduction
mode.
Each switching cycle can be divided into two half cycles t0 –t8
and t8 –t16 . Because of symmetry, only the first-half cycle is ex-
plained and the operating waveforms for the proposed converter
illustrated in Fig. 4.
CHO et al.: HIGH-EFFICIENT MULTILEVEL HALF-BRIDGE CONVERTER 945

linearly charged from 0 V, and the voltage of CM 1 is linearly

discharged from Vin at the same time by utilizing the large out-
put inductance energy. This mode continues until the time when
the primary voltage of the transformer reaches to 0 V.
Mode 6 (t5 –t6 ): When the main transformer voltage Vpri (1)
is decreased to 0 V, the voltage of main-switch M2 increases
in manner of resonance between Llkg and CM 1 + CM 2 . The
voltage of M2 and the primary current are expressed as follows
 
1 Llkg
vC M 2 (t) = ipri(1) (t5 ) + ipri(1) (t5 )
n2 CM 1 + CM 2
 
Llkg
× sin t + vC M 2 (t5 ) (3)
CM 1 + CM 2
 
Llkg
ipri(1) (t) = ipri(1) (t5 ) cos t . (4)
CM 1 + CM 2

On the secondary side, both the rectifier diodes start to con-

duct and commutation of the two diodes D1 and D2 begin. This
mode ends when voltage of the switch M1 discharges to 0 V.
Mode 7 (t6 –t7 ): In mode 7, the primary current flows through
Fig. 4. Operating waveforms of the proposed converter. the body diode of the main switch, M1 . As the main transformer
is regarded as short circuit, all voltages are applied to the leakage
inductance and the primary current is sharply decreased. The
Mode 1 (t0 –t1 ): When commutation is completed at t0 , mode 1
primary current is expressed as
begins. In this mode, extra voltage is added to the nominal
main transformer voltage for the regulation of the converter.
(1/2)vin + (1/n2 )vin
Thus, the input capacitor voltage Vin /2 and reflected auxiliary ipri(1) (t) = − (t − t6 ) + ipri(1) (t6 ).
transformer voltage, VS (2) are applied to the main transformer. Llkg
The primary current increases linearly in this mode with the (5)
slope of [(Vin /2+VS (2) )/n1 −VO ]/LO . Mode 8 (t7 –t8 ): When the main switch M1 is turned on at t7 ,
Mode 2 (t1 –t2 ): When S1 is turned off at t1 , mode 2 begins. this mode begins. The primary current, that was flowing though
The output capacitors of the auxiliary switches CS 1 and CS 2 the body diode of M1 in the previous mode changes the path
are charged and discharged, respectively, in a resonant manner. to the channel of switch M1 . The primary current in this mode
Since the large output inductor energy is participated in this is expressed the same as that of the previous equation (5). This
resonance, the ZVS condition of S1 and S2 are easily realized. mode continues until following condition is satisfied:
Mode 3 (t2 –t3 ): After the auxiliary switch S2 is completely
discharged, the current of the auxiliary circuit ipri(2) flows n1 × ipri(1) (t) = iL o (t). (6)
through the body diode of S2 , as shown in Fig. 5. Thus, the
voltage of S2 is sustained at 0 V, and the applied voltage to the
IV. ANALYSIS OF THE PROPOSED CONVERTER
main transformer remains at Vin /2.
Mode 4 (t3 –t4 ): When the auxiliary switch S2 is turned on In this section, the key characteristics of the proposed con-
at time t3 , mode 4 begins. Since the output capacitor of S2 is verter are presented and they are compared with the character-
completely discharged in the previous mode, it is turned on istics of the asymmetric half-bridge converter.
under ZVS condition. The primary current decreases following
the output inductor current in this mode. The primary current
A. DC Conversion Ratio
ipri is expressed as follows.
1 Fig. 6 shows the filter voltages in the proposed converter
ipri(1) (t) = io (t) (1) and the asymmetric half-bridge converter. The shaded areas in
n1

 Fig. 5 represent the output inductor voltages in each switching
vS (1) − vo cycle. According to voltage-second balance rule of the output
io (t) =
Lo inductor, the dc conversion ratios are expressed as follows. For

 the proposed converter:
× (t − t0 ) + ipri(1) (t3 ) × n1 VS (1)
Vo . (2)
 
Mode 5 (t4 –t5 ): The main switch M2 is turn off at the begin- vO 1 2 1
= × Deff + ( n1 , n2 ≥ 1) (7)
ning of this mode. The voltage of the output capacitor CM 2 is vin n1 n2 2

Authorized licensed use limited to: Guru Anandan Saminathan. Downloaded on June 14,2010 at 08:06:45 UTC from IEEE Xplore. Restrictions apply.
946 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 4, APRIL 2010

Fig. 5. Equivalent circuits of the proposed converter.

Authorized licensed use limited to: Guru Anandan Saminathan. Downloaded on June 14,2010 at 08:06:45 UTC from IEEE Xplore. Restrictions apply.
CHO et al.: HIGH-EFFICIENT MULTILEVEL HALF-BRIDGE CONVERTER 947

C. Output Filter Inductor

As shown in Fig. 6, the frequency shown at the output filter of
the proposed converter is doubled than that of the asymmetric
half-bridge converter and the applied voltage to the output in-
ductor is also decreased. Thus the required output inductance for
the same ripple current condition can be reduced significantly
in the proposed converter compared to that of the asymmetric
half-bridge converter. This property helps increase the power
density of the system. The output inductances required for the
proposed converter and the asymmetric half-bridge converter
are given by (11) and (12), respectively.
[(0.5Vin + Vin /(1/n2 )) /(1/n1 )] − VO
LO = Deff T (11)
∆IO
(1/n1 )(1 − D)Vin − VO
LO = DT. (12)
∆IO

Fig. 6. Applied filter voltages in each converter: (a) he proposed converter
and (b) asymmetric half-bridge converter.
where Deff represents the duration of mode1. The dc conversion
ratio for the asymmetric half-bridge converter is
D. Component Stress
Due to the symmetric control of the switches, the proposed
converter has balanced current and voltage stress on its com-
ponents, while the asymmetric half-bridge converter has un-
balanced stress distribution because of its asymmetric control
method. As a result, the proposed converter can adopt primary
switches with lower current ratings and rectifier diodes with
lower voltage ratings than that of the asymmetric half-bridge
converter. Thus, the cost of the switches can be reduced, and the
efficiency of the rectifier diodes is increased with the proposed
converter.

E. ZVS Condition
vO NS
=2 × D(1 − D). (8) The ZVS conditions of the auxiliary switches in the proposed
vin NP
converter are well achieved because the output capacitors of the
auxiliary switches are discharged by utilizing the large energy
Different from the dc conversion ratio of the asymmetric
stored in the output inductance. For the main switches M1 and
half-bridge converter, the dc conversion ratio of the proposed
M2 , the auxiliary transformer helps increase its ZVS range. It
converter has linearity, as shown in Fig. 7.
is because the energy stored in the leakage inductance of the
auxiliary transformer has also participated in the ZVS operation
B. DC Offset Current in Magnetizing Inductor with the energy stored in the leakage inductance of the main
transformer. Hence, the ZVS range can be extended with the
Since the switches of the proposed converter are controlled leakage inductance of the auxiliary transformer. Fig. 8 shows
symmetrically, the dc offset of the magnetizing current can be the required leakage inductance on every load current condition.
easily eliminated in the proposed converter. Therefore, the trans- As the turn ratio of the auxiliary transformer increases, the
former is fully utilized and it increases the power density of the required leakage inductance for ZVS operation is decreased.
system. However, the dc offset current in the magnetizing induc- Therefore, the ZVS range in the proposed converter can be
tor is varied with the duty ratio in the asymmetric half-bridge extended by increasing the turn ratio of the auxiliary transformer
converter. Thus, the utilization of the transformer is severely de- turn ratio. Also the auxiliary leakage inductance can be added
teriorated in the asymmetric half-bridge converter. The dc offset in the proposed converter to achieve ZVS operation in more
current for the proposed converter (9) and for the asymmetric extended load range. The condition to realize the ZVS operation
half-bridge converter (10) are expressed as follows: in the proposed converter is presented in (13).
      2
IO IO 1 1 1
Deff ILm + = Deff −ILm + .·. ILm ,prop osed = 0 (2COSS ) VS − 0.5 VS / 1 + ≤ Llkg i2pri(1)
n1 n1 2 n2 2
(13)
(9) where COSS is output capacitor of main switches. However,
nS the ZVS condition of the asymmetric half-bridge converter is
ILm ,conventional = (1 − 2 × D) × IO . (10)
nP heavily depended on its dc offset of magnetizing current. Due to

Authorized licensed use limited to: Guru Anandan Saminathan. Downloaded on June 14,2010 at 08:06:45 UTC from IEEE Xplore. Restrictions apply.
948
Fig. 7. dc conversion ratios of each converter: (a) proposed converter and (b) asymmetric half-bridge converter.
Fig. 8. Relation of the minimum required leakage inductance and load current
(at 700 W, Vo = 12 V spec.).
the offset current, the two switches in the same leg have different
ZVS condition. The ZVS range of one switch is increased,
but the range is decreased to the other switch in the same leg.
Thus, to achieve safe ZVS condition in both switches, following
Authorized licensed use limited to: Guru Anandan Saminathan. Downloaded on June 14,2010 at 08:06:45 UTC from IEEE Xplore. Restrictions apply.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 4, APRIL 2010
condition (14) must be satisfied.
 2
1 1 1
(2COSS ) VS ≤ Llkg (ipri − ILm )2 . (14)
2 2 2
V. DESIGN CONSIDERATIONS
In this section, design guideline of the transformers is
presented.
There are two main factors that must be considered for the
selection of turn ratio of the transformers in the proposed con-
verter. These are the voltage regulation condition and the loss at
the auxiliary circuit. In the proposed converter, the main trans-
former is always operated with its maximum duty ratio and
output voltage is regulated by controlling the effective duty ra-
tio of the auxiliary circuit. When the input voltage decreases, the
auxiliary circuit supplies additional voltage to the main trans-
former for the compensation of the input voltage. Therefore, to
satisfy the regulation condition, the voltage supplied by the aux-
iliary transformer must be able to increase as much as maximum
input differences. This condition is expressed as follows:
Dnom < Deff ,m ax < 0.5 ( at, Vin,m in )
. (15)
0 < Deff ,m in < Dnom (at, Vin,m ax )
The aforementioned condition is also represented as a graph
in Fig. 9. The proper range of the transformer turn ratio can be
determined with the voltage regulation rule.
The loss at the auxiliary circuit is another factor when de-
signing the transformers. To minimize the loss of the auxiliary
circuit, core loss of the auxiliary transformer and conduction
loss of the auxiliary switches should be minimized. For the least
core loss of the auxiliary transformer at nominal operating con-
dition, the converter should be able to operate without utilizing
the auxiliary transformer at nominal operating condition. As a
result, the effective duty ratio has to be minimized at nominal
operating condition. Fig. 10 shows the effective duty ratio for
the different turn ratio of the auxiliary transformer. As the turn
ratio increases the effective duty ratio at nominal operating con-
dition decreases. The increased turn ratio also helps extend ZVS
range of the main switches. Therefore, the largest turn ratio of
CHO et al.: HIGH-EFFICIENT MULTILEVEL HALF-BRIDGE CONVERTER 949

Fig. 9. Range of the transformer turn ratio (at 700 W, Vo = 12 V spec.).

Fig. 11. Experimental waveforms: (a) proposed converter and (b) asymmetric
half-bridge converter.

Fig. 10. Effective duty ratio at nominal operating condition for the different
turn ratio of the auxiliary transformer (at 700 W, Vo = 12 V spec.).

the auxiliary transformer should be selected in the allowable

range in Fig. 9.
The size of the auxiliary transformer is influenced by the
load range or the output power. When the auxiliary transformer
turn ratio is determined, the core size of the transformer is se-
lected by considering the current density of the transformer wire.
The current that flows into the auxiliary transformer is reduced
in proportion with the turn ratio of the auxiliary transformer.
Therefore, the size of the auxiliary transformer is much smaller
compared to that of the main transformer, but its size can be
increased followed by increasing output power.
Fig. 12. Switch voltages of the proposed converter: (a) half-load condition
and (b) full-load condition.
VI. EXPERIMENTAL RESULTS
To verify the operation of the proposed converter and eval- two overlapped EI3026 (volume: 12 880 mm3 , µ : 2300) cores
uate performance of the proposed converter and the asymmet- for the main transformer and single EI3026 (volume: 6440 mm3 ,
ric half-bridge converter, prototype circuits have been designed µ : 2300) core for the auxiliary transformer. In the asymmetric
with following specifications: Input voltage : 400 V (330– half-bridge converter, two EI3329 cores (volume: 15280 mm3 ,
400 V), output power: 700 W (12 V/58), switching frequency: µ : 2070) are used as a transformer. For output inductor,
86 kHz. The magnetic cores used for the proposed topology are CH234160 (volume: 2281 mm3 , µ : 160) and CH330060 (vol-

Authorized licensed use limited to: Guru Anandan Saminathan. Downloaded on June 14,2010 at 08:06:45 UTC from IEEE Xplore. Restrictions apply.
950
Fig. 13. Voltage regulation of the proposed converter: (a) nominal operation
(Vin = 400 V) and (b) hold-up time operation (Vin = 330 V).
ume: 5477 mm3 , µ : 60) cores are used in the proposed con-
verter and the asymmetric half-bridge converter, respectively.
The switch used for the main switches in proposed converter is
IPP60R299, and IPP60R600 is used for the auxiliary switches.
In order to compare both converters in the same condition, the
same switches used in the proposed converter are adopted to par-
allel connected switches in the main switches of the asymmetric
half-bridge converter. Synchronous switches are also adopted in
the rectifier stage to improve efficiency of the converters. For
the control of the experimental prototypes, a UCC3895 phase-
shift PWM controller is used for the proposed converter and
a IRS21844 S half-bridge driver is used for the asymmetric
half-bridge converter.
Fig. 11 shows experimental waveforms for the proposed con-
verter and for the asymmetric half-bridge converter at nominal
load condition (12 V/58 A). The experimental results are in good
agreement with the theoretical waveforms. The ZVS condition
of the main switches in the proposed converter and the main
switches in the asymmetric half-bridge converter are designed
to operate ZVS down to half-load condition. The ZVS condition
of the proposed converter is shown in Fig. 12, and voltage reg-
ulation operation of the proposed converter is shown in Fig. 13.
As discussed earlier, the effective duty increased to its maxi-
mum value when the input voltage decreased to the minimum
operation voltage.
Fig. 14 shows the efficiency of the proposed converter, the
asymmetric half-bridge converter and the modified proposed
converter, which uses the same filter inductance with that of the
asymmetric half-bridge converter. Since the balanced compo-
nents stress in the proposed converter decreases the conduction
loss of the converter, the proposed converters show higher ef-
ficiencies compared to the asymmetric half-bridge converter.
Also the efficiency graphs of the proposed converter and the
modified proposed converter verify that the characteristic of re-
duced filter inductance in the proposed converter helps decrease
the loss of the filter inductor.
Authorized licensed use limited to: Guru Anandan Saminathan. Downloaded on June 14,2010 at 08:06:45 UTC from IEEE Xplore. Restrictions apply.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 4, APRIL 2010
Fig. 14. Efficiency comparisons.
VII. CONCLUSION
A new multilevel half-bridge converter was presented and an-
alyzed. By employing one small subtransformer and two small
additional switches, the proposed converter shows better perfor-
mance than the asymmetric half-bridge converter in entire load
range. The proposed converter has lower conduction loss and re-
quires smaller filter inductance than the asymmetric half-bridge
converter. Also, it achieves good ZVS condition, and its sym-
metrical operation characteristic balances the voltage/current
stresses on its components and eliminates the dc offset of magne-
tizing current, which degrade the utilization of the transformer.
Therefore, the proposed converter can be selected as a good
candidate in middle power server system.
REFERENCES
[1] J. P. Bryant, “AC-DC power supply growth variation in China and North
America,” in Proc. Appl. Power Electron. Conf. Expo., 2005, pp. 159–162.
[2] L. H. Mweene, C. A. Wright, and M. F. Schlecht, “A 1 kW 500 kHz
front-end converter for a distributed power supply system,” IEEE Trans.
Power Electron., vol. 6, no. 3, pp. 398–407, Jul. 1991.
[3] C. Calwell, A. Mansoor, E. Consulting, and C. O. Durango, “AC-DC
server power supplies: Making the leap to higher efficiency,” in Proc.
Appl. Power Electron. Conf. Expo., 2005, pp. 155–158.
[4] K. G. Brill. (2007). Data center energy efficiency and productivity.
presented at the Uptime Institute Symposium 2007 [Online]. Available:
www.energystar.gov/ia/products/downloads/WF_3_Handout_DataCenter
_efficiency.pdf
[5] F. C. Lee, P. Barbosa, P. Xu, J. Zhang, B. Yang, and F. Canales, “Topolo-
gies and design considerations for distributed power system applications,”
Proc. IEEE, vol. 89, no. 6, pp. 939–950, Jun. 2001.
[6] J. A. Sabate, V. Vlatkovic, R. B. Ridley, F. C. Lee, and B. H. Cho, “De-
sign considerations for high-voltage high-power full-bridge zero-voltage-
switched PWM converter,” in Proc. Appl. Power Electron. Conf. Expo.,
1990, pp. 275–284.
[7] C. Zhao, X. Wu, P. Meng, and Z. Qian, “Optimum design consideration and
implementation of a novel synchronous rectified soft-switched phase-shift
full-bridge converter for low-output-voltage high-output-current applica-
tions,” IEEE Trans. Power Electron., vol. 24, no. 2, pp. 388–397, Feb.
2009.
[8] X. Wu, X. Xie, J. Zhang, R. Zhao, and Z. Qian, “Soft switched full bridge
DC-DC converter with reduced circulating loss and filter requirement,”
IEEE Trans. Power Electron., vol. 22, no. 5, pp. 1949–1955, Sep. 2007.
[9] J. Zhang, X. Xie, X. Wu, and Z. Qian, “A novel zero-current-transition full
bridge DC/DC converter,” IEEE Trans. Power Electron., vol. 21, no. 2,
pp. 354–360, Mar. 2006.
[10] W. Li and X. He, “A family of interleaved DC-DC converters deduced
CHO et al.: HIGH-EFFICIENT MULTILEVEL HALF-BRIDGE CONVERTER
from a basic cell with winding-cross-coupled inductors (WCCIs) for high
step-up or step-down conversions,” IEEE Trans. Power Electron., vol. 23,
no. 4, pp. 1791–1801, Jul. 2008.
[11] Y. Tao and S. J. Park, “A novel ripple-reduced DC-DC converter,” J.
Power Electron., vol. 9, no. 3, pp. 396–402, Jan. 2009.
[12] J. A. A. Qahouq, O. Abdel-Rahman, L. Huang, and I. Batarseh, “On load
adaptive control of voltage regulators for power managed loads: Control
schemes to improve converter efficiency and performance,” IEEE Trans.
Power Electron., vol. 22, no. 5, pp. 1806–1819, Sep. 2007.
[13] Y. Gu, Z. Lu, L. Hang, Z. Qian, and G. Huang, “Three-level LLC series
resonant DC/DC converter,” IEEE Trans. Power Electron., vol. 20, no. 4,
pp. 781–789, Jul. 2005.
[14] I. Batarseh, “Resonant converter topologies with three and four energy
storage elements,” IEEE Trans. Power Electron., vol. 9, no. 1, pp. 64–73,
Jul. 1994.
[15] H. S. Choi, “Design consideration of half-bridge LLC resonant converter,”
J. Power Electron., vol. 7, no. 1, pp. 13–20, Jan. 2007.
[16] N. Lakshminarasamma and V. Ramanarayanan, “A family of auxiliary
switch ZVS-PWM DC-DC converters with coupled inductor,” IEEE
Trans. Power Electron., vol. 22, no. 5, pp. 2008–2017, Sep. 2007.
[17] Y. Zhu and B. Lehman, “Three-level switching cell for low voltage/high-
current DC-DC converters,” IEEE Trans. Power Electron., vol. 22, no. 5,
pp. 1997–2007, Sep. 2007.
[18] J. Zhang, X. Xie, X. Wu, and Z. Qian, “A novel zero-current-transition full
bridge DC/DC converter,” IEEE Trans. Power Electron., vol. 21, no. 2,
pp. 354–360, Mar. 2006.
[19] X. Ruan, Z. Chen, and W. Chen, “Zero-voltage-switching PWM hybrid
full-bridge three-level converter,” IEEE Trans. Power Electron., vol. 20,
no. 2, pp. 395–404, Mar. 2005.
[20] G. A. Karvelis, M. D. Manolarou, P. Malatestas, and S. N. Manias, “Anal-
ysis and design of non-dissipative active clamp for forward converters,”
in Proc. IEE Proc. Elect. Power Appl., Sep. 2001, vol. 148, pp. 419–424.
[21] Y. K. Lo and J. Y. Lin, “Active-clamping ZVS flyback converter employing
two transformers,” IEEE Trans. Power Electron., vol. 22, no. 6, pp. 2416–
2423, Nov. 2007.
[22] R. L. Steigerwald, “A comparison of half-bridge resonant converter
topologies,” IEEE Trans. Power Electron., vol. 3, no. 2, pp. 174–182,
Apr. 1988.
[23] P. Imbertson and N. Mohan, “Asymmetrical duty cycle permits zero
switching loss in PWM circuits with no conduction loss penalty,” IEEE
Trans. Ind. Appl., vol. 29, no. 1, pp. 121–125, Jan. 1993.
[24] J. C. P. Liu, N. K. Poon, B. M. H. Pong, and C. K. Tse, “Low output ripple
DC-DC converter based on an overlapping dual asymmetric half-bridge
topology,” IEEE Trans. Ind. Appl., vol. 22, no. 5, pp. 1956–1963, Sep.
2007.
[25] R. Miftakhutdinov, A. Nemchinov, V. Meleshin, and S. Fraidlin, “Mod-
ified asymmetrical ZVS half-bridge DC-DC converter,” in Proc. Appl.
Power Electron. Conf. Expo., 2005, pp. 567–574.
[26] H. Mao, J. Abu-Qanhouq, S. Luo, and I. Batarseh, “Zero-voltage-
switching half-bridge DC-DC converter with modified PWM control
method,” IEEE Trans. Power Electron., vol. 19, no. 4, pp. 947–958,
Jul. 2004.
[27] K. M. Cho, W. S. Oh, and G. W. Moon, “A new half-bridge converter
without DC offset of magnetizing current,” in Proc. Int. Conf. Power
Electron., 2007, pp. 147–149.
In-Ho Cho (S’09) was born in Korea in 1982. He
received the B.S. degree from Hanyang University,
Seoul, Korea, in 2007, and the M.S. degree in electri-
cal engineering from the Korea Advanced Institute of
Science and Technology (KAIST), Daejeon, Korea,
in 2009. He is currently working toward the Ph.D.
degree at the KAIST.
His research interests include dc/dc converter,
power-factor-correction, ac/dc converters, and server
power systems.
Mr. Cho is a member of the Korean Institute of
Power Electronics.
Authorized licensed use limited to: Guru Anandan Saminathan. Downloaded on June 14,2010 at 08:06:45 UTC from IEEE Xplore. Restrictions apply.
951
Kang-Hyun Yi (S’05–M’06) was born in Korea in
1978. He received the B.S. degree in electrical engi-
neering from Hanyang University, Seoul, Korea, in
2003, and the M.S. degree in electrical engineering
and computer science from the Korea Advanced In-
stitute of Science and Technology (KAIST), Daejeon,
Korea, in 2006. He is currently working toward the
Ph.D. degree in electrical engineering at the KAIST.
His research interests include high-efficiency
plasma display panel driver circuit, dc/dc converters,
soft switching technique, and digital display driver.
Mr. Yi is a member of the Korean Institute of Power Electronics.
Kyu-Min Cho (S’08–M’09) was born in Korea
in 1978. He received the B.S. degree in electrical
engineering from Kyungpook National University,
Daegu, Korea, in 2003, and the M.S. degrees in elec-
trical engineering from the Korea Advanced Insti-
tute of Science and Technology (KAIST), Daejeon,
Korea, in 2003. He is currently working toward the
Ph.D. degree at KAIST.
His research interests include dc/dc converters,
power-factor-correction ac/dc converters, backlight
inverters of liquid-crystal display television (LCD
TV), driver circuits of LCD TV, PC power supply, and server power systems.
Mr. Cho is a member of the Korean Institute of Power Electronics.
Gun-Woo Moon (S’92–M’00) received the M.S.
and Ph.D. degrees in electrical engineering from the
Korea Advanced Institute of Science and Technol-
ogy (KAIST), Daejeon, Korea, in 1992 and 1996,
respectively.
He is currently a Professor at the Department of
Electrical Engineering, KAIST. His research inter-
ests include modeling, design and control of power
converters, soft-switching power converters, resonant
inverters, distributed power systems, power-factor
correction, electric drive systems, driver circuits of
plasma display panels, and flexible ac transmission systems.
Prof. Moon is a member of the Korean Institute of Power Electronics, the
Korean Institute of Electrical Engineers, the Korea Institute of Telematics and
Electronics, the Korea Institute of Illumination Electronics and Industrial Equip-
ment, and the Society for Information Display.