Device Scaling in COSMOS Architecture
Ahmad Al-Ahmadi and Savas Kaya*
SEECS, Ohio University, Athens, OH 45701, USA
* e-mail: kaya@ohio.edu, Tel: +1-740-597-1633, Fax: +1-740-593-0007
The Si nanoelectronic engineering have recently
reached a level of capability, which make 3D processing
and strain engineering on silicon-on-insulator (SOI)
substrates not only possible [1,2], but also a necessity in
order to surmount practical limitations of conventional
planar CMOS [3]. Thus, device designers are presented
with a multitude of options in exploring new designs, as
evident in the proliferation of alternative architectures,
including multi-gated, strained Si/SiGe channel, Schottky
and Tunneling MOSFETs. While these structures have
unique features superior to conventional bulk devices,
nonetheless, they still retain the redundancy inherent to
CMOS operation, namely building two devices even
though only one operates at a given stable output.
In this paper we demonstrate and design, through the
use of 1/2/3D device simulations, a novel symmetrically
operating CMOS device pair with a single gate structure
having a unique device layout and ultra-thin strained
channels [4]. The new architecture, named complementary
orthogonal stacked MOS (COSMOS), places the n and p-
MOSFETs perpendicular to one another under a single
gate, integrating them vertically (see Figs.1&2). Thus
COSMOS can eliminate the aforementioned redundancy in
CMOS and may result in dramatic savings (>50%) not only
in active device area of a conventional digital CMOS
layout, but also in R-C device parasitics associated with
building and wiring two sets of devices for a single
Boolean output function. We argue that the COSMOS
structure is a natural candidate for very dense, low-power
circuitry required in sub-5Onm scale.
The proposed COSMOS architecture relies for
operation on a conventional silicon electron channel grown
atop a strained-SiGe channel for holes, as shown in Fig.2.
To facilitate threshold tuning, reduce parallel conduction
and eliminate need for doping, Ge concentration in the
strained channel must be high. In accordance, the gate
material may be a mid-gap metal, poly-SiGe alloy or poly-
Si, depending on the choice of Ge concentration or
background doping. The channel layers must be grown [5]
or bonded [6] on a SOI substrate to allow isolation of both
MOSFETs, while also keeping with the general scaling
trends associated with low-leakage and low-parasitic SOI
substrates. For a sample layer structure with a 4nm
strained-Si03Ge0.7 hole channel and 3nm Si electron
channel under a mid-gap metal gate, ID self-consistent
Poisson-Schrodinger simulations (see Fig.3) indicate that
symmetric population of both channels is possible with a
threshold of IVTI=0.4±0.2 V. We also find that there is no
significant parallel conduction in this layer structure,
removing concerns for isolation in the stacked channels.
Even for this non-optimum layer example, the carriers in
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both channels of COSMOS layers are well confined and have
quite similar distributions.
The use of large Ge concentration in the buried strained
channel should improve hole mobility considerably over that of
electrons in Si inversion channel. Thus, for x.0.3, hole
mobility in strained Sii-.Gex layers should be comparable to or
larger than electron mobility in undoped Si inversion layer [7].
By aligning p-MOSFET along the [011] direction [8], hole
mobility may be further improved, thus restoring p-MOSFET
transconductance deficit due to larger separation from the gate.
In COSMOS, there are several independent parameters of layer
structure, including layer composition, thickness and order,
which can be used to optimize a symmetric device threshold. In
Fig.4, we demonstrate how these parameters can be
independently tailored to prevent parallel conduction and to set
VT accurately. 3D TCAD simulations of the individual
MOSFET characteristics (Fig.5) validate the ID analysis
above, providing further support for the ability of symmetric
control of two channels with a single gate.
To show the usefulness of COSMOS for digital circuits,
we simulated in 3D the transient response of a 40nm COSMOS
NOT gate to an input pulse (Fig.6). The gate has respectable
delay (lO00ps) and noise margin figures at low drive voltages
(VDD+IVssl< .OV) used in sub-SOnm scale. These results
illustrate the unique potential of COSMOS logic for low-power
and high-density applications, which can be further enhanced
by optimizing the structure and choice of symmetric VT. The
delay of the gate can be improved at the expense of static
leakage (Fig.7) due to parasitic p-i-n device turning on at high-
drive conditions. To inhibit this, two additional etching steps
are required during the fabrication of COSMOS structure [4].
Furthermore, the COSMOS gates have peculiar scaling trends,
with smaller gate lengths having larger thresholds and smaller
ON current below 20nm nodes due to reciprocal dependency of
gate length and width in orthogonal device layout (Fig.8).
The present study is an attempt at presenting how the
novel COSMOS architecture can be operated, optimized and
utilized in sub-50nm. We illustrate the design principles of this
so far unexplored COSMOS architecture for optimum leakage
and switching performance. This work shows how significant
area and performance gains can be obtained in CMOS logic
circuits by a unique combination of layout and channel
engineering,
[1] P A Packan, Science, vol. 285, p.2079,1999.
[2] D Hisamoto, IEDM Tech Dig., p. 429432,2001
[3] H-S P Wong, IBMJRes & Dev., vol.46, p.133,2002.
[4] S Kaya, Proc. Si Nanoelectronic Workshop, p.7, 2004
[5] T Numata et al., IEEE SOI Conference, p. 1 19, 2003,
[6] K Rim et al., IEDM Tech Dig., p.49,2003.
[7] M L Lee and E A Fitzgerald, Appl Phys. Lett., p.4202,2003.
[8] T Mizuno et al., IEDM Tech Dig., p.809,2003.
93
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73E(np OSFET a)
"MO
FIGURE 1: Comparison of current paths for n or p MOSFETa in FIGURE 2: a) Generic layer structure for formation of channels and b) cross-sectional views of
conventional CMOS and proposed COSMOS architectures. the two MOSFETs in the proposed COSMOS architectures.

105

E
~'(a

S.
X
2 4
Distanc:t [mm
6 al l

a°
'A
104-

10
-

S.S 2 * Lb
=~~~ ~~~~~~~~~
f X
I0n
4.
IV 1.
A j1 X - I / -0.4 -0.2 0 0.2 0.4
.
I
-.S 0 0.5 I
Gate Voltage [V]
Gate Bias [VI a) b)
FIGURE 3: ID self-consistent simulation of e- FIGURE 5: a) 3D view of the COSMOS device (L=200nm) and the 3D simulation domain. b): Simulated I-V
and h+ distributions and resulting density in the characteristics in 3D. Note that QM corrections are omitted in to save time, electron and hole mobility are not set
channel as a function ofgate voltage. equal, and layer design is not optimized for symmetric threshold as seen in Fig.3
I
I ,.1........
Mid-gap Metal Gate ...., .. 11 ....---. .... T....
filled: 70% Go Midgap Metal Gate
Electron channel empty: 35% Ge U,
0.5 0.5 (0c- r- -I
0
0)
synmetric
operaio 0 ^ Pa4cEdctn chnnel
for -30%Ge 0 IHale chwnne
* ~~~HOle chann
(0 ..... .......
a l -200
-0.5
a3
a.~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
c
>0.3 V Buffer ID- ~~~~~~~4 - v 8.1ci'.a
A~ ------ channel
*Parasitic ±--^--------*
-----
- U3
-1 ..........-..... I
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 10 20 30 40 50 60 100 200 0 100 200
x [%Ge] b) Strained Channel Thickness [A]
Time [ps]
FIGURE 4: Optimization of COSMOS threshold as a function of (a) Ge% (x), and (b) FIGuRE 6: The transient response of a 40 nm COSMOS inverter
strained SiGe thickness (tsi). Threshold can be optimized using various {x,tsi} pairs. obtained from 3D drift-diffusion simulations. CL=1fF assumed.
'I ' I l 3
. r T 1
20
t0
I
V 10
1.
r -Statict Le-kage
Static Leakage- I-

3eO
I r 0
, . . .I
0.4 -

9118150 1000
-0.6V.,: {
00
0~~~~~~~~~~~-
-
> ~~~Vl=sVDD= i, --*-0.5
0 6v
V:
2- Empty: 18 mm -- - 100
-0.4 St
u1: 36 nm ,.~ M
i 1.5 _--- Loss of NM Switching Delay
,.
100 10 20 30 40 50 60
-0
0. 5 1 1.5 2
a) Channel Length, L8 [nrn] 10 20 30 40 50 6
b) Drive Voltage (VDD-IVSSI) [VI b) Channel Length, L8 [mi]
FIGURE 7: Voltage scaling trends in the FIGURE 8: Dependence of a) delay and static leakage, and b) threshold voltage of COSMOS gates (total t,h=5nm), on
40nm COSMOS gate. effective channel length. The peculiar scaling trend is due to reciprocal coupling of gate dimensions in COSMOS.

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