ECE 650 – Lab 4:

Macromodeling (with Standard Library Components) and Behavioral Modeling

(with Verilog-A) of a Tunable 2nd-Order Filter Block in Cadence

1. Introduction

To implement the filter tuning schemes covered in the lecture, it is usually beneficial to begin with
simulations using macromodel cells or behavioral blocks specified with a hardware description
language such as Verilog-A, which typically saves simulation and design time. For that purpose, a
simple macromodel of a tunable 2nd-order transconductance-capacitor (Gm-C) filter block (biquad)
will be introduced in this lab using ahdl components from the standard libraries in Cadence. A
customized and more general behavioral model of a 2nd-order filter with low-pass, bandpass, and
high-pass outputs will be written in Verilog-A. Both cells will have tunable gain, center frequency
(fo), and quality factor (Q). An 8th-order Chebyshev bandpass filter will be simulated with the Gm-C
block to demonstrate the usefulness of tunability. Furthermore, an analog tuning scheme will be
added in the simulation setup for automatic tuning of gain, center frequency, and quality factor of the
filter sections.

NCSU design kit 1.5.1 is used in this lab. Create a new folder (e.g. cadence_ncsu) for this design kit
and start Cadence within the new folder by typing “/homes/karsilay/ncsu151/bin/ncsu151” on a
Linux host (local host or a Linux server).

In the library manager, create a new library and attach the technology file CSU_TechLib_ami06.

2. Macromodel of a Tunable Gm-C Biquad

2.1. Ideal model of a tunable transconductor

Fig. 2.1 shows a simple model of a tunable transconductor, which is useful for quick verification of
filter transfer functions and tuning schemes. The non-idealities of operational transconductance
amplifiers (OTAs) are not accounted for in this model, but they can be included by adding functional
blocks that introduce poles and zeros in the frequency response, non-linearities, saturation effects, etc.

In the new library, create a schematic and place the components with the same values as in Fig. 2.1.
The main path has a fixed transconductance (vccs from analogLib) of 1mA/V and the auxiliary path
can add up to 0.5mA/V depending on the control voltage Vc. This tuning is realized by multiplying
the input to the auxiliary 0.5mA/V vccs by a scaling factor of 2×(Vc – 0.5V) after limiting Vc with a
voltage clamp having a range from 0.5V to 1V. The hard_voltage_clamp and multiplier cells are both
in the ahdlLib. Also create the corresponding symbol for the transconductor model after finishing the
schematic.

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 Fig. 2.1: Ideal tunable transconductor model

Create a testbench schematic as in Fig. 2.2a to verify the functionality of the transconductor. The
signal source has AC magnitude = 1V, amplitude = 1V, frequency = 1kHz; and the DC control
voltage is specified as a variable (Vc). Open the Analog Environment and double-check that the /tmp
directory is specified as in the description of Fig. 1.1 on page 1. Set up the following analyses in the
Analog Environment:
Transient: 10ms, moderate
AC: 1Hz – 1GHz

Run the simulations with different control voltages to verify that the AC and transient responses have
the expected dependency on Vc. Set Vc = 1V and save the transient/AC responses for the report.
Also run a parametric sweep of Vc from 0V to 1.5V (auto, 50 steps) to generate the plot in Fig. 2.2b
for the report by plotting Gm = io_ac / vin_ac from the current through the resistor and the input voltage.
[ Note: - If the current is not automatically saved after the simulation, then select Outputs → to
be saved → select on schematic and click on the resistor terminal.
- One way to plot the result is to enter the following expression in the calculator:
value(abs(IF("/R0/MIUS")/VF("/Vin")), 1k) ]

a) b)

Fig. 2.2: a) Transconductor testbench b) Gm vs. Vc

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2.2. Ideal biquad model

Use the tunable transconductor from the previous section in a new schematic for the ideal Gm-C
biquad macromodel shown in Fig. 2.3. Capacitors C1 and C2 in this example are 21.209fF and
42.003pF, respectively. Note, C1 is in the range of parasitic capacitances in modern CMOS
technologies; hence a value of ~21fF could be too small, especially since it is desirable to avoid
relying on parasitic capacitances due to their high process variation compared to metal-insulator-
metal capacitors for example. Changes to the macromodel should be made based on circuit-level
characterization of the anticipated technology, which may require the use of different capacitor or
transconductance values. In this example, the idealized capacitor and transconductance values for the
Gm-C biquad are chosen based on the equation for the bandpass output below, where s = jω.
gm1
V out s C2
T BPF (s) = V in
= gm 4 g g (1)
s2+s C2
+ mC 2C m 3
1 2
The quality factor (Q) and center frequency (fo) can be determined from the following expressions:
Q = 2πC2fo / gm4 = fo / (f3dB_high - f3dB_low) (2)
1 gm2gm3
fo = 2π C 1C 2
(3)

Fig. 2.3: Idealized Gm-C biquad with tuning voltages

Characterize the tunable Gm-C biquad cell with the testbench displayed in Fig. 2.4a. The DC voltage
sources for the frequency, quality factor, and gain tuning are specified as variables Vf, Vq, Vgain,
respectively; and the AC sine source (vsin) has the following parameters:
AC magnitude = 1V
Amplitude = 1V
Frequency = 210.8MHz

In the Analog Environment, check that the settings are as in Fig. 1.1a and set the Vf, Vq, Vgain
design variables equal to 0.75V. Next, set up the following simulations:
Transient: 400ns, conservative
AC: Linear sweep, 500 total points, range: 100MHz – 300MHz

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Simulate and save the frequency response (in dB20, Fig. 2.4b) and transient output voltage for the
report. Compare the theoretical and measured values of the quality factor based on equation (2),
where fo is the center frequency and f3dB_high and f3dB_low are the 3-dB frequencies in Fig. 2.4b. Note,
the accuracy (number of points) in the AC simulation affects the accuracy of the peak around the
center frequency and therefore the quality factor estimation. What is the amplitude of the transient
output voltage? To improve the accuracy of the result, re-open the transient analysis in the Analog
Environment (left window in Fig. 2.5) and click “Options…” to change the step as well as maxstep to
1e-11 as in the window on the right in Fig. 2.5. Re-simulate with these settings and record the new
amplitude of the transient output voltage.

a) b)
Fig. 2.4: a) biquad testbench b) frequency response with Vf = Vq = Vgain = 0.75V

Fig. 2.5: Simulation time stop options for improved accuracy

Disable the transient analysis to shorten the simulation time required for the parametric sweeps of the
tuning voltages. Select Tools → Parametric Analysis from the Analog Environment. Sweep the
frequency control voltage Vf with the settings shown in Fig. 2.6 and plot the frequency responses for
the different control voltage values in the same plot as in Fig. 2.7. Mark the frequency tuning range
in the plot.

Repeat the parametric sweep with the same settings for the other two control voltages (Vq, Vgain)
and provide the quality factor as well as gain tuning ranges in the report. In both cases, plot all
frequency responses in one plot to visualize the effect of changing the control voltages.

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 Fig. 2.6: Settings for the parametric sweeps of individual control voltages

Fig. 2.7: Example sweep: center frequency tuning with control voltage Vf

2.3. Transconductor and biquad results expected in the lab report

1) Tunable transconductor
a. Screenshots of the transconductor and testbench schematics
b. Gm vs. Vc plot
c. Transient and AC responses (with Vc = 1V)
2) Tunable Gm-C biquad
a. Screenshots of the biquad and testbench schematics
b. Frequency and transient responses with Vf = Vq = Vgain = 0.75V
i. Quality factor calculation based on equation (2)
ii. Mark amplitude of the transient output voltage with accurate simulation settings
c. Plots from parametric sweep of control voltages
i. Sweep of Vf (Fig. 2.6) with annotated frequency tuning range
ii. Sweep of Vq (all frequency responses in one plot). What is the tuning range for
the quality factor?
iii. Sweep of Vgain (all frequency responses in one plot). What is the tuning range for
the gain?

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3. Generalized Behavioral Model of a 2nd-Order Filter in Verilog-A

3.1. Description

Behavioral modeling with a hardware description language such as Verilog-A is another alternative
to simulate filters and tuning schemes significantly faster than with circuit-level simulations. Again,
the starting point is an idealized model to which more complex functions can be added based on
anticipated or known non-idealities. In this lab, the focus is on implementing the 2nd-order transfer
function below with tunable center frequency, quality factor, and gain.

V out K1s 2 + K 2 s + K 3
H (s) = V in
= ωo (4)
s2 +s Q
+ ω o2

As before, Q = fo / (f3dB_high - f3dB_low). Parameters K1-K3 in this generalized transfer function

determine the filter type and passband gain as follows:
Low-pass filter (LPF): K1 = K2 =0 → K3 = ωo2 for 0dB passband gain
Bandpass filter (BPF): K1 = K3 =0 → K2 = ωo / Q for 0dB passband gain
High-pass filter (HFP): K2 = K3 =0 → K1 = 1 for 0dB passband gain

The biquad macromodel in section 2 is a special case of equation (4). Verilog-A will be used in the
next section to make a more general tunable 2nd-order filter that does not imply a Gm-C
implementation as the macromodel in section 2.

3.2. Model Creation

Start by making a new symbol for the Verilog-A block in the library manager: File → ew →Cell
View. Select the symbol composer (Fig. 3.1a) in the file creation menu and select any cell name. An
example symbol is shown in Fig. 3.1b, in which the following insertions were made:
Add → Selection Box to place the red keep-out layer around the symbol
Add → Label → type [@instanceame] and place the label
Add → Pin → enter pin name (direction: InputOutput, type: square) and place the pin

After completing the symbol, select Design → Create Cell View → From Cell View from the menu
of the symbol editor. In the pop-up window, change the Tool/Data Type to VerilogA-Editor as in Fig.
3.2 before clicking “ok”. A terminal window will automatically open after which you have to press
“enter” on the keyboard. Now, the “veriloga” view will be listed under the symbol in the library
manager, and the newly opened terminal window should display the basic code for the module with
correct input/output pin and signal definitions (see Fig. 3.3). You can write the Verilog-A code for
the module in this editor using the same commands as the VI editor in UNIX. To save and quit, use
the following sequence: press escape (Esc) on the keyboard, write :wq in the command line, and
press enter. The compiler will automatically check the code after you quit the editor and messages
regarding syntax errors or successful checking will be displayed in the CIW window. If syntax errors
exist, a window will open up with descriptions and the Verilog-A editor will re-open in edit mode.

If you are not familiar with VI commands: You can use your preferred editor by opening the
veriloga.va file directly from a UNIX terminal.

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To use nedit, for instance, type: nedit veriloga.va from within the above directory. If you open the
file with another editor it will not be checked for syntax errors. Thus, you will have to open it again
in the Verilog-A editor by double-clicking on the veriloga view in the library manager and
typing :wq in the command line as above to initiate the syntax checking.

a) b)
Fig. 3.1: Symbol a) creation b) diagram

Fig. 3.2: Verilog-A file creation

Fig. 3.3: Auto-generated filter module code

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Use the Verilog-A editor (or another editor) to insert the code below for the module of the tunable
filter. You can skip the comments that begin with “//”. After entering the code, make sure to save &
quit the Verilog-A editor and resolve any syntax errors before continuing.

>> begin to insert after the line “electrical Vgain;” in Fig. 3.3 <<

// Parameter initializations:
parameter real fo = 1e6;
parameter real pi = 3.14159265;
parameter real wo = 2*pi*fo;
parameter real Q = 1;
parameter real K1 = 1;
parameter real K2 = wo/Q;
parameter real K3 = wo*wo;
// Control (tuning) voltages are limited (clipped):
parameter real Vgain_min = 0.5; // Gain control voltage range
parameter real Vgain_max = 1.5;
parameter real Vf_min = 0.5; // frequency control voltage range
parameter real Vf_max = 1.5;
parameter real Vq_min = 0.5; // Q-factor control voltage range
parameter real Vq_max = 1.5;
real G, w_fact, q_fact; // Scaling factors for gain, wo, and Q
// Numerator and denominator arrays for the different transfer functions:
real num_BPF[0:2], num_LPF[0:2], num_HPF[0:2];
real den[0:2]; // common denominator for all cases

analog begin
// Limitation of control voltage for frequency scaling:
if (V(Vf) > Vf_max) begin
w_fact = Vf_max;
end else if (V(Vf) < Vf_min) begin
w_fact = Vf_min;
end else begin
w_fact = V(Vf);
end
// Limitation of control voltage for Q-factor scaling:
if (V(VQ) > Vq_max) begin
q_fact = Vq_max;
end else if (V(VQ) < Vq_min) begin
q_fact = Vq_min;
end else begin
q_fact = V(VQ);
end
// Transfer function input variables must be initialized once.
// The "static" analysis uses DC operating point values of the scaling factors
// (The inputs of the laplace_nd function below cannot be calculated
// dynamically in the outut expressions below, which is why they are saved
// in arrays after the initial (static) calculations.)
// Numerators & denominators for BPF, LPF, HPF cases with scaling:
@(initial_step("static")) begin
num_BPF[0] = 0;
num_BPF[1] = w_fact*K2/q_fact;
num_BPF[2] = 0;
num_LPF[0] = w_fact*w_fact*K3;
num_LPF[1] = 0;
num_LPF[2] = 0;
num_HPF[0] = 0;
num_HPF[1] = 0;
num_HPF[2] = K1;
den[0] = w_fact*w_fact*wo*wo;
den[1] = w_fact*wo/(Q*q_fact);
den[2] = 1;
end
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 // Limitation of the gain scaling factor:
// (gain scaling can be done in the output expression because the
// multiplication is outside of the laplace_nd function.)
if (V(Vgain) > Vgain_max) begin
G = Vgain_max;
end else if (V(Vgain) < Vgain_min) begin
G = Vgain_min;
end else begin
G = V(Vgain);
end
// Output assignments based on filter transfer functions:
V(Out_BPF) <+ G * laplace_nd( V(In), num_BPF, den ) ;
V(Out_LPF) <+ G * laplace_nd( V(In), num_LPF, den ) ;
V(Out_HPF) <+ G * laplace_nd( V(In), num_HPF, den ) ;

end

>> the next line is “endmodule” in Fig. 3.3 <<

3.3. Verification

Create a new schematic with the test setup for the behavioral model of the filter shown in Fig. 3.4.
Note, that the tuning voltage in the in the Verilog-A code are limited from 0.5V to 1.5V. Furthermore,
the scaling of frequency, quality factor, and gain is obtained by multiplication with Vf, VQ, and
Vgain, respectively. Hence, nominal filter values are obtained with control voltages of 1V rather than
0.75V as in the previous Gm-C macromodel.

As before, variables are used for the DC control voltages. The signal source has AC magnitude = 1V,
amplitude = 1V, frequency = 10MHz.

Verilog-A input parameters can also be modified by selecting the filter block in the schematic,
clicking Edit → Properties → Objects… in the schematic window, and changing the “CDF
parameter of view” to veriloga, as in Fig. 3.5. Specify fo = 10MHz and Q = 1; the default
parameters from the Verilog-A module code will be used by the simulator for the remaining
parameters in the list.

Fig. 3.4: Testbench for the Verilog-A filter block

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 Fig. 3.5: Verilog-A filter block parameters
Open a new Analog Environment and change the Project Directory to /tmp as in Fig. 1.1. Set
variables Vf, VQ, and Vgain to 1. The analyses below should be used for the first simulation.
Transient: 2us, conservative
AC: Type: logarithmic, 500 total points, 1MHz – 100MHz

Run the simulations and verify that the frequency responses and transient at the three outputs agree
with Fig. 3.6. Check from the bandpass response that Q is equal to 1.

a) b)
Fig. 3.6: Verilog-A filter outputs with Vf = VQ = Vgain = 1V, fo = 10MHz, Q = 1
a) frequency responses b) transient waveforms

Edit the component properties of the Verilog-A block in the schematic to change Q in Fig. 3.5 from
1 to 10. Re-run the simulations and plot the frequency responses. As Q is increased, the peak of the
LPF and HPF responses also increases and its frequency (ωpeak) approaches ωo. Additionally, it can
be checked easily whether the quality factor of the LPF/HPF output from the Verilog-A block is
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correct because Q ≈ fpeak / (f3dB_high - f3dB_low) as Q → ∞, where f3dB_high and f3dB_low are the 3dB
frequencies relative to the peak. Estimate the quality factors of the LPF and HPF outputs from the
frequency responses with Q = 10 and mark the frequencies at which the gain is 3dB below the peak
gain. Note that all outputs have a gain of 0dB in the passband due to the scaling of K1-K3 in the
Verilog-A code.

Also observe the transient output voltages with Q = 10. Do their amplitudes agree with the expected
results? You can simulate with different input signal frequencies if you are not sure.

Change Q in Fig. 3.5 to 0.707 (no peaking in the LPF and HPF responses). Deactivate the transient
simulation, open the parametric analysis tool from the Analog Environment, and specify the sweep
for the frequency control voltage as in Fig. 3.7. Check that LPF frequency responses for the different
Vf values match Fig. 3.8; afterward generate the same plots for the BPF and HPF case. In each plot,
mark the minimum and maximum value of fo (BPF) or the minimum and maximum value of f3dB
(LPF, HPF). Do the frequency tuning ranges agree with those expected based on the Verilog-A code?
Also simulate with values of Vf outside of the 0.5V-1.5V range; is the control voltages limited
(clipped) in agreement with the above code?

Fig. 3.7: Parametric sweep settings for Vf (shown), VQ, and Vgain

Fig. 3.8: Sweep results example: LPF frequency responses after sweeping control voltage Vf

Keep Q = 0.707 and sweep only VQ with the same settings as those that were used for the Vf sweep
in Fig. 3.7. Plot the BPF responses in one window and mark the 3dB frequencies for the case with
maximum Q before saving the plot for the report. Determine the maximum and minimum quality

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 factors, and comment whether the ratio Qmax / Qmin is expected based on the Verilog-A code. You can
also observe the LPF and HPF responses, even though the plots are not required in the report.
Nevertheless, make comments in the report if you recognize anything that you consider unexpected.

Still with Q = 0.707, sweep Vgain using the same settings as those for the Vf sweep in Fig. 3.7.
Afterwards, plot the HPF filter responses in one window and annotated the minimum and maximum
passband gain. From the magnitude of the maximum and minimum gain (not in dB20) in the
passband, calculate |Gmax| / |Gmin| and compare the ratio with the one expected from the Verilog-A
code. Also plot the LPF and BPF responses to verify functionality, but you do not have to save them
for the report unless you observe unexpected results.

3.4. Behavioral modeling results expected in the lab report

1) Verilog-A model and testbench

a. Screenshot of Fig. 3.3 after inserting your code or print-out of your veriloga.va file
b. Screenshot of the CIW window after quitting the Verilog-A editor without errors,
showing the message: “veriloga Diagnostics: Successful syntax check for veriloga text of
cell VerilogA_Filt2ndOrder.”
c. Snapshot of the testbench schematic for the Verilog-A filter block
2) Simulation results
a. Plots in Fig. 3.6
b. BPF, LPF, HPF frequency responses with Q = 10 (mark frequencies 3dB below peak in
LPF/HPF responses and estimate Q from the plots).
c. From sweep of Vf with Q = 0.707: plots in Fig. 3.8 with annotated minimum and
maximum f3dB, same plots for the HPF case and for BPF case (with min./max. value of
fo marked).
d. From sweep of VQ with Q = 0.707: BPF frequency responses in one window with
marked 3dB frequencies for the Qmax case. What is Qmax / Qmin? Is this ratio in agreement
with the Verilog-A code?
e. From sweep of Vgain with Q = 0.707: HPF filter responses in one window with annotated
minimum and maximum passband gain. Calculate |Gmax| / |Gmin| and compare the ratio
with the one expected from the Verilog-A code.

4. Tunable 8th-Order Chebyshev Filter with the Gm-C Biquad Macromodel

4.1. Chebyshev filter realization and simulation

An 8th-order Chebyshev filter can be constructed by cascading four bandpass Gm-C biquad sections.
Since each section has the transfer function in equation (1), the overall 8th-order Chebyshev transfer
function is:
gm1 g m1 gm1 g m1
s C2
s C2
s C2
s C2
TChebBP (s) = gm 4 g g
× gm 4 gm 2 gm 3
× gm 4 g g
× gm 4 gm 2 gm 3 (5)
s2 +s C2
+ mC2C m 3 s2 +s C2
+ C1C 2
s2 +s C2
+ mC2C m 3 s2 + s C2
+ C1C 2
1 2 1 2

Let us assume that the specifications in Table I are expected to be met in an application and that a
standard method1, Matlab, or other design procedure was applied to derive the center frequencies,

1
For details, see: R. Schaumann and M. E. Van Valkenburg, Design of Analog Filters, Oxford University Press, 2001.
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quality factors, and gains of the biquad sections. For example, the transfer function below is one
possible realization that meets the specifications.
TChebBP( s ) = 1.469×1032 s
× s
× s
× s (6)
s 2 + 2.976×107 s +1.754×1018 s 2 + 6.972×107 s +1.647×1018 s 2 + 6.669×107 s +1.507×1018 s 2 + 2.674×107 s +1.415×1018

Table I: Filter specifications

The Gm-C biquad model now becomes useful to check the derived implementation before starting
circuit-level design, making it possible to re-calculate the parameters for each section before
investing any time on circuit design. Table II lists selected parameters for the four cascaded biquad
sections (Fig. 2.3) that realize the transfer function in (6) to demonstrate the concept. Here, the ratios
of gm1/gm4 were chosen for simplicity rather than optimum gain distribution in each stage based on
linearity, SNR, or other considerations that might be required for certain applications. With ideal
models and the gm1/gm4 ratios in Table II, the two different Gm-C biquads can be formed by
connecting multiple transconductors in parallel to increase gm1 after copying from the schematic in
Fig. 2.3. The resulting cells are shown in Fig. 4.1.

Table II: Parameters for the Gm-C biquads in the Chebyshev Filter
Ratio of
Biquad Q fo gm2 = gm3 = gm4 C1 C2
gm1 / gm4
1 44.5022 210.78 MHz 2 1.25mS 21.209 fF 42.003 pF
2 18.4073 204.25 MHz 3 1.25mS 52.914 fF 17.929 pF
3 18.4075 195.38 MHz 2 1.25mS 55.317 fF 18.743 pF
4 44.4853 189.32 MHz 3 1.25mS 23.622 fF 46.746 pF

a) b)
Fig. 4.1: The two different Gm-C biquads configuration in the Chebyshev filter
a) biquads 1 and 3: gm1/gm4 = 2 b) biquads 2 and 4: gm1/gm4 = 3

Create a new schematic for the Chebyshev filter shown in Fig. 4.2. Before inserting the biquad in
each stage, copy your cell for the circuit in Fig. 2.3 in the library manager and open the new biquad
schematic (e.g. BP_Biquad_1). In this new biquad schematic, add the appropriate number of tunable
transconductor blocks in parallel with gm1 and change the two capacitor values to match Table II for
each of the four biquad stages. Afterwards, insert the different biquads into the schematic (Fig. 4.2)
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together with the same control voltage sources, using variables as previously (Fig. 2.4a). The signal
source has AC magnitude = 1V, amplitude = 1V, frequency = 200MHz.

Fig. 4.2: 8th-order Chebyshev filter

Open a new Analog Environment and change the Project Directory to /tmp (Fig. 1.1). Set up the
following analyses and variables:
Transient: 300ns, conservative
AC: type: linear, 500 total points, range: 160MHz – 250MHz
Vf = Vq = Vgain = 0.75

Run the simulations and plot the frequency response in dB20 (Fig. 4.3). Also plot the phase vs.
frequency and save both plots for the report. Do these plots confirm that the filter response is 8th-
order Chebyshev? Zoom into the passband of the filter until the ripple is clearly visible. Mark the
ripple in the plot and include it in the report. Prepare a table to compare the specifications in Table I
with the simulations results. Finally, plot the transient output voltage with the 200MHz input signal
to be included in the report.

Fig. 4.3: Chebyshev transfer function in dB20

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 4.2. Automatic analog tuning: implementation example

References:

[1] F. Bahmani, T. Serrano-Gotarredona, and E. Sanchez-Sinencio, “An Accurate

Automatic Quality-Factor Tuning Scheme for Second-Order LC Filters,” IEEE
Transactions on Circuits and Systems I, vol. 54, no. 4, April 2007.

[2] T. Sumesaglam and A. I. Karsilayan, “A digital approach for automatic tuning of

continuous-time high-Q filters,” IEEE Transactions on Circuits and Systems II, vol. 50,
no. 10, October 2003.

Quality factors higher than 10 are difficult to achieve with practical Gm-C biquads, especially in the
presence of process, voltage, and temperature (PVT) variations after fabrication. Automatic tuning
circuits help to alleviate PVT variations and to ensure the desired filter response. Behavioral
modeling of the tuning scheme can also reduce design efforts and simplify optimizations.
Nevertheless, simulations with ideal models are not sufficient to determine whether the specified
performance can be guaranteed with the selected design parameters because non-idealities of
components in the tuning circuitry affect the accuracy, stability, and settling time of the tuning loops.
Hence, re-design is often required after the first simulation on the transistor-level.
The analog tuning scheme in this lab is based on the one presented in [1], which is intended for LC
filters. Fig. 4.4 shows a block-level diagram of this tuning method, consisting of a loop for amplitude
tuning and another one for Q-tuning. To tune the Gm-C blocks of the Chebyshev filter from section 3,
the method from [1] was modified by including a frequency tuning loop and using the amplitude
loop for tuning of the overall passband gain (of the cascaded biquads). With this modification, two
master filters and three loops are utilized in the tuning2 (Fig. 4.5).

Fig. 4.4: Analog tuning method described in [1]

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FYI: Using three instead of two tuning loop adds significant complexity and could also lead to stability problems during
transistor-level simulations from circuit parasitics. Depending on the accuracy requirement of the application, Q-tuning and
frequency tuning with two loops is likely to be sufficient for the Gm-C biquads under the assumption that the
transconductors are matched in layout because the passband gain depends on the ratio of transconductors that can be
maintained by sharing the control voltage from the quality factor tuning loop.
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 Fig. 4.5: Analog tuning scheme for the Chebyshev filter (similar to [1])

Create a new schematic and copy the cascaded biquads from the Chebyshev filter in Fig. 4.2 into the
new schematic for automatic tuning simulations. Delete the voltage sources, and construct the tuning
loops as in Fig. 4.5. Below are a high-level description of the three loops and snapshots of zoomed-in
regions of the schematic. Use the same component values and wire labels as displayed in the
snapshots. As done in section 2, make one more copy of the cell for the biquad in Fig. 2.3 and edit it
to match Fig. 4.6 (C1 = 52.914fF, C2 = 17.929pF); this is the biquad for Master 1 and Master 2 in
Fig. 4.5. Note, the master filters are the ones within the tuning loops and the control voltages from
the loops are applied to all sections of the Chebyshev filter using wire labels (Fig. 4.7).

Fig. 4.6: Biquad for Master 1 and Master 2

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 Fig. 4.7: Chebyshev filter with labels for tuning voltages

Frequency tuning loop (Fig. 4.8):

This is the fastest-acting loop consisting of a unity-gain biquad (Master 1), a multiplier (gain =15) to
obtain the product of the input signal and lowpass output, and an integrator (gain = 3e7). The output
of this standard frequency tuning loop from the lecture notes is added to a DC voltage (Vf_dc =
0.5V) to obtain the frequency control voltage (Vf), which is applied to all Biquads in the slave filter
and tuning scheme. Master 1 from Fig. 4.6 has capacitors identical to Biquad 2. The input signal
(Vin) is a sinusoid (frequency = 204.25 MHz, amplitude = 25mV) at the center frequency of the
Master 1/Biquad 2 sections.
FYI: The integrator and multiplier are both in the library ahdlLib.

Q-tuning loop (Fig. 4.9):

The same loop as in [1] was implemented to tune the quality factor. The loop consists of two
multipliers, two lowpass filters, a gain block, and an integrator. One multiplier is used to multiply the
input to the Master 2 Biquad (identical to Master 1) with itself. This input signal (Vtune) is a sine
wave (frequency = 198.702MHz, amplitude = 25mV) with the same frequency as the lower 3dB-
frequency of Masters 1, Master 2, and Biquad 2. The second multiplier is used to multiply the
bandpass output of Master 2 with input (Vtune). Both multiplier outputs are passed through lowpass
filters (LPFs), which are all 1st-order RC LPFs (R = 100kΩ, C = 20pF). The gain (vcvs gain = 2) to
control the desired gain (2/Ad) follows one LPF, where Ad = 1 for unity gain. The subtraction of the
signals is performed with unity-gain voltage-controlled voltage sources (vcvs). A vcvs is also used to
add the error (labeled GainError) from the amplitude tuning loop at the integrator of the Q-tuning
loop. This feedback has the benefit of improved stability because the amplitude error signal provides
feedback to the Q-tuning loop in case the amplitude has not settled yet [1].

Amplitude tuning loop (Fig. 4.10):

Also adapted from [1], this loop has the same configuration as the Q-tuning loop with the exception
that the input (same as to the frequency tuning loop) is at the center frequency of Biquad 2. This
frequency falls into the passband of the Chebyshev filter. Thus, the signal can be used to tune the
passband gain of the cascaded Biquads to 1 (0dB) by adjusting the control voltage (Vgain) of the
input transconductors (gm1). Therefore, any loss from coupling between the filter stages or PVT
variation of the gain can be compensated via tuning.

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Fig. 4.8: Frequency tuning loop

Fig. 4.9: Q-tuning loop

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 Fig. 4.10: Amplitude tuning loop

Simulation of the tuning loops:

Open the Analog Environment from the schematic with Chebyshev filter and tuning circuitry.
Change the Project Directory to /tmp. Afterwards, set up a 2µs long transient simulation
(conservative setting).
Run the 2µs transient simulation and plot the tuning voltages to verify that the start-up response
looks like in Fig. 4.11. Resolve any issues in the schematic if the response looks different. Next,
change the transient simulation time to 30µs and re-simulate. (This simulation will take several
minutes). Plot the transient responses of Vf, Vq, and Vgain after the simulation and include it in the
report. Also, write down the final values of the voltages after settling.

Fig. 4.11: Transient tuning voltages (start-up)

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Simulation of the Chebyshev filter with final values of the tuning voltages:

Re-open the Chebyshev filter schematic in Fig. 4.2 and its Analog Environment. Update the
variables in the Analog Environment with the values of Vf, Vq, and Vgain recorded after the
simulation of the automatic tuning scheme. Re-simulate with the new variables and plot the transfer
function of the tuned filter for the report. Also save a zoomed-in version that shows the marked
passband ripple. Add the results from the new simulation to the comparison table and comment
whether all specifications have been met after tuning.

4.3. Expected Chebyshev filter results in the report

1) Filter characterization (from Fig. 4.2)

a. Schematic of the Chebyshev filter
b. Transfer function (Fig. 4.3) and phase vs. frequency
c. Comment whether the simulation results are in agreement with the theory (8th-order
Chebyshev type)
d. Frequency response with annotated passband ripple
e. Table with comparison of specifications and simulations results
f. Transient output voltage with 200MHz input sinusoid
2) Tuning
a. Screenshot of Chebyshev filter schematic with tuning circuitry
b. Transient plot of Vq, Vf, Vgain after settling (30µs simulation)
i. Provide values of the settled control voltages
c. Filter transfer function after tuning
d. Frequency response with annotated passband ripple after tuning
e. Table comparison of specifications and simulations results with tuned control voltages

4.4. Digital tuning example

The purpose of this subsection is to provide additional information to point out that digital tuning is
also an alternative for a possible tuning project in this course. In the digital case, you also have the
options to implement the tuning circuitry with models from the libraries in Cadence or custom
Verilog-A models. Fig. 4.12 visualizes the technique proposed in reference [2] (listed in section 4.2)
based on phase comparison, which can also be applied as digital tuning scheme for one of the
Biquads in the Chebyshev filter. In this example, only one Biquad was tuned under the same
assumption that the same control voltages are applied to all Biquads as in the analog tuning case. The
simulation setup of a single Biquad and tuning circuitry is shown in Fig. 4.13. Amplitude tuning was
not implemented with the digital scheme and the control voltage of the input transconductors in the
biquads (Vgain) is identical to the output of the Q-tuning loop (Vq). Therefore, the passband gain
relies on the matching accuracy of the ratio of transconductors gm1 and gm4 in the biquads. As
mentioned before, the amplitude tuning loop in the analog scheme can also be omitted to reduce
complexity if approximately 1-2dB more gain variation is acceptable in the application.

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 Fig. 4.12: Digital tuning methodology described in [2]

Fig. 4.13: Digital tuning implementation for the biquad in the Chebyshev filter

It can be observed from Fig. 4.14 that simulation of the digital tuning scheme results in similar
control voltage values for Vf and Vq as with the analog scheme. Using the values for Vf and Vq after
settling as well as Vgain = Vq to simulate the Chebyshev filter as before, the tuned filter response
that meets the given specifications is obtained (Fig. 4.15).

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 Fig. 4.14: Digital tuning: control voltages vs. time

Fig. 4.15: Chebyshev filter frequency response with control voltages after digital tuning
(Vgain = Vq as during the tuning simulation)

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