ABSTRACT

Fuzzy specific hardware systems, or the adaptation of standard

embedded controllers, are the common approaches for real-time fuzzy logic
implementation.

High speed applications may require the more sophisticated hardware,

but most embedded control applications do not have the high speed
processing requirements that necessitate the cost prohibitive enhanced
hardware.

A review of embedded control fuzzy logic applications indicates a

preference for 16-bit architectures; devoting significant processing resources
for fuzzification, rule application, and defuzzification. While faithful to the
foundations of fuzzy logic control, processor demand can limit a controller's
ability to handle peripheral I/O interfaces.

This project describes a generic, hybrid approach suitable for

unenhanced 8-bit microcontrollers and adaptable to most single input, single
output systems.

A motor speed application with real-time I/O interface provides proof

of concept performance data and highlights limitations.
Introduction

The fuzzy control is made on a D.C. shunt motor, with speed sensor
attached. The output characteristics are similar with the c.c. motors. The order
current is quasi rectangular, trapezoidal excitation. DC shunt motor appeared
out of a need for electric drives which would work with variable speed in wide
range. DC shunt motors are classified according the control method used in:

• Open loop control without feedback reaction for rudimentary applications

(pumps, fans);
• closed loop control with feedback reaction using decoders/ transducers.
The control of DC shunt motor with a fuzzy regulator is a closed loop control
method and it is based on fuzzy logic (FL).

The fuzzy logic is a class of artificial intelligence with a recent history and
application. In 1965, Lotfy Zadeh a computer scientist propounded the theory
of fuzzy logic. He argued that human thinking is often fuzzy, vague, or
imprecise in nature, and, therefore cannot be represented by yes (1) or no (0).
Although FL deals with imprecise “IF … THEN …” rules, the information is
processed in sound mathematical theory, which has progressed (seen advances)
in recent years. Each fuzzy set is defined by a linguistic variable (low, large)
which is again defined by a multi valued membership function (MF). An MF
varies between 0 and 1 and can have a range of shapes. The logical operations
on fuzzy sets and crisp sets are and (intersection), or (reunion), not, sum, prod.
The IF part of the rule is defined as antecedent and THEN part is defined as
consequence. The corresponding fuzzy set of each rule is defined by a
linguistic variable.
 The basic steps in fuzzy inference systems (FIS) are:
• Fuzzification of input variables;
• Application of fuzzy operator in the IF part of the rule;
• Implication from the antecedent to the consequent part of the rule;
• Aggregation of the consequents across the rule;
• Defuzzification.
Fuzzification defines the correlation between a crisp value and one or more
linguistic values. The conversion of fuzzy outputs in a fuzzy system into crisp
output is defined as defuzzification. The fuzzy output in constructed by
superimposing the outputs of individual rule. The most usual method of
defuzzification is the center of area method (also called centroid) which
involves integration covering the outer envelope.
Fuzzy logic has two different meanings, in a narrow sense, fuzzy logic is a logical
system, which is an extension of multivolume’s logic, and however, in a wider
sense fuzzy logic is almost synonymous with the theory of fuzzy sets, a theory
which relates to classes of objects with un-sharp boundaries in which membership
is a matter of degree. In this perspective fuzzy logic in its more narrow definition,
fuzzy logic differs both in concept and substance from traditional multi-valued
logical system. Fuzzy logic is a convenient way to map input space to an output
space. Mapping input to output is the starting point for everything.

The main objectives of this study are:-

• To understand the fuzzy logic and how fuzzy rule base system can be
applied in derivation of rules for power system planning, operation and
control.
• To study the MATLAB fuzzy toolbox and understand the concept of
member function & rule base.

• To derive optimal power system operation rules at the macro level for better
performance and control of the power system.

• To develop a fuzzy logic tool for deriving optimal operational rules at the
macro level for better performance and control of power system.
4.1 WHY USE FUZZY LOGIC?
Fuzzy logic offers several unique features that make it a particularly good
choice for many control problems.
• Fuzzy logic is conceptually easy to understand. The mathematical concepts
behind fuzzy reasoning are very simple. Fuzzy logic is a more intuitive
approach without the for-reachicomplexity. Fuzzy logic is flexible. Fuzzy
logic is tolerant of imprecise data. Fuzzy logic can model non-linear
function of arbitrary complexity. Fuzzy logic is based on natural language.

• It is inherently robust since it does not require precise, noise-free inputs and
can be programmed to fail safely if a feedback sensor quits or is destroyed.
The output control is a smooth control function despite a wide range of input
variations.

• Since the Fuzzy logic controller processes user-defined rules governing the
target control system, it can be modified and tweaked easily to improve or
drastically alter system performance. New sensors can easily be incorporated
into the system simply by generating appropriate governing rules.

• Fuzzy logic is not limited to a few feedback inputs and one or two control
outputs, nor is it necessary to measure or compute rate-of-change parameters
in order for it to be implemented. Any sensor data that provides some
indication of a system's actions and reactions is sufficient. This allows the
sensors to be inexpensive and imprecise thus keeping the overall system cost
and complexity low.
• Because of the rule-based operation, any reasonable number of inputs can be
processed (1-8 or more) and numerous outputs (1-4 or more) generated,
although defining the rule base quickly becomes complex if too many inputs
and outputs are chosen for a single implementation since rules defining their
interrelations must also be defined.

• It would be better to break the control system into smaller chunks and use
several smaller Fuzzy logic controllers distributed on the system, each with
more limited responsibilities.

• Fuzzy logic can control nonlinear systems that would be difficult or

impossible to model mathematically. This opens doors for control systems
that would normally be deemed unfeasible for automation.
4.2 HOW FUZZY LOGIC IS USED?
1) Define the control objectives and criteria: What am I trying to control? What do
I have to do to control the system? What kind of response do I need? What are the
possible (probable) system failure modes?
2) Determine the input and output relationships and choose a minimum number of
variables for input to the Fuzzy logic engine (typically error and rate-of-change-of-
error).
3) Using the rule-based structure of Fuzzy logic, break the control problem down
into a series of IF X AND Y THEN Z rules that define the desired system output
response for given system input conditions.
4) Create Fuzzy logic membership functions that define the meaning (values) of
Input /Output terms used in the rules.
5) Create the necessary pre- and post-processing Fuzzy logic routines if
implementing in software, otherwise program the rules into the Fuzzy logic
hardware engine.
6) Test the system, evaluate the results, tune the rules and membership functions,
and retest until satisfactory results are obtained.

Fuzzy logic control is a control algorithm based on a linguistic control strategy,

which is derived from expert knowledge into an automatic control strategy. Fuzzy
logic control doesn't need any difficult mathematical calculation like the others
control system. While the others control system use difficult mathematical
calculation to provide a model of the controlled plant, it only uses simple
mathematical calculation to simulate the expert knowledge. Although it doesn't
need any difficult mathematical calculation, but it can give good performance in a
control system. Thus, it can be one of the best available answers today for a broad
class of challenging controls problems.

Block diagram of Fuzzy Logic Controller

5.1 BASIC CONFIGURATION OF FUZZY LOGIC CONTROLLER (FLC):-
BLOCK DIAGRAM:-

Fuzzy logic control is derived from fuzzy set theory. In fuzzy set theory, the
transition between membership and non-membership can be graded. Therefore,
boundaries of fuzzy sets can be vague and ambiguous, making it useful for
approximate systems. Fuzzy Logic Controller (FLC) is an attractive choice when
precise mathematical formulations are not possible. Other advantages are
• It can work with less precise inputs.

• It doesn’t need fast processors.

• It needs less data storage in the form of membership functions and rules than
conventional look up table for nonlinear controllers.

• It is more robust than other non-linear controllers.

There are three principal elements to a fuzzy logic controller.

a. Fuzzification module (Fuzzifier)
b. Rule base and Inference engine
c. Defuzzification module (Defuzzifier)
5.2a Fuzzification: -

The first step in designing a fuzzy controller is to decide which state

variables represent the system dynamic performance must be taken as the input
signal to the controller. Fuzzy logic uses linguistic variables instead of numerical
variables. The process of converting a numerical variable (real number or crisp
variables) into a linguistic variable (fuzzy number) is called Fuzzification. System
variables, which are usually used as the fuzzy controller inputs includes states
error, state error derivative, state error integral or etc. In power system, based on
previous experience, Area Control Error and its derivative (d(ACE)/dt) are chosen
to be the input signals of fuzzy AGC.
The membership function is a graphical representation of the magnitude of
participation of each input. There are different memberships functions associated
with each input and output response. In this study, we use the trapezoidal
membership function for input and output variables. The number of membership
function determines the quality of control which can be achieved using fuzzy
controller. As the number of membership function increases, the quality of control
improves. As the number of linguistic variables increases, the computational time
and required memory increases. Therefore, a compromise between the quality of
control and computational time is needed to choose the number of linguistic
variables. For the speed control of DC motor study, five linguistic variables for
each of the input and output variables are used to describe them, as in the
following Table.
5.2b DEFUZZIFICATION:-
The reverse of Fuzzification is called Defuzzification. The use of Fuzzy
Logic Controller (FLC) produces required output in a linguistic variable (fuzzy
number). According to real world requirements, the linguistic variables have to be
transformed to crisp output. Centre of gravity method is the best well-known
defuzzification method and used in this research work. Sugeno type of
defuzzification method is adopted in this work. It obtains the center of area
occupied by the fuzzy set. It is given by the expression.

Defuzzification is the process of producing a quantifiable result in fuzzy logic.

Typically, a fuzzy system will have a number of rules that transform a number of
variables into a "fuzzy" result, that is, the result is described in terms of
membership in fuzzy sets. For example, rules 33 designed to decide how much
pressure to apply might result in "Decrease Pressure (15%), Maintain Pressure
(34%), Increase Pressure (72%)". Defuzzification would transform this result into a
single number indicating the change in pressure. The simplest but least useful
defuzzification method is to choose the set with the highest membership, in this
case, "Increase Pressure" since it has a 72% membership, and ignore the others,
and convert this 72% to some number. The problem with this approach is that it
loses information. The rules that called for decreasing or maintaining pressure
might as well have not been there in this case.
A useful defuzzification technique must first add the results of the rules
together in some way. The most typical fuzzy set membership function has the
graph of triangle. Now, if this triangle were to be cut in a straight horizontal line
somewhere between the top and the bottom, and the top portion were to be
removed, the remaining portion forms a trapezoidal. The first step of
defuzzification typically "chops off" parts of the graphs to form trapezoids (or
other shapes if the initial shapes were not triangles). For example, if the output has
"Decrease Pressure (15%)", then this triangle will be cut 15% the way up from the
bottom. In the most common technique, all of these trapezoids are then
superimposed one upon another, forming a single geometric. Then, the centroid of
this shape, called the fuzzy centroid, is calculated. The x coordinate of the centroid
is the defuzzified value.
5.3 Fuzzy control in detail:-
Fuzzy controllers are very simple conceptually. They consist of an input stage, a
processing stage, and an output stage. The input stage maps sensor or other inputs,
such as switches, thumbwheels, and so on, to the appropriate membership
functions and truth values. The processing stage invokes each appropriate rule and
generates a result for each, then combines the results of the rules. Finally, the
output stage converts the combined result back into a specific control output value.
The most common shape of membership functions is triangular, although
trapezoidal and bell curves are also used, but the shape is generally less important
than the number of curves and their placement. From three to seven curves are
generally appropriate to cover the required range of an input value, or the "universe
of discourse" in fuzzy jargon.
As discussed earlier, the processing stage is based on a collection of logic
rules in the form of IF-THEN statements, where the IF part is called the
"antecedent" and the THEN part is called the "consequent". Typical fuzzy control
systems have dozens of rules.
Consider a rule for a thermostat:
“IF temperature is COLD then heater is HIGH”
This rule uses the truth value of the "temperature" input, which is some truth value
of "cold", to generate a result in the fuzzy set for the "heater" output, which is
some value of "high". This result is used with the results of other rules to finally
generate the crisp composite output. Obviously, the greater the truth value of
"cold", the higher the truth value of "high", though this does not necessarily mean
that the output itself will be set to "high", since this is only one rule among many.
In some cases, the membership functions can be modified by "hedges" that are
equivalent to adjectives. Common hedges include "about", "near", "close to",
"approximately", "very", "slightly", "too", "extremely", and "somewhat". These
operations may have precise definitions, though the definitions can vary
considerably between different implementations.
In practice, the fuzzy rule sets usually have several antecedents that are
combined using fuzzy operators, such as AND, OR, and NOT, though again the
definitions tend to vary: AND, in one popular definition, simply uses the minimum
weight of all the antecedents, while OR uses the maximum value. There is also a
NOT operator that subtracts a membership function from 1 to give the
"complementary" function.
There are several different ways to define the result of a rule, but one of the
most common and simplest is the "max-min" inference method, in which the
output membership function is given the truth value generated by the premise.
Rules can be solved in parallel in hardware, or sequentially in software. The results
of all the rules that have fired are "defuzzified" to a crisp value by one of several
methods. There are dozens in theory, each with various advantages and drawbacks.
The "centroid" method is very popular, in which the "centre of mass" of the result
provides the crisp value. Another approach is the "height" method, which takes the
value of the biggest contributor. The centroid method favors the rule with the
output of greatest area, while the height method obviously favors the rule with the
greatest output value. The diagram below demonstrates max-min inferencing and
centroid defuzzification for a system with input variables "x", "y", and "z" and an
output variable "n". Note that "mu" is standard fuzzy-logic nomenclature for "truth
value".

Theoretical background
2.1 Fundamentals of DC Motor
The commonly used configuration of the dc motors is shown below in figure . In a
separately excited motor, the armature and the field coil are connected to different
dc source. This gives the configuration total control over the armature and the field
voltage separately. In the shunt motor, both coils have a common source. In case of
the series motor, both the armature and the field current are the same. In the
cumulatively compound motor, the magneto-motive force of the series field is a
function of armature current and is in the same direction as mmf of the shunt field.

Figure 2-1Commonly used DC motors

The steady state equivalent circuit of armature of a dc machine is shown in the
figure 2-2. Resistance Ra is the resistance of the armature circuit. In shunt and
separate excited motor it is the resistance of the armature coil whereas for series it
is the sum of the field and the armature coil. The basic equation of the system is as
follows:
E = KeФwm [1.1]
V = E + RaIa [1.2]
T = KeФIa [1.3]
where,
E(V) = the back emf produced by the motor
Ф (Tesla,T) = the flux created by the field coil and is dependent upon the field
current
wm (rads-1) = the angular velocity of the motor
V(V) = supplied dc voltage
RRa (Ω)= the equivalent resistance of the armature circuit
Ia (A) = armature current
Ke = the motor constant

Figure 2-2 Steady state equivalent circuit of the armature

From these general mathematical equations of the dc motor, we can come to
various important conclusions. It can be seen that as the speed increases the back
e.m.f alse increase. The torque provided by the motor is directly proportional to the
field flux and the armature current. In case of the shunt and separately excited
motor, the field current remains constant. Where as in series motor, the armature
current and the field current are equal and can be controlled by different
mechanism. The series motor is usually used when high starting torque is required.
The two most important characteristics of the dc motors are the Speed-torque
characteristics and the Torque-current characteristics. They play vital role during
the process of motor selection for a particular application. These are the dictionary
of the motor through which engineers can compare between different motors and
make an appropriate selection. The profile for the different types of motors is
different. The characteristic curves are shown in the figure 2-3 and 2-4.

Figure 2-3 Torque-current curves Figure 2-4 Speed-torque curves

The nature of the curve can be justified by the nature of the equations. In shunt and
separate, the curve is linear due to the direct relationship between the variables i.e.
the constant field current. But in case of the series and the compound the torque is
dependent upon two changing variables the armature current and the field current.
Among these different types of motors, the project is concerned only with the
separately excited dc motor. Therefore from now onwards we will be dealing only
with the separately excited dc motor in greater depth. The transient and the steady
response of the motor will be analyzed with required mathematical details.
HARDWARE DETAILS:
Microcontroller atmega16:

Pin diagram:

Features:

 High-performance, low-power avr, 8-bit microcontroller

 Advanced risc architecture
 Nonvolatile program and data memories
 Two 8-bit timer/counters with separate prescaler, one compare mode
 Byte-oriented two-wire serial interface
 Programmable serial usart
  Master/slave spi serial interface
 Programmable watchdog timer with separate on-chip oscillator
 On-chip analog comparator
 Power-on reset and programmable brown-out detection
 Internal calibrated rc oscillator
 External and internal interrupt sources
 I/o and packages
 23 programmable i/o lines
 28-lead pdip, 32-lead tqfp, and 32-pad mlf
 Operating voltages
 2.7 - 5.5v (atmega16l)
 4.5 - 5.5v (atmega16)
 Speed grades
 0 - 8 mhz (atmega16l)
 0 - 16 mhz (atmega16)

Description:
The atmega16 is a low-power cmos 8-bit microcontroller based on
the avr risc architecture. By executing powerful instructions in a single clock cycle,
the atmega16 achieves throughputs approaching 1 mips per mhz, allowing the
system designer to optimize power consumption versus processing speed. The avr
core combines a rich instruction set with 32 general-purpose working registers. All
the 32 registers are directly connected to the arithmetic logic unit (alu), allowing
two independent registers to be accessed in one single instruction executed in one
clock cycle. The resulting architecture is more code efficient while achieving
throughputs upto ten times faster than conventional cisc microcontrollers.
 The device is manufactured using atmel’s high-density non-volatile
memory technology. The flash program memory can be reprogrammed in-system
through an spi serial interface, by a conventional non-volatile memory
programmer, or by an on-chip boot program running on the avr core. The boot
program can use any interface to download the application program in the
application flash memory. Software in the boot flash section will continue to run
while the application flash section is updated, providing true read-while-write
operation. By combining an 8-bit risc cpu with in-system self-programmable flash
on a monolithic chip, the atmel atmega16 is a powerful microcontroller that
provides a highly flexible and cost-effective solution to many embedded control
applications. The atmega16 avr is supported with a full suite of program and
system development tools, including c compilers, macro assemblers, program
debugger/simulators, in-circuit emulators, and evaluation kits.
Pin descriptions:

• Vcc - digital supply voltage.

• Gnd - ground.

• Avcc:
Avcc is the supply voltage pin for the a/d converter, port c (3-
0) and adc (7-6). It should be externally connected to vcc, even if the adc
is not used. If the adc is used, it should be connected to vcc through a
low-pass filter. Note that port c (5-4) use digital supply voltage, vcc.

• Aref:
Aref is the analog reference pin for the a/d converter.
 • PORT B: (PB7 – PB0)

Port b is an 8-bit bi-directional i/o port with internal pull-up

resistors (selected for each bit). The port b output buffers have symmetrical drive
characteristics with both high sink and source capability. As inputs, port b pins that
are externally pulled low will source current if the pull-up resistors are activated.
The port b pins are tri-stated when a reset condition becomes active, even if the
clock is not running.

• Port c: (pc5 - pc0)

Port c is a 7-bit bi-directional i/o port with internal pull-up

resistors (selected for each bit). The port c output buffers have symmetrical drive
characteristics with both high sink and source capability. As inputs, port c pins that
are externally pulled low will source current if the pull-up resistors are activated.
The port c pins are tri-stated when a reset condition becomes active, even if the
clock is not running.
• Port d: (pd7- pd0)

Port d is an 8-bit bi-directional i/o port with internal pull-up

resistors (selected for each bit). The port d output buffers have symmetrical drive
characteristics with both high sink and source capability. As inputs, port d pins that
are externally pulled low will source current if the pull-up resistors are activated.
The port d pins are tri-stated when a reset condition becomes active, even if the
clock is not running.
• Pc6/reset:
 If the rstdisbl fuse is programmed, pc6 is used as an i/o pin.
Note that the electrical characteristics of pc6 differ from those of the other pins of
port c pc6 is used as a reset input.
Reset (reset input). A low level on this pin for longer than the
minimum pulse length will generate a reset, even if the clock is not running.

Functional block diagram of microcontroller atmega16:

AVR CPU CORE:

Introduction:
 This section discusses the avr core architecture in general. The main
function of the cpu core is to ensure correct program execution. The cpu must
therefore be able to access memories, perform calculations, control peripherals,
and handle interrupts.
Architectural overview:
In order to maximize performance and parallelism, the avr uses harvard
architecture with separate memories and buses for program and data. Instructions
in the program memory are executed with a single level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program
memory. This concept enables instructions to be executed in every clock cycle.
The program memory is in system reprogrammable flash memory. The fast-access
register file contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle arithmetic logic unit (alu)
operation. In a typical alu operation, two operands are output from the register file,
the operation is executed, and the result is stored back in the register file – in one
clock cycle.
1.1.1.1.1.1

1.1.1.1.1.2 ARITHMETIC LOGIC UNIT – ALU:

The high-performance avr alu operates in direct connection with all the 32
general purpose-working registers. Within a single clock cycle, arithmetic
operations between general-purpose registers or between a register and an
immediate are executed. The alu operations are divided into three main categories
– arithmetic, logical, and bit-functions. Some implementations of the architecture
also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “instruction set” section for a detailed description.
Status register:

The status register contains information about the result of the most recently
executed arithmetic instruction. This information can be used for altering program
flow in order to perform conditional operations. Note that the status register is
updated after all alu operations, as specified in the instruction set reference. This
will in many cases remove the need for using the dedicated compare instructions,
resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt
routine and restored when returning from an interrupt. This must be handled by
software.
The global interrupt enable bit must be set for the interrupts to be enabled.
The individual interrupt enable control is then performed in separate control
registers. If the global interrupt enable register is cleared, none of the interrupts are
enabled independent of the individual interrupt enable settings. The i-bit is cleared
by hardware after an interrupt has occurred, and is set by the reti instruction to
enable subsequent interrupts. The i-bit can also be set and cleared by the
application with the sei and cli instructions, as described in the instruction set
reference.

Bit 6 – t: bit copy storage

The bit copy instructions bld (bit load) and bst (bit store) use the t-bit as
source or destination for the operated bit. A bit from a register in the register file
can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a
register in the Register file by the bld instruction.
Bit 5 – h: half carry flag
 The half carry flag h indicates a half carry in some arithmetic operations.
Half carry is useful in bcd arithmetic. See the “instruction set description” for
detailed information.

Bit 4 – s: sign bit, s = n or v

The s-bit is always an exclusive or between the negative flag n and the
two’s complement overflow flag v. See the “instruction set description” for
detailed information.
Bit 3 – v: two’s complement overflow flag
The two’s complement overflow flag v supports two’s complement
arithmetics. See the “instruction set description” for detailed information.
Bit 2 – n: negative flag
The negative flag n indicates a negative result in an arithmetic or logic
operation. See the “instruction set description” for detailed information.

Bit 1 – z: zero flag

The zero flag z indicates a zero result in an arithmetic or logic operation. See
the “instruction set description” for detailed information.
Bit 0 – c: carry flag
The carry flag c indicates a carry in an arithmetic or logic operation. Set
description” for detailed information.

1.1.1.1.1.2.1 General purpose register file:

 The register file is optimized for the avr enhanced risc
instruction set. In order to achieve the required performance and flexibility, the
following input/output schemes are

Supported by the register file:

• One 8-bit output operand and one 8-bit result input.

• Two 8-bit output operands and one 8-bit result input.
• Two 8-bit output operands and one 16-bit result input.
• One 16-bit output operand and one 16-bit result input.

 THE X-REGISTER, Y-REGISTER AND Z-REGISTER:

The registers r26, r31 have some added functions to their general-
purpose usage. These registers are 16-bit address pointers for indirect addressing of
the data space.
 Stack pointer:
The stack is mainly used for storing temporary data, for storing local
variables and for storing return addresses after interrupts and subroutine calls. The
stack pointer register always points to the top of the stack. Note that the stack is
implemented as growing from higher memory locations to lower memory
locations. This implies that a stack push command decreases the stack pointer.

The stack pointer points to the data sram stack area where the
subroutine and interrupt stacks are located. This stack space in the data sram must
be defined by the program before any subroutine calls are executed or interrupts
are enabled. The stack pointer must be set to point above 0x60. The stack pointer is
decremented by one when data is pushed onto the stack with the push instruction,
and it is decremented by two when the return address is pushed onto the stack with
subroutine call or interrupt. The stack pointer is incremented by one when data is
popped from the stack with the pop instruction, and it is incremented by two when
address is popped from the stack with return from subroutine ret or return from
interrupt reti.
The avr stack pointer is implemented as two 8-bit registers in the i/o
space. The number of bits actually used is implementation dependent. Note that the
data space in some implementations of the avr architecture is so small that only spl
is needed. In this case, the sph register will not be present.

 INSTRUCTION EXECUTION TIMING:

This section describes the general access timing concepts for
instruction execution. The avr cpu is driven by the cpu clock cpu, directly
generated from the selected clock source for the chip. No internal clock division is
used.
 RESET AND INTERRUPT HANDLING:

The avr provides several different interrupt sources. These

interrupts and the separate reset vector each have a separate program vector in the
program memory space. All interrupts are assigned individual enable bits which
must be written logic one together with the global interrupt enable bit in the status
register in order to enable the interrupt. Depending on the program counter value,
interrupts may be automatically disabled when boot lock bits blb02 or blb12 are
programmed.
  Interrupt response time:

The interrupt execution response for all the enabled avr interrupts
is four-clock cycles minimum. After four clock cycles, the program vector
address for the actual interrupt handling routine is executed. During this 4-clock
cycle period, the program counter is pushed onto the stack. The vector is
normally a jump to the interrupt routine, and this jump takes three clock cycles.
If an interrupt occurs during execution of a multi-cycle instruction, this
instruction is completed before the interrupt is served. If an interrupt occurs
when the mcu is in sleep mode, the interrupt execution response time is
increased by four clock cycles. This increase comes in addition to the start-up
time from the selected sleep mode.
 Avr atmega16 memories:
This section describes the different memories in the atmega16. The
avr architecture has two main memory spaces, the data memory and the program
memory space. In addition, the atmega16 features an eeprom memory for data
storage. All three memory spaces are linear and regular.
Types of memories:
• In-system reprogrammable flash program memory:

The atmega16 contains 8k bytes on-chip in-system reprogrammable

flash memory for program storage. Since all avr instructions are 16- or 32-bits
wide, the flash is organized as 4k x 16 bits. For software security, the flash
program memory space is divided into two sections, boot program section and
application program section.
The flash memory has an endurance of at least 10,000 write/erase
cycles. The atmega16 program counter (pc) is 12 bits wide, thus addressing the 4k
program memory locations. The operation of boot program section and associated
boot lock bits for software protection are described in detail in “boot loader support
– read-while-write self-programming” on page 206. “memory programming” on
page 219 contains a detailed description on flash programming in spi- or parallel
programming mode. Constant tables can be allocated within the entire program
memory address space (see the lpm – load program memory instruction
description).

• Data memory:
.
The lower 1120 data memory locations address the register file, the i/o
memory, and the internal data sram. The first 96 locations address the register file
and i/o memory, and the next 1024 locations address the internal data sram. The
five different addressing modes for the data memory cover: direct, indirect with
displacement, indirect, indirect with pre-decrement, and indirect with post-
increment. In the register file, registers r26 to r31 feature the indirect addressing
pointer registers.
• EEprom data memory:

The atmega16 contains 512 bytes of data eeprom memory. It is

organized as a separate data space, in which single bytes can be read and
written. The eeprom has an endurance of at least 100,000 write/erase cycles.
The access between the eeprom and the cpu is described bellow, specifying the
 eeprom address registers, the eeprom data register, and the eeprom control
register.
Eeprom read/write access: the eeprom access registers are
accessible in the i/o space.

• I/o memory:

All atmega16 i/os and peripherals are placed in the i/o space. The i/o
locations are accessed by the in and out instructions, transferring data between the
32 general-purpose working registers and the i/o space. I/o registers within the
address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi
instructions. In these registers, the value of single bits can be checked by using the
sbis and sbic instructions. Refer to the instruction set section for more details.
When using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f
must be used. When addressing i/o registers
As data space using ld and st instructions, 0x20 must be added to these addresses.
For compatibility with future devices, reserved bits should be written to zero if
accessed.

Boot loader support – read- while-write Self- programming

The boot loader support provides a real read-while-write self-programming

mechanism for downloading and uploading program code by the mcu itself. This
feature allows flexible application software updates controlled by the mcu using a
flash-resident boot loader program. The boot loader program can use any available
data interface and associated protocol to read code and write (program) that code
into the flash memory, or read the code from the program memory.
The program code within the boot loader section has the capability to write into the
entire flash, including the boot loader memory. The boot loader can thus even
modify itself, and it can also erase itself from the code if the feature is not needed
anymore. The size of the boot loader memory is configurable with fuses and the
boot loader has two separate sets of boot lock bits which can be set independently.
This gives the user a unique flexibility to select different
Boot loader
Features
• read-while-write self-programming

• flexible boot memory size

• high security (separate boot lock bits for a flexible protection)

• separate fuse to select reset vector

• optimized page size

• code efficient algorithm

• efficient read-modify-write support

Application and boot loader flash sections

The flash memory is organized in two main sections, the application

section and the boot loader section the size of the different sections is configured
by the bootsz fuses as shown. These two sections can have different level of
protection since they have different sets of lock bits.

Application section
The application section is the section of the flash that is used for
storing the application code.
The protection level for the application section can be selected by the
application boot lock bits. The application section can never store any boot loader
code since the spm instruction is disabled when executed from the application
section.
Bls – boot loader section
While the application section is used for storing the application code,
the the boot loader software must be located in the bls since the spm instruction
can initiate a programming when executing from the bls only. The spm instruction
can access the entire flash, including the bls itself. The protection level for the boot
loader section can be selected by the boot loader
Read-while-write and no read- while-write flash sections
Whether the cpu supports read-while-write or if the cpu is halted
during a boot loader software update is dependent on which address that is being
programmed. In addition to the two sections that are configurable by the bootsz
fuses as described above, the flash is also divided into two fixed sections, the read-
while-write (rww) section and the no read-while- write (nrww) section. The limit
between the rww- and nrww sections is given. The main difference between the
two sections is:
when erasing or writing a page located inside the rww section, the nrww section
can be read during the operation.
when erasing or writing a page located inside the nrww section, the cpu is halted
during the entire operation.

Note that the user software can never read any code that is located inside the rww
section during a boot loader software operation. The syntax “read-while-write
section” refers to which section that is being programmed (erased or written), not
which section that actually is being read during a boot loader software update.

Switching element
Switching element are the important part of any electric drive. Switching element
provides the power to the load. The switching element should have following
characteristics.
• Minimum conduction loss
• Minimum switching loss
There are various types of switching element, among them MOSFET (Metal oxide
semiconductor field effect transistor) and IGBT (insulated gate bipolar transistor)
are mostly used in the electric drive.
2.2.1 Metal oxide semiconductor field effect transistor (MOSFET)
Power MOSFETs are the voltage controlled device requiring small current to turn
ON. Switching speed of the Power MOSFET is very high (of the order of
nanosecond). They are mostly used in low and medium power and high frequency
application. Figure 2-10 shows the symbol and the internal structure of the power
MOSFET. The characteristics curve of the MOSFET is given in figure 2-11.

Figure 2-10 Power MOSFET (a) Symbol (b) Vertical cross section

Figure 2-11 Characteristics curve of the MOSFET

2.2.2 Insulated Gate bipolar transistor (IGBT)
IGBT is the combination of the MOSFET and the power BJTs. BJTs have low ON
state resistance as a result it has low conduction loss, but it suffer from the high
switching loss. On the other hand, MOSFET have low switching loss but due to its
high ON state resistance it has high conduction loss. IGBT combines the
advantages of both BJT an MOSFET, hence it has low conduction and switching
loss. Figure 2-12(b) shows equivalent circuit symbol of the IGBTs.

Figure 2-12 IGBT (a)Symbol (b) Equivalent circuit model (c) Vertical cross
section
Figure 2-13 Characteristics curve of the IGBT

2.2.3 Comparison of IGBT and MOSFET

IGBT are suited for the high power application because they have higher break
down voltage. The switching loss of the IGBT is higher than the MOSFET so they
are suitable for the medium frequency application. MOSFET has lower break
down voltage in comparison to the IGBT so they are suited for the medium and
low power application. The switching loss of the MOSFET is small in comparison
to the IGBT so they are used in the high frequency application up to 100 KHz.
The figure 2-14 shows the comparison of the MOSFET and IGBT in term of the
operating voltage and the frequency.

Figure 2-14 Comparison of the IGBT and MOSFET

2.2.4 Gate Drive Circuit
The Gate drive circuit provides control signal to the switching elements of any
electric drive .The simple gate drive circuit is shown in figure 16a. In this figure
the switching element consists of the MOSFET but actually it can be replaced by
any power transistor such as IGBT, BJT. Here the gate drive circuit consists of the
simple source which provides the control voltage between gate and source and
turns ON the MOSFET and as a result of which, current is provided to the load
from VBatt.

In the figure 2-9 C and D are known as Lower side transistor. There are various
gate drive circuits for the lower side transistor. Fig 2-15 and 2-16 shows the
gate drive circuit for the lower side transistors. The gate drive circuit implementing
totem pole is better than the gate drive circuit of figure 2-16 because the switching
time for the totem pole transistors is fast.

Figure 2-15 Simple Gate Drive circuit

In the figure 2-9, A and B are known as the higher side transistors. The gate drive
circuit for the higher side transistors is different from the lower side transistors due
to the presence of the floating voltage. Transformer and the optocoupler are used to
drive the higher side transistors, but they have their own disadvantages. The best
gate drive circuit for the higher side transistor is known as bootstrap circuit.
 Figure 2-16 Bootstrap circuit
When VCC is applied at the PWM Input current from the bootstrap capacitor
passes through resistor R1 to turn ON the transistor Q3. When Q3 is ON (i.e. in
active region) gate charge to the transistor Q1 is provided by the Bootstrap
capacitor. When 0V is applied in the PWM Input, current flows through R1 and R2
as a result of which Q3 moves in cut off mode and Q4 in the active mode as a
result of which gate charge of the Q1 is discharge through Rgate.
3 Design and Implementation
3.1 Proposed System Overview
The system is a closed loop system which consists of a command signal,
processing unit plant and feedback as shown in figure 3-1.
The overall block diagram of our system is given below.
Figure 3-1 Block Diagram of the whole system
Curtis controller does not implement any control system theory. It relies on the
input command given by the user. In other words, it is an open loop control
system. But the system designed in the project is a closed loop as mentioned
above. In the system, the command is reference velocity given through the
computer using parallel port. The project is not concerned with the means of
command signal but instead with the controller only. Therefore the project mainly
focuses on the design of the entire block in the Fig 3-1. The main block of the
system is the core of the system – the controller. For the processing of the error
signal fuzzy control has been employed due to its efficiency in design and its ease
of execution. In other words, the system is a discrete control system. The controller
generates a control signal i.e. PWM output to the Full Bridge DC-DC Converter.
The DC-DC converter drives the motor is four quadrants (Motoring and Braking in
both direction). The velocity feedback is employed using the concept of optical
encoder. The feedback signal is processed through the microcontroller and the
required error signal is generated.
3.2 Driver Circuit
The driver circuit used in this project is given in figure 3-2. In this circuit
MOSFET has been implemented as the switching element. The reasons for
implementing MOSFET are given below.
• MOSFET provides minimum switching and conduction loss.
• The availability of the MOSFET in the local market is greater than the
IGBT
• Since this driver circuit is of the medium power level, MOSFET is best
suited. The circuit consists of the MOSFET in the parallel combination. By
implementing in parallel, the switching loss is minimized in the MOSFET. The
gate drive circuit has been implemented using the IC IR2110. This IC has the
bootstrap circuit for the higher side transistors and totem pole for driving lower
side transistor.

3.3 Fuzzy implementation in the project

In general, fuzzy controllers may be classified into two types according to fuzzy
controller input. For the first type, the fuzzy controller is based on the traditional
control theory, e.g. fuzzy PID controller; regarding the second type, the controller
is constructed with assistance of some useful approaches, such as fuzzy neural
network and genetic algorithms, etc. In the project, the fuzzy PID control is used as
the working method. This method requires a mathematical model of the motor.
Moreover we have used the fuzzy PI controller. The input to the controller is
velocity error (e) and the change of this error (de). The inputs are then fuzzified,
rule is applied and the fuzzy output is defuzzified to give a crisp output
which is the change in the PWM width. Hardware implementation of the controller
can be achieved in a number of ways.
The most popular method of implementing fuzzy controller is using a
general-purpose microprocessor or microcontroller. General, 8-bit microcontroller
are more economical and flexible, but often face difficulties in dealing with control
systems that require high processing and input/output handling speeds. As an
option, the controller can be implemented on a FPGA, which is suitable for fast
implementation and quick hardware verification. FPGA based systems are flexible
and can be reprogrammed unlimited number of times. For designing the Fuzzy
rules and simulating the rules Matlab® Ver. 7.4.0.287(R2007a) was used. Rules
were written using its fuzzy tool and the dc motor’s speed control using the fuzzy
controller was simulated using Simulink. The input and output membership
functions and rules used in the controller are shown below.

Figure 3-3 Membership functions of inputs

Figure 3-4 Membership Function of output

Figure below shows the Simulink model of the controller and the result obtained.
The result shows the desired speed and the actual speed obtained from the dc
motor model.

PWM implementation
The single mosfet is used to drive the motor operates with the Pulse Width
Modulated (PWM) control signal. This signal is applied to the gate of MOSFETs
building the bridge. The duty cycle of this PWM signal is controlled by the fuzzy
controller. The PWM generator was implemented into the microcontroller. The
PWM generator generates 9.765 KHz PWM signal. The block diagram of the
PWM generator is shown below.
Figure 3-13 PWM generator block
The PWM generator has three modules or segments within it, namely
dutycycle_register, clk_counter and count_comparator. When a new duty cycle is
sent to the dutycycle register from the Fuzzy controller and then setting the Reset
pin high, the current count in the clk_count is stopped and the counter resets to
zero count (getting ready for next count). Also the high on Reset pin latches the
input new duty cycle into the dutycycle_register. The count_comparator
continuously compares the count value to the register value and generates PWM
output low after the count reaches the register value. Before that the PWM output
is high.
Figure 3-14 PWM generation
3.6 Feedback mechanism
The velocity feed back in terms of the revolution per minute (RPM) was sensed
using an opto-interrupter (also known as beam breaker). Opto-interrupter consists
of a infrared emitting diode and photo transistor aligned such that the emitted beam
falls on photo sensitive base of the photo transistor. A slotted disk as shown in the
figure below breaks the beam at regular interval and hence generates train of
pulses. Then the no of system frequency (10 KHz) clock pulses that fall on these
pulses (high or low) is counted. This count gives the width of a slot in terms of no
of 10 KHz pulse ie, in terms of time. From the already known slots count (30 open
and 30 closed slots) time for one revolution is determined by multiplying the slot
width (in time) with slot count. Its reciprocal gives us the revolution per sec, from
where RPM can be determined by multiplication with

.
Figure 3-15 Opto – interrupter

Figure 3-16 Slotted disk

Figure 3-17 Implementation of Opto-interrupter
Equation for finding the RPM;
System frequency
2 x Count = Revolution per minute (RPM)
Where,
Count = no of system frequency clock pulses that fall on high or low pulse from
the opto-interrupter
7.1 Conclusion

The Electric Drive technology is an alternative to the current fuel crisis and
the increasing environmental issues. Hence, the project has mounted itself to the
fundamentals of the speed controller. It deals with the problem of high current
driver circuit and an efficient algorithmic based control (Fuzzy Logic) to track the
velocity. The necessary component for this design was easily available in the local
market. The design was based on the choice of the MOSFET that could handle the
required current. In order to drive the gate of the MOSFET, a method known as
Bootstrap was used.
The circuit was successfully implemented and tested. The traditional analog
control of the motor’s speed requires the knowledge of the accurate mathematical
model which is very difficult to determine and varies with each motor, even with
the same manufactures’ specification. This makes the design inflexible. But in
contrast, the discrete control system has the advantage of employing complex
mathematical algorithm that is efficient and accurate. Hence the choice of FPGA
makes the best solution for the objective of the project. In addition, the
implementation of Fuzzy Logic in microcontroller makes the system design easier.
Also, it increases the flexibility of the controller to the change in system’s
parameter.