NMOS Symmetric Load Ring VCOs Modeling for Submicron

Technologies
M. Helena Fino∗
Department of Electrical Engineering, FCT/UNL, Quinta da Torre, 2829-516 Caparica, Portugal

ABSTRACT

Voltage Controlled Oscillators (VCOs) are a key element in PLL design. The simulation of VCOs is a time consuming
process because transient circuit simulations must run long enough that the steady state is attained. Furthermore, the
robustness of design against operating and technological conditions must also be tested by simulating the circuits at
several corners, thus making the design methodology based in iterative simulation rather prohibitive for this class of
circuits. The development of efficient and reliable VCO models is therefore a very important task, not only for the
automation of the circuit design, but for design space exploration as well. Besides accuracy and simplicity, models must
easily adapt to the rapid technology evolution. In order to grant such robustness, we must develop models based on
transistor level technological parameters. This paper presents an accurate model for submicron Voltage Controlled
Oscillators (VCOs). The model obtained is based on the Npower MOS model, yielding quite accurate results for sub
micron technologies. An example considering a 1.2V TSMC013 VCO is presented, where the accuracy of the results
obtained against Hspice simulation is shown. Results obtained in about 2 seconds have 4% average error, compared to
simulations taking over 15 minutes.

Keywords: Submicron VCO model, Ring VCO, Npower MOS model

1. INTRODUCTION

Voltage Controlled Oscillators (VCOs) are a key element in PLL design, since the quality of the signals produced
depends heavily on the VCO performance. In order to obtain VCOs with improved phase-noise, LC-tank oscillators have
been proposed. These oscillators however, show some limitations such as the difficulty in implementing high-quality
inductors in standard CMOS process, and a limited tuning range. Ring oscillators, in spite of showing a poorer phase-
noise performance, are preferred for such applications with very stringent frequency specifications, such as in RF
synthesizers employed in wireless transceivers. Furthermore, ring oscillators normally occupy less chip-area and, if
implemented with an even number of stages, generate both in-phase and quadrature-phase outputs.
During the last fifteen years several ring VCO topologies have been proposed 1-5. Although ring VCOs are widely used,
their design is still quite difficult, since it involves many trade-offs regarding the range of frequency of oscillation
attainable, area, power and noise. In what concerns evaluating the frequency of oscillation the designer may use a circuit
simulator such as Hspice. This approach, however, gives little insight regarding the key parameters for improving the
circuit design. Although some qualitative knowledge may be acquired by running several different simulations, this
design methodology becomes quite time consuming for this class of circuits, since it is based on transient circuit
simulation. Furthermore, the robustness of design against operating and technological conditions must also be tested by
simulating the circuits at several corners, thus making the design methodology based in iterative simulation rather
prohibitive for this class of circuits.
In order to overcome the limitation shown for the simulation based design methodologies, some models have been
proposed for the ring VCOs 3,6-9. These models, however, show some inaccuracy when applied to submicron
technologies, since they rely on the quadratic law for modeling MOS transistors. In 10 an accurate model for PMOIS
symmetric Load VCOs is proposed where the accuracy of results obtained for Submicron technologies is obtained by
using the Npower MOS transistor Model.

∗
hfino@ieee.org
In this paper we propose the adoption of the Npower MOS model 11 as a basis for deriving VCO models. We further
propose the inclusion in the model of information concerning its limits of validity. In some cases a piecewise model,
regarding different operating regions of MOS transistors is considered as a way of yielding the designer qualitative
information regarding the circuit behavior.
Besides this Introduction this paper comprises five additional Sections. In Section 2 a brief description of ring VCOs is
given. Firstly, we introduce the PMOS symmetric load VCO and a brief overview of the models proposed is given. Then,
the NMOS load VCO is presented and the corresponding model is derived. In Section 3, we introduce the Npower
MOSFET transistor model, and then we apply this transistor level model into the previously presented VCO models. In
Section 4 the methodology for the automatic generation of the VCO model is explained. The results obtained with a
working example are presented in Section 5. Finally conclusions are offered in Section 6.

2. RING VCO MODELS

Over the last fifteen years ring voltage controlled oscillators with a differential topology as shown in figure 1 have been
adopted.

Figure 1: Differential buffers ring oscillator basic structure

According to the switching behavior of the delay cells, the VCOs are considered as pertaining to two different types 5. In
the case where the delay cells do not perform full switching operation, they may be modeled as linear amplifiers and the
overall VCO is described as a linear feedback system. For those delay cells where full switching is attained, the
frequency of oscillation is considered as given by eq. (1), where N stands for the number of delay stages, and tdelay is
the delay introduced by each stage.
f osc = 1 ........................................................................... (1)
2.N .tdelay

In this paper we will focus our attention in this second type of VCOs. For the implementation of each differential stage
the symmetric load topology proposed in 3 will be considered.

3.1 PMOS Symmetric Load VCO

In this work we have started by considering the PMOS symmetric load differential delay cell represented in figure 2. The
bias current source, Ibias, is designed as a replica of half the delay cell, granting a maximum output voltage swing equal
to the control voltage. The first model proposed for ring VCOs consisting of N PMOS symmetric load differential delay
cells, considers eq.(2) for the evaluation of tdelay where Ceff, stands for the effective delay cell output capacitance, and Reff
is the effective resistance of the symmetric load represented
t delay = Reff .C eff ............................................................................ (2)

In 12 Reff is considered as the inverse of the transconductance gm of one of the two equally sized load transistors when
biased at the control voltage Vc. By considering the drain current of one of the load transistors given by eq. (3), taking
the derivative with respect to Vc yields eq.(4).

I D = (β load 2)(Vc − Vt ) 2 . ...................................................................... (3)

Reff = gm−1 = (βload (Vc − Vt) )−1 ................................................................. (4)

Combining the previous eq.s (1), (3) and (4) we obtain eq. (5) for the VCO linear model.
 β load (Vc − Vt )
f osc = .......................................................................... (5)
2.N .C eff

Figure 2: PMOS Symmetric load differential buffer basic structure

In 7 a new model is proposed, yielding more accurate results for the case of small values of the control voltage. In this
model the effective resistance of the symmetric load is considered as the ratio between the maximum voltage swing,
VLMax, and ILmax,. Since by design constraints, the maximum output voltage swing equals the control voltage, Reff is given
by eq. (6), leading to the VCO model represented in eq. (7)

2.(β load 2 ).(Vc − Vt ) 2

Reff = . ................................................................... (6)
Vc
β load .(Vc − Vt ) 2
f osc = . ....................................................................... (7)
2.N .C eff .Vc

3.2 NMOS Symmetric Load VCO

A reduction in inter-stage mismatches due to body effect can be obtained if we use NMOs symmetric loads delay cell 13,
as represented in figure 3.In the same figure we also represent the self bias current source used. The control voltage, Vc,
is applied to the self bias source where the symmetrical load control voltage, Vcn, is generated.
In order to obtain the expression for the frequency of oscillation of the NMOS symmetric load VCO, we start by
considering the approach in 7. The maximum current fed to the symmetric load is equal to the bias current, thus given by
eq. (8)

I bias = (β b 2)(Vc − Vt b ) 2 . ...................................................................... (8)

For obtaining the analytical expression for the NMOS symmetrical load control voltage, Vcn, we only need eq. (9), which
leads to eq. (10)
I bias = 2 * I l ................................................................................. (9)

(β b 2)(Vc − Vtb ) 2 = β l (Vcn − Vtl ) 2 . ............................................................ (10)

From eq. (10) we immediately obtain eq.(11) yielding the VCO analytical model in eq.(12).
 βb
v ds max = Vc n = Vt n + (Vc − Vt b ) . ......................................................... (11)
2.β l

a) b)
Figure 3: NMOS Symmetric loads differential buffer: a) basic structure; b) self bias current source

βb
.(Vc − Vt b ) 2
f osc = 2 . ........................................................ (12)
βb
2.N .C eff . Vt l + (Vc − Vt b )
2.β l

However, the above-derived models show the following limitations:

The model was derived considering that transistor Mb of the self bias is saturated
Even for the case where Mb is saturated the expressions used for obtaining the drain current do not account for its
dependency on transistor vds
The model considers the quadratic (Shockley) model for MOS transistors, which is not accurate when sub micron
technologies are to be used.
In Section 3 a more accurate model for sub micron transistors will be briefly described and, then, the adoption of the
MOS model into the VCO model is presented. There, the validity of the model according to operating region of the
transistors is also accounted for.

3. ANALYTICAL MODEL FOR SUBMICRON VCOS

The previously proposed models rely on the quadratic Id (vgs) law of the transistors. As stated in 11, Shockley’s model is
not accurate for sub micron technologies, since it does not account for saturation effects of carriers. Sakurai & Newton
proposed the Npower model where the MOS transistor behavior can be described by equations (13) trough (18)
VTh = VT 0 + γ ( 2.φF − VBS − )
2.φ F . ............................................................ (13)

VD SAT = K .(VGS − VTh )m . .................................................................... (14)

 W
I D SAT = .B.(VGS − VTh )n . ................................................................. (15)
Leff

λ = λ0 − λ1.VBS ............................................................................. (16)

I D = I D SAT .(1 + λVDS .). ⇐ VDS > VDSAT ............................................................. (17)

VDS V . .................................................... (18)

I D = I D SAT . 2 − . . DS ⇐ VDS < VDSAT
VDSAT VDSAT

Since for the VCO model we are only using the ID(VGS) characteristic of transistors comprising the symmetric loads,
where VBS=0, we consider a simplified model, where eq. (13) is replaced by eq. (19) and eq.(17) is replaced by eq.(20)

VTh = VT 0 . ........................................................................ (19)

I D = I D SAT .(1 + λ0 .VDS ) ⇐ VDS ≥ VDSAT ................................................... (20)

3.1 NMOS Load Submicron VCO Model

By considering the Npower MOSFET model, the expression relating the maximum output voltage swing Vdsmax to the
control voltage Vc will be given by eq.(21).
Wb
Bb .
Leffb
Vds max = Vcn = Vtl + nl (Vc − Vtb ) nb ................................................. (21)
W
2.Bl . l
Leffl

Then, the new VCO model will be described by eq.(22)

Wb
Bb . .(Vc − Vt b ) nb
Leffb
f osc = . ..................................................... (22)
W
Bb . b
Leffb
2.N .C eff . nl (Vc − Vt b ) nb
W
2.Bl . l
Leffl

Although this model is derived considering the Npower MOS model, thus yielding accurate results for sub micron
technologies, it still suffers from the two first limitations pointed out in Section 2. In order to overcome these limitations,
an optimization-based procedure was considered which will described in the next Section.

4. AUTOMATIC GENERATION OF THE VCO MODEL

As we may easily conclude, the models obtained were derived assuming that the bias transistor, Mb, as well as the load
transistors, Ml, of the biasing current source are operating in the saturation region. For certain transistor sizes, however,
we may come to some situations where the transistors may no longer remain saturated. Therefore, we have considered
applying an non-linear equation solver approach for the solution of the autobias current source operating point. Figure 5
shows the pseudo code for the solution.
The determination of the self bias current source operating point, is accomplished by solving the multivariable equations
represented by eqs (23) to (24), where Is, Ib and Il stand for the switch, bias and load Mosfet drain currents, respectively.
I b = I s . ......................................................................... (23)
 I s = 2 * I l ............................................................................... (24)
For the evaluation of the above mentioned currents, the Npower model equations (13)-(18) were fed into the solver, as
well as the circuit eqs.(25) – (29)
vgsb = vc . ......................................................................... (25)

vdsb = v dd − v x . ........................................................................... (26)

vgs s = v x ................................................................................. (27)

vds s = v x − v cn ............................................................................. (28)

vgsl = vdsl = v cn . .......................................................................... (29)

def autobias(x): # solution for autobias cell

# x[0] contains Vcn; x[1] contains Vx;
vdsb=Vdd-x[1] # vds of bias mosfet
vdss=x[1]-x[0] # vds of switch mosfet
vdsl=x[0] # vds of load mosfet
Is=getI(betaMs, paramMs,x[1],vdss) # drain
current of switch mosfet
Ib=getI(betaMb,paramMb,Vcp,vdsb) # drain current
of bias mosfet
IL=2*getI(betaMl,paramMl,x[0],x[0]) # drain
current of load mosfets
out=[Ib-Is]
out.append(IL-Is)
return out

def getI(Bx,Px,vgs,vds): # returns Id

if vgs<Px.Vth:
I=0
else:
I=Bx*(1+Px.la*vds)*((vgs-Px.Vth)**Px.n)
vdsat=Px.K*((vgs-Px.Vth)**Px.m)
delta=vds/vdsat
if delta<1.0:
I=I*(2-delta)*delta
return I
Figure 4: Pseudo code for the procedure defining the set of equations used for solving the operating point of the self bias current
source represented in figure 3.b.

For each value of the input voltage, Vc, we obtain the corresponding voltages, Vcn and Vx, represented in figure 3b.
Given the DC voltages Vcn and Vx, the corresponding bias current is obtained by considering eq. (30)-(31) and applying
the Npower MOS model
 V D SAT = K .(Vc − VTh )m . ..................................................................... (30)

V D S = Vdd − V x ............................................................................ (31)

Once the solver returns the bias current, Ibias, the frequency of the VCO is then calculated applying eq.(32)
I bias
f osc = ......................................................................... (32)
2.N .C eff .Vcn

For the fully automatic VCO model generation we need the MOS parameters, for the technology used. The need for
obtaining the Npower model parameters for each technology, associated to the rapid evolution of technologies, lead us to
develop a simple Python Script for the automatic evaluation of the above mentioned parameters. Given a technology file,
tables for NMOS and PMOS transistors model parameters were generated, using the methodology proposed in 11. For
each of them, tables for typical case and for corners were obtained. For each table transistors with sizes (L and W)
ranging from the minimum value for the given technology up to W=L=100µ are considered.
For the automatic evaluation of a VCO model with given transistor sizes, the corresponding MOS parameters are
obtained by applying a bilinear interpolation of entries existent in given Technology table, thus granting a better
accuracy of the model obtained.

5. WORKING EXAMPLE
As a working example we have considered a three-stage NMOs symmetrical load differential VCO. The VCO is
implemented in the 1.2V TSMC013 technology. Each stage considered is illustrated in Figure 3, with the transistor sizes
shown in Table 1.
Switch (Pmos) Load (Nmos) Bias (Pmos)
W 10µ 5µ 69.5µ
L .13µ .38µ 1.3µ
M 1 1 10
Tab. 1: Transistor Sizes for the working example
The corresponding Npower model parameters obtained with our Python Script are represented in Table 2.

Switch (Pmos) Load (Nmos) Bias (Pmos)

n 1.399 1.359 1.716

Wb 0.002508 0.001584 0.018926

Bb .
Leffb

Vt 0.408 0.416 0.309

m 0.551 0.585 0.863
K 0.701 0.684 0.838
λ0 0.258 0.060 0.040
Tab. 2: Npower model parameters for the transistors with sizes in Tab.1

For the given MOSFET parameters in table 2 we represent, in figure 5 the Id (vds,vgs) characteristics for the load
transistors, generated with the Npower model, against those obtained with Hspice.
In figure 5 we represent the generated Vcn values for each control voltage Vc given. Also in the same figure we may
observe the values of Vcn obtained with eq.(21), i.e., considering that the bias transistor ,Mb, is in saturation for all range
of the control voltage, Vc. We may easily conclude that for control voltages bigger then .47V, transistor Mb is no longer
saturated. We may, therefore conclude that the VCO model represented in eq.(22) is valid only for control voltages
between .35V and .47V

1.2E-03
1.0E-03
8.0E-04
6.0E-04
Id

4.0E-04
2.0E-04
1.0E-19
0.0 0.2 0.4 0.6 0.8 1.0 1.2
vds

Figure 5: Drain current characteristics obtained with Npower model (-) against Hspice simulated values (*), for .5V ≤ vgs ≤ 1.2V

0.9

0.8
Vcn

0.7

0.6

0.5

0.4
3.50E-01 4.00E-01 4.50E-01 5.00E-01
Vc

simulated Vcn from eq.(21)

from solver

Figure 6: Values of VCO output swing for control voltages between .35V and .55V

The results obtained with the VCO model generated with the solver-based methodology are shown in figure 6. Although
control voltages between .35V and .55V are considered we should have in mind, as illustrated in figure 5, that the
corresponding control voltage applied to the symmetric load, Vcn, is actually ranging between .44V and .85V. The
comparison with results obtained from simulation with Hspice; also represented in figure 6, show the accuracy of the
results obtained with the proposed methodology. In the same figure we also represent, in dashed line, the VCO frequency
response obtained by applying the model in eq. 22. As we may conclude the model is accurate only for such control
voltages granting the saturation of the biasing Mosfet transistor.
 1.2E+09

1.0E+09

8.2E+08

Frequency
6.2E+08

4.2E+08

2.2E+08

2.0E+07
3.50E-01 4.00E-01 4.50E-01 5.00E-01 Vc

simulated from opt. from eq.(22)

Figure 6: Values of VCO frequency for control voltages between .35V and .55V

6. CONCLUSIONS

In this paper we proposed a new methodology for the automatic generation of sub micron ring VCO models. The VCO
models are derived considering the Npower MOS model, thus providing the accuracy of the results obtained for sub
micron technologies. As previously proposed models were obtained considering certain transistor operating regions, i.e.,
with biasing MOSFETs in saturation, the accuracy of results obtained is limited to the range of control voltages yielding
such working conditions. By adopting an optimization-based methodology based on the resolution of the biasing circuit
equations, the results obtained are valid for a wider range of control voltages. This latter situation is particularly
important in such cases where the models are used inside an optimization loop for designing VCOs meeting a given set
of specifications.

Acknowledgments

The author would like to thank Chipidea - Microelectronica, S.A., for providing exceptional working conditions as
well as for granting the access to all the technology characterizations files, which made this work possible. Special
acknowledgment is due to Dr A. B. Leal, for the helpful suggestions in the development of the current work.
Further acknowledgement is due to Fundação Calouste de Gulbenkian, for the Grant supporting the presentation of
the present work.

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