DIGITAL CONTROLLER IMPLEMENTATION USING FIELD PROGRAMMABLE GATE ARRAY

P.Vanchi1, P.Vanaja Ranjan2

1,2

Department of electrical and electronics engineering, College of Engineering Guindy, Anna University, Chennai-25, India.
1

vanchiece@gmail.com

Abstract A fully digital and high-efficiency power supply system controller has been developed based on a finite-state machine (FSM) control scheme. The system monitors circuit performance with a delay line and provides a substantially constant minimum supply voltage for digital processors to properly operate at a given frequency. In addition, the system adjusts the supply voltage to the required minimum under different process, voltage, temperature and load conditions. This digital FSM scheme significantly reduces the complexity of control-loop implementation and power consumption compared to other approaches based on proportionalintegraldifferential control. The power delivery control system is implemented in field programmable gate array to minimize the cost of area required.

both clock frequency and supply voltage depending on the computational work load, the power consumption required for the given task can be dynamically and adaptively optimized. Techniques for minimizing power consumption using AVS have been proposed for digital applications at a fixed throughput, and demonstrated on silicon for microprocessor application. Their performance is improved for variable-rate digital signal processing throughput and. Most previous works used analog- or mixed-mode circuit techniques for these implementations, which caused yield and tuning problems due to process, voltage, and temperature (PVT) variations. The contribution of this paper is to extend these efforts by considering yield issues and the compensation of fabrication process parameter no uniformity in a single die, reference voltage fluctuation, and temperature variation. 2. Adaptive Voltage Scaling. A block diagram of the all digital self-adjusting minimum power supply system is presented in Fig.2.1. The system dynamically monitors circuit performance with a delay line and provides a substantially constant minimum supply voltage for digital processors to properly operate at a given frequency and the system adjusts the supply voltage to the required minimum under different process, voltage and temperature and load conditions. Adaptive voltage scaling can decrease power consumption without sacrificing performance provided the tasks performed are finished within the allowed time. If AVS is employed to dynamically adjust both clock frequency and supply voltage depending on the computational work load, the power consumption required for the given task can be dynamically and adaptively optimized. The system consists of a closed-loop controller, a fixed frequency clock signal (Clk), frequency information (FI), a dc-dc buck-converter, and a processor as a load current source. The loop controller consists of a slacktime detector, a voltage adjuster, and a PWM modulator. The controller performs the discrete-time compensation:

Keywords:

controller implementation, Adaptive voltage scaling, Finite state machine and Field programmable gate array. Digital

1. Introduction
The strong demand for low-power computing has been driven by a growing variety of portable and batteryoperated electronic devices. These span a broad range of performance and functions with respect to throughput. Power consumption is a limiting factor in VLSI integration for portable applications. The resulting heat dissipation also limits the feasible packaging and performance of the VLSI chip. Since the dynamic power dissipation in synchronous digital integrated circuits is determined by, reducing the supply voltage is an effective way to reduce power consumption. However, the gate delay of a digital gate is inversely proportional to the supply voltage. Therefore, the application operates at a reduced clock frequency with a lower supply voltage at the cost of performance reduction to meet the low power requirement. This is not a desirable solution to keep pace with the current demand for improved performance. Adaptive voltage scaling (AVS) can decrease power consumption without sacrificing performance provided the tasks performed are finished within the allowed time. If AVS is employed to dynamically adjust

D (n+1) =F (n) + E (n) +A (n)

(2.1)

Where D (n+1) is the next value of the duty ratio, F (n) is the frequency compensator E (n) is the current values of the detected error A (n) is the accumulated compensation is error scaling factor As in (2.1), the control approach does not request any previous values, while an accumulated compensation factor is needed. The variations of PVT and load are dynamically updated in the compensation factor. During updating, the duty ratio is controlled by a finite-state machine (FSM) which maintains a substantially constant supply voltage. The scaling coefficient is used to increase the error resolution and it is implemented by the shift-right function instead of multiplication. 2.1 Slacktime Detector Slacktime detection is the ability to determine the minimum voltage required for a given operating frequency. It requires continuous monitoring of a critical path delay through the digital circuitry with respect to PVT, load and frequency. The proposed slacktime detector consists of a chain of delay cells and a tap register as shown in Fig.2.2. The principle of a delayline as an ADC is based on the relation between supply voltage and propagation delay. The slacktime detector determines the voltage level of the delay lines supply based on the propagation delay through the delay line. In other words, the delay along with the supply voltage is converted to a digital value by sampling the delayline. Fig.2.2 Circuit schematic of slacktime detector 2.2 Voltage Adjuster The voltage adjuster consists of an error compensator, a frequency compensator, a process, voltage, and temperature compensator, and a control block as shown in Fig.2.3. The major role of the voltage adjuster is to compensate a supply voltage error at a given frequency from the measurement of the slacktime detector and to provide a desirable constant voltage level against variations of frequency as well as PVT. In addition, for high-speed and low- overshoot/undershoot start-up, it controls soft-start operation. 2.2.1 Error Compensator The role of the error compensator is to detect the voltage error, E(n) as in (2.1), and to generate a proportionally compensated value. It receives the propagation delay word TX (27:12) from the slacktime detector and detects the position of one and zero pair of taps as shown in Fig. 2.4. The compensator converts the propagation delay position to an error voltage by comparing it to the reference delay position along with supply voltage under worst case conditions. In turn, it generates a proportionally compensated propagation delay word ECW (5:0) that represents a reference value at a default frequency plus a compensated error value.

Fig.2.1 Block diagram of all digital self-adjusting minimum power supply system.

Fig.2.3 Block diagram of voltage adjuster against variations of frequency and PVT.

2.2.3 Process, voltage, and temperature compensator It consists of an internal dynamic voltage reference source, a pulse width generator, and a ringing. The internal dynamic voltage reference source adds or subtracts one, two, or three steps according to the increment/decrement indicators U1, U2, U3, D1, D2, D3, and generates an internal dynamic voltage reference, IREF(7-0). 2.2.4 Control Block of Voltage Adjuster Fig.2.4 One-zero edge detector and an example of encoding procedure. 2.2.2 Frequency Compensator The frequency compensator adjusts the duty cycle of the PWM pulse based on the desired supply voltage at a given frequency. The first subtractor, SUB1, in Fig.2.5 generates a difference between the frequency information, FI(5:0), and the internal reference voltage level, RFI(5:0). The difference implies the desirable voltage variation in response to a given frequency. The up/down counter (CNT) receives the difference and counts up or down at the load signal (LOAD) until the output of the counter is equal to the difference. This prevents the supply level and frequency variation from abruptly changing and reduces ringing. The second subtractor, SUB2, receives the proportionally compensated propagation delay word ECW(5-0) from the error compensator and the shift-left counter number for the subtrahend, and generates a frequency compensated propagation delay word FCW1(5-0). The compensated error-step from the delayline is the same as the resolution of the delayline (6 bits). The control block consists of a clock generator, a tap selector, an FSM, a control signal generator, and a false low-level detector. The clock generator outputs a 1/4 frequency input clock signal, ICLK, and a 1/4 period lagged SCLK from an external clock input, CLK, a 1/32 frequency PWM LOAD and a delayline RSTN from the SCLK, and a frequency doubled clock (DCLK) from the external Input clock, CLK, as shown in Fig. 2.6. The tap selector chooses one of 4-taps prior-tap INCSET, centertap CNTTAP, next-tap DECSET, and next next-tap DECSET2 from 16-taps TX12TX27 of a slacktime detector in response to external frequency information FI(5:0). The control signal generator outputs increment or decrement indicators UP, UP3, DOWN, and DOWN3 in response to the status of the tap detector, the state CS2CS0 from a finite-state machine, and external frequency information.

Fig. 2.6 Block diagram of clock generator

Fig. 2.5 Block diagram of frequency compensator

Fig. 2.7 State diagram of the FSM The FSM in Fig.2.7 receives monitor signals from the other control modules and data path block, and it outputs control signals to the data path block. The monitor signals consist of the first tap TX12, the last tap TX27, the 4-taps INCSET, CNTTAP, DECSET, and DECSET2, two frequency-change indicators INC and DEC, and the external FI. The control signals consist of a current state CS (2-0), a low-voltage state signal LOW, a high-voltage state signal HIGH, and a clear signal CLR of a PWM pulse width counter. The states from 000 to 011 controls a soft-start routine to avoid large overshoot/undershoot with high-speed saturation. In the states from 100 to 111, the FSM controls the duty cycle of the DPWM according to the current-voltage status detected by the 4-taps varying over PVT conditions. The outputs of the FSM are used to change the counter number of the PVT compensator at weighed steps and to double or halve the counter number. This accelerates the supply voltage to the appropriate value for various PVT quickly and stably in start-up as well as normal operation. The DACs higher resolution than ADC gives multiple DAC values for a given ADC output. During a high-to-low voltage transition with frequency change, the highest DAC voltage level equal to the ADC level may be a settling point. The false low level detector steps down the voltage level until a true minimum DAC level at a given frequency is detected. The supply voltage settles at the first high DAC level in an ADC bin by the FSM and, in turn, converges to the bottom DAC level by the false low-level detector. 3. Implementation And Result Combining Advanced Silicon Modular Block (ASMBL) architecture with a wide variety of flexible features, the Virtex-4 Family from Xilinx greatly enhances programmable logic design capabilities, making it a powerful alternative to ASIC technology. Virtex-4 FPGAs comprise three platform familiesLX, FX, and SXoffering multiple feature choices and combinations to address all complex applications. The wide array of Virtex-4 hard-IP core blocks includes the PowerPC processors (with a new APU interface), tri-mode Ethernet MACs, 622 Mb/s to 6.5 Gb/s serial transceivers, dedicated DSP slices, high speed clock management circuitry, and source-synchronous interface blocks. The basic Virtex-4 building blocks are enhancements of those found in the popular Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X product families, so previous-generation designs are upward compatible. Virtex-4 devices are produced on a state-of-the-art 90-nm copper process using 300-mm (12-inch) wafer technology. The resource utilization of Virtex 4 FPGA is shown in fig 3.1.

2.3 DPWM Pulse Modulator The DPWM pulse modulator in Fig. 2.8 consists of a loadable down counter and a pulse generator. Counter loads the PWM pulse width PW (7-0) from the voltage adjuster by the LOAD, changing a binary output of counter as a count in response to the DCLK. DPWM pulse modulator outputs a pulse modulated signal PWM defined by the binary input value PW(7-0) of counter.

Fig 3.1 Virtex-4 FPGA Resource Utilization 3.1 Virtex 4 FPGA Families Three Families LX/SX/FX 1. Virtex-4 LX: High-performance logic applications solution. 2. Virtex-4 SX: High-performance solution for digital signal processing (DSP) applications. 3. Virtex-4 FX: High-performance, full-featured solution for embedded platform applications. Virtex-4 LX Platform FPGAs are optimized for general logic applications and offer the highest logic density and most cost-effective high-performance logic and I/Os. Members of this family provide abundant logic cells together with embedded Block RAM, digital clock

Fig.2.8 Block diagram of PWM modulator

management (DCM) blocks, and XtremeDSP/arithmetic functions to handle high-density, I/O intensive, and highperformance logic applications across multiple markets. Virtex-4 SX Platform FPGAs are optimized for very high-performance signal processing applications such as wireless communication, video, multimedia and advanced audio that may require a higher ratio of XtremeDSP slices to logic than other members of the Virtex-4 family. Members of this family offer all the capabilities of the LX platform and are designed for very high-performance real-time signal processing. The exceptionally high ratio of XtremeDSP-slices-to-logic and embedded Block RAM-to-logic ratios allow the Virtex-4 SX programmable devices to offer breakthrough DSP performance at significantly reduced power consumption compared to alternative FPGA solutions. These higher levels of performance make the SX devices the ideal complement to programmable DSP processors accelerators. Virtex-4 FX Platform FPGAs are assembled with capabilities tuned for complex system applications including high-speed serial connectivity and embedded processing, especially in networking, storage, telecommunications and embedded applications. Members of this family offer the industry's first multi-gigabit serial transceivers supporting any speed between 600 Mbps and 11.1 Gbps, enhanced embedded PowerPC 405 processors with an auxiliary processor unit for hardware acceleration, in addition to abundant logic cells, block RAM, DCM clock managers and DSP/arithmetic functions.Virtex-4 FX programmable devices provides the most advanced Platform FPGA available for system design.

automatically in a pleasant GUI so that the user can create FPGA designs in seconds. 3.3 Simulation Results

Fig 3.3 Synthesis and Simulation of the PWM program using ISE 9.1i-1 The behavioral simulation of the PWM signal using Xilinx 9.1i ISE, the inputs given to the counter and data in as shown in figure 3.3

Fig 3.4 Synthesis and Simulation of the PWM program using ISE 9.1i-2 4. Conclusion and Future Work Adaptive voltage scaling (AVS) can decrease power consumption without sacrificing performance provided the tasks performed are finished within the allowed time. The AVS is employed to dynamically adjust both clock frequency and supply voltage depending on the computational workload, the power consumption required for the given task can be dynamically and adaptively optimized. The implementation of the fully digital selfadjusting minimum-power supply system to regulate the supply voltage as the minimum required operating value at given PVT and frequency is presented along with the detail algorithm to compensate the PVT variations. The power delivery control system is implemented in field programmable gate array, to minimize the cost of area required and improve the overall efficiency as well. The future work can be done to implement of Buck Converter IC for cellular phone application.

Fig 3.2 Virtex 4 FPGA Kit 3.2 Xilinx ISE 9.1i Xilinx ISE is a popular FPGA development tool used widely in industry and in educational institutions. This tool allows for complete FPGA development. ISE can read in VHDL/Verilog/Schematic modules created for a project design and synthesize them into logic elements to be placed on an FPGA. ISE can automatically interpret your HDL syntax, synthesize your description, place and route the logic elements and then provide a software BIT file description to connect these logic elements together to create the circuit described in the HDL. All these tool flow steps require their own respective application program to perform the function. ISE calls these programs

Acknowledgement I would like to express my sincere appreciation and gratitude to Mrs. P.Vanaja Ranjan, Ph.D., Assistant Professor, Department of Electrical Engineering, College of Engineering, Guindy, Anna University, Chennai for her constant encouragement and support. References [1] Benjamin J. Patella, Aleksandar Prodic, and Dragan Maksimovic, (2003). High-Frequency Digital PWM Controller IC for DCDC Converters, IEEE transactions on power electronics, vol. 18, no. 1, [2] Dae Woon Kang, Member, IEEE, Yong-Bin Kim, Senior Member, IEEE, and James T. Doyle, Senior Member, IEEE ( 2006) "A High-Efficiency Fully Digital Synchronous Buck Converter Power Delivery System Based on a Finite-State Machine" IEEE Transactions on very large scale integration (vlsi) systems, vol. 14, no. 3. [3] Tadahiro Kuroda, Kojiro Suzuki, Shinji Mita, Tetsuya Fujita, Fumiyuki Yamane, Fumihiko Sano, Akihiko Chiba, Yoshinori Watanabe, Koji Matsuda, Takeo Maeda,Takayasu Sakurai, Member, and Tohru Furuyama, (1998)"Variable Supply-Voltage Scheme for Low-Power High-Speed CMOS Digital Design IEEE journal of solidstate circuits, vol. 33, no. [4] Gu-Yeon Wei and Mark Horowitz (1999)"A Fully Digital, Energy-Efficient, Adaptive Power-Supply Regulator " IEEE journal of solid-state circuits, vol. 34, no. 4, [5] Jaeha Kim, Student Member, IEEE, and Mark A. Horowitz, Fellow, IEEE, (2002) "An Efficient Digital Sliding Controller for Adaptive Power-Supply Regulation" IEEE journal of solid-state circuits, vol. 37, no. 5, [6] Vincent von kaenel, Peter macken, and Marc g. r. Degrwwe, member IEEE, (1990). "A Voltage Reduction Technique for Battery-Operated Systems" IEEE journal of solid-state circuits, vol. 25, no. 5. [7] Lars S. Nielsen, Cees Niessen, Jens Sparso, and Kees van Berkel (1994). "Low-Power Operation Using SelfTimed Circuits and Adaptive Scaling of the Supply Voltage IEEE transactions on very large scale integration (vlsi) systems, vol. 2, no. 4. [8] Anantha Chandrakasan, Vadim Gutnik, Data Driven Signal Processing: An Approach for Energy Efficient Computing".

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