The enhancement MOSFET Figure 3.34 shows the basic structure and symbol for enhancement-type MOSFET.

The channel between the source and drain terminals is interrupted by a section of substrate material. A gate voltage is required on this device for current to flow from the source to drain terminal. Figure 3.35 shows a biased n-channel enhancement MOSFET. Both d.c. voltages, VGS and FDS, must be forward biased in order to enhance the flow of current from the source to the drain terminal. When VGS = 0, no current flows from the source to the drain terminal and no enhancement region occurs. The greater VGS, the more positive the gate terminal becomes, causing holes to move away from the gate area and/or electrons to move into the gate area. Consequently, an inversion layer is formed that completes a conductive channel between the source and the drain. The more positive the gate becomes, the wider the inversion layer becomes, which enhances the flow of current from the source to the drain terminal. Figure 3.36 shows the drain characteristic curves for an n-channel enhancement-type MOSFET. The MOSFET transistor has four major regions (modes) of operation (Table 3.3): cutoff, ohmic (or triode), saturation and breakdown. In the nonsaturated (or triode) region, the voltage drop across the drain-source terminals approaches zero volts as the magnitude of the voltage drop across the gate-source terminals approaches FDD KSs- For example, in a 5 V system, the drain-source

Voltage approaches OY as the magnitude of the gate-source voltage drop approaches 5 V. In the cutoff region, the drain-to-source current, 7DS, approaches OA (i.e. the drain-source resistance approaches infinity: an open circuit). Hence, the drain and source terminals of a MOSFET transistor can be treated as an almost ideal switch alternating between the off (cutoff) and on (non-saturated) modes of operation. In this case, we use the symbol VT to represent the threshold voltage. The same equations are valid for pchannel devices if the subscript SG is substituted for GS and SD is substituted for DS.

EXAMPLE 3.3 Determine the resistance Rs in the circuit shown in Figure 3.37, where R1 = 3 M ohm; R2 = 2M ohm; RD = 10k ohm; VT = 4V; IDSS = 6Ma

V DD=40V;

VDS = 8V;

Solution The voltage supply, FDD, appears across the potential divider comprising Rx and R2. Consequently, the base terminal of the transistor will see the Thevenin equivalent circuit composed of the Thevenin equivalent voltage (self-biasing):

and the Thevenin equivalent resistance:

The gate circuit equation is:

and since the MOSFET input resistance is infinite, J'G = 0, so

The drain circuit equation is:

From Equation 3.3A,

Substituting Equations 3.36 and 3.37 into Equation 3.35:

Hence,

From Equation 3.35:

The depletion MOSFET Figure 3.38 shows the basic structure and symbol for a depletion-type MOSFET. The channel between the source and drain terminals is a straight-through piece of semiconductor material. In an n-channel depletion-type MOSFET, the electrons in the n-type material carry the charges, but in a p-channel depletion-type MOSFET, the charges are carried by holes through the p-n type material. The gate is separated from the channel by a very thin layer of silicon oxide, which is a very good insulating material. Consequently, no current flows between the gate terminal and the channel. However, as in JFET, applying a voltage to the gate of the MOSFET controls the amount of current that flows through the channel. Figure 3.39 shows the n-type depletion MOSFET mode of operation. The normal operating conditions are as follows: the source-drain connection must be forward biased since the charge carriers flow from source to drain. the gate-source connection must be reverse biased to give the depletion mode operation. When the bias voltage, vGS, is zero, the maximum current ID flows from the source to the drain. When the bias voltage, VGS, is increased, the depletion region increased resulting in a smaller /D flowing from the source.

A very large bias voltage, vGs can cause no current to flow from the source to the drain. Figure 3.40 shows the drain characteristic curves for an n-channel depletion-type MOSFET.

Again there are four regions of operation with the equations shown in Table 3.4. Here VP represents the depletion type MOSFET threshold voltage. The same equations are valid for p-channel devices if the subscript SG is substituted for GS and SD is substituted for DS. Rules for connections in MOSFETs Rule 1: The bulk (or substrate) connections for MOSFETs are normally connected to a power supply rail, p-channel bulk connections are typically tied to the FDD rail and n-channel bulk connections are typically tied to the FSs rail.

Rule 2: For proper operation as an ideal switch (see later), the p-channel MOSFET must be connected to the most positive voltage rail while the n-channel MOSFET must be connected to the most negative voltage rail. Figure 3.41(a) shows the substrate connected to the power supply. Figure 3.41(b) shows the symbols for when the source-bulk connection has been shorted to ground. These symbols are most commonly used in documenting analog CMOS circuits. Figure 3.41(c) shows the schematic symbols for MOSFETs, and substrate connection is not indicated.

Notice too that the gates for the p- and n-channel devices differ. The p-channel device is identified by a 'bubble' on the gate input. The presence or absence of a 'bubble' on the gate input is used to signify what logic level is used to turn on the transistor. The presence of a 'bubble' on the p-channel device indicates that this device should have a logic low applied to the gate input to turn on the transistor while the absence of a 'bubble' on the n-channel device indicates that this device should have a logic high applied to the input to turn on the device. These schematic symbols are most commonly used when documenting CMOS logic circuits. The bulk-substrate connections are almost always connected to the power supply rails using MOSFET Rule 1.