1940

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 11, NOVEMBER 1995

Analytical Models for n +-p + Double-Gate SO1 MOSFET' s

Kunihiro Suzuki, Member, IEEE, and Toshihiro Sugii

Absfrur- Previously, we proposed n+-p+ double-gate SO1 MOSFET's, which have n+ polysilicon for the back gate and

p+ polysilicon for the front gate to adjust a threshold voltage, and demonstrated high speed operation. In t i parer, we eshs tablish analytical models for this device. This transistor has two threshold voltages related to n+ and p+ polysilicon gates: V t h l and Vth2, respectively. V t h l is a function of the gate oxide thickness tox and SO1 thickness tsi and i about 0.25 V when s tox/tsi = 5, while Vth2 is insensitive to tox and tsi and i s about 1 V. We also derive models for conduction charge and drain current and verified their validity by numerical analysis. Furthermore, we establish a scaling theory unique to the device, and show how to design the device parameters with decreasing a gate length. We show numerically that we can design sub 0.1 pm gate length devices with an appropriate threshold voltage and an ideal subthreshold swing. We also show that our theory agrees well with experimental data.

n'

I
Polyslllcon

NA

I I
SI0
2

n*

IPS

n S I

- Metel

I.

INTRODUCTION

VG

OUBLE-GATE SO1 MOSFET's (Fig. l(a)) are expected to be free from the bulk MOSFET's scaling limit [ 11-[5]. Superb short-channel effect immunity, high transconductance, and ideal subthreshold factor have been reported by many theoretical and experimental studies on this device [61-[201. The threshold voltage Vth of the double-gate SO1 MOSFET's is dominantly determined by the work function of the gate material, and is insensitive to gate oxide thickness tox and SO1 thickness ts; [17]. Its value is 1 V if we use p+ polysilicon and -0.1 V if we use n+ polysilicon, both are inadequate to realize high-speed and low-power operation in deep submicrometer gate length regimes. We must therefore investigate gate material to obtain a proper &. We proposed a n+-p+ double-gate SO1 MOSFET's as shown in Fig. l(b) in which &h is controlled through the interaction between the both gates. In this paper, we discuss the theory of our device: &h, conduction charge, drain current, and scaling theory.
11. THRESHOLD VOLTAGE

n
S I

o
Polyslllcon

= SI02

Metal

Fig. 1. Double-gate nMOSFET: (a) p+-p+ double-gate. (b) n+-p+ double-gate.

In both p+-p+ and n+-p+ double-gate SO1 MOSFET's (Fig. l), the both gate oxide thicknesses tox are the same,
Manuscript received October 12, 1994; revised May 24, 1995. The review of this paper was arranged by Associate Editor D. A. Antoniodis. The authors are with Fujitsu Laboratories Ltd., Atsugi 243-01, Japan. IEEE Log Number 9414579.

and the same gate voltage Vc is applied to both gates. The channel doping concentration N A is constant, independent of gate length L G and is as low as 1015 ~ m - V t h of p+-p+ ~ . double-gate SO1 MOSFET's is given by [17]

oQ18-9383/95$04.00 0 1995 IEEE

SUZUKI AND SUGII: ANALYTICAL MODELS FOR "+-pi

DOUBLE-GATE SO1 MOSFETS

1941

m
Q

1.0 0.5

=
0

>
0
v)

1
0

vFBp+

0.5
Numerical

z 1
0 .c

0.0

Midgap gate

E
Q)

5 -0.5
L,
W 1 pm I,,,

= 10 pA
0.05 V

I -

= 10 pm V,

e c
0

-1.0 -1.5

z
100

Q)

-1 .o

50 SO1 thickness (nm)

-20

I . . . . IWlm . . 1 0 20 40 60 Distance (nm)

I I I

where

Br=-1n(?) 1

P
= - In 1

(r)
Np+poly

Fig. 4. Schematic potential distribution of n+-p+ double-gate SO1 MOS-

is the Boltzmann constant, T is the absolute temperature, FET's when the channel is induced on the inside surface of the n+ polysilicon gate: The dashed line corresponds to and a solid n is the intrinsic carrier concentration, V F B p + is the flat band line to a n+-p+ double-gate device. a p+-p+ double-gate deviceenlarged by i The gate oxide thickness is voltage associated with the p+ polysilicon gate, N p + p o l y is the 7 which is the ratio of the permittivity constant of Si to that of Si02 and its doping concentration of the p+ polysilicon, and cox and Si value is 3. This enables us to draw the potential distribution over the entire gate oxide and channel regions as a straight line. are the permittivity constants of Si02 and Si, respectively. The analytical model agrees with the numerical data calculated using a two-dimensional device simulator FLAPS [21] the inside surface of the n+ polysilicon gate. The potential (Fig. 2). &h of the numerical data is defined as the gate voltage distribution then changes linearly fixing the surface potential. at which the drain current I D is 10 PA. The inversion layer is formed on the inside surface of the The third and fourth terms of (1) depend on device param- p+ polysilicon, and after that the potential distribution in eters tox and t s i , but they contribute less to the magnitude the channel region is invariable, and the applied voltage of V t h . Therefore Vth of p+-p+ double-gate SO1 MOSFET's, is sustained by both gate oxides. Therefore, this transistor &h (p+-p+), is insensitive to tox and t s ; and is about 1 v. has two different threshold voltages related to each gate If we use n+ polysilicon, &h is below 0 V. Both values are material. inadequate for deep submicron devices to ensure high drain Based on the above numerical study, we geometrically current and suppressed stand-by current. Therefore, a new gate derived a Gh model of this device as shown in Fig. 4 which material such as TiN [22] must be developed to make such describes the potential distribution when the channel is induced devices practical. on the inside surface of the n+ polysilicon gate. To simplify We proposed n+-p+ double-gate SO1 MOSFET's the analysis, the gate oxide thickness is enlarged by y, which (Fig. l(b)) with the idea of controlling Vth through the is the ratio of the permittivity constant of Si to that of Si02 and interaction between the both gates [23], [24]. its value is 3. This enables us to draw the potential distribution To derive the V&, model for this device, we first studied over the entire gate oxides and channel region as a straight line. potential distribution dependence on the gate voltage using For p+-p+ double-gate SO1 MOSFET's, the potential FLAPS (Fig. 3). is constant in the entire channel region, and the transistor The potential distribution in the channel region is almost a switches on when the potential reaches [17] straight line in the subthreshold region (VG < 0.25 V), and is shifted parallel to VG.The inversion layer is formed on (3) B s t h = &h(P+-P+) - v F B p + .
Icg

1942

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 11, NOVEMBER 1995

1.5n
l

.
!

p+-p' gate

1.0)
Q)

= 0 >
x
U)

u l

0.5 ;

:
E

0.0

1
\
.

n* n+ gate

>
"thZ

n+-p' gate

'
-

. . -Analytical
.
0

where the original point is set at the p+ polysiliconlgate oxide interface. Since the carrier concentration is expressed as

Numerical

(7)

The induced charge per unit area is

Q1 =
11

'thl

-0.5

ql: rx+tsi

n(y) d Y

L, = 1 pm I,,

10pA

:
.

W = 10 pm V, = 0.05 V

= q-n: 2ytox+tsi NA A ~ F B

-1.0-

to.

= 5 nm
'

Fig. 5. Dependence of threshold voltage of p+-p+ and n+-n+ double-gate device on SO1 thickness.

= q-

tsi 1 - exp A .] V ) A~FB 2$0x tsi ' exP [P(%h2 - VFBp+)] exp [P(vG - V t h l ) ] .

NA

4 2ytox + tsi
V G

(+

(8)

Next, let us consider the potential distribution of the n+-p+ double-gate SO1 MOSFET's. The potential has a gradient because of the difference between flat band voltages of each gate. The potential distribution is shifted parallel maintaining its gradient with VG, and the inversion layer is formed on the inside surface of n+ polysilicon gate. From the similar triangles ABC and AED in Fig. 4, we obtain

B,

Khl

Kh2

The potential distribution in this gate voltage region is

(9)
and the sheet charges are formed on the inside surface of the n+ polysilicon gate. &I is then given by

When VG increases further, the line AD changes to become the line FD,and when point A reaches point F, the inversion layer is formed on the inside surface of the p+ polysilicon gate. Therefore, the second threshold voltage associated with the p+ polysilicon gate is
Vth2

= %h(P+-p +)

(5)

which is the same as that of p+-p+ double-gate SO1 MOSFET's. The numerical data agrees well with the analytical model (Fig. 5). depends on tox and ts; because of the interaction between the both gates. Since &h(p+-p+) and AVFB are independent of tox and tsi, the magnitude of V t h is hence a function of tox/tSi, and is about 0.25 V for toxltsi = 5. Vth2 is about 1 V, independent of device structure. Therefore, both channels contribute to conduction when the gate voltage exceeds 1 V, but the p+ polysilicon gate only controls K h l when the gate voltage is less than 1 V.
111. CONDUCTIVE CHARGE CONCENTRATION

'

+ cOx(vG -

exP [P(%h2 - VFBpf)] exp [P(vG - K h l ) ]

Khl)

(10)

where we apply a charge sheet approximation for the inversion layer charge.

We modeled the conduction charge concentration and evaluated the charge sheet approximation [25], [26] for this device.
A. VG Khl Looking at Fig. 4, the potential distribution in this gate voltage region is expressed as

C. VG > VthP be The potential distribution in this region is assumed uniform and constant at Vth2-VFBp+, and sheet charges are formed on the inside surface of the both n+ and p+ polysilicon gates. The &I in this region is then
&I

4(

A~FB ~= VG - VFB~+ 2$0x tsi Y )

= q l t s i exP [ P ( V t h 2 - VFB~+ 11

n2

(6)

NA

+ COx(vG -

T/thl)

+ COx(vG - Kh2).

(11)

SUZUKI AND SUGII: ANALYTICAL MODELS FOR n+-p+ DOUBLE-GATE SO1 MOSFET'S

1943

1oi4, 10'2

1
c

L ,
'

= 1 pm

tOx 5 nm t,, = 30 nm

F 1o'O
E
0
Y

2 -

lo0

'pnefl 400 cm2/Vs =

I
0.0

0 Numerical -Analytical (Total) ---Analytical (Sheet charge)

1Q,: off Q,: Off

tOx= 5 nm ts, = 30 nm VI,( = 0.19 v VI,, = 1.02 v

104L -0.5

0.5 1.0 1.5 Gate voltage (V)

(a)

2.0

0 Numerical -Analytical (Total) ----Analytical (Sheet charge)

a -

-Analytical ---Analytical

(IDl + I,,J (I,,,)

'
0

a %0
F

z
Y

. .....
. I . . .

.......- .....

Gate voltage (V)

(b)

Drain voltage (V)

Fig. 8. Comparison with the analytical and numerical data for t'0-1~ characteristics.

Fig. 6. Induced charge concentration: (a) log-plot, and (b) linear-plot.

The induced charge concentration N I = Q I / q calculated based on analytical models of (8), (lo), and ( 1 1) agree well with the numerical data in both the subthreshold and strong inversion regions (Fig. 6(a)). When VG exceeds K h l , the sheet charge concentration N I S
{COX(% Khl)/q ( K h l < VG < VthZ) 2 c O x ( v G - Vth1iVth2)/q (VG > K h Z )

drain current is then given by [27]

where saturation voltage, VDsat, and the critical electric field E, at which electron velocity saturates at U,, are

(12) dominates N I . When VG exceeds K h l , the contribution of the channel associated with the p+ gate to NI becomes significant (Fig. 6(b)). Consequently, the charge sheet approximation is also valid for this device.

IV. CURRENT VOLTAGE CHARACERIS~CS We consider only sheet charges in this section based on the results in Section 111. We regard this device as two transistors connected in parallel, and each has its own threshold voltage: Vthl relating to n+ polysilicon gate and Vth2 to p+ polysilicon gate. The

Operation mode mapping for VG-VO is shown in Fig. 7. Off corresponds to the off state, L correspond to linear region, and S correspond to saturation region. VDsatZ is always smaller than VDsatl. The analytical model agrees well with the numerical data (Fig. 8). To do a stringent test of the model, we neglect the vertical electric field dependence and use the same mobility model in [28] which is 1400 cm2/(Vs). This agreement means that the theory is accurate and can be a theoretical frame work which enables us to verify a mobility model.

1944

IEEE TRANSACTTONS ON ELECTRON DEVICES, VOL. 42, NO. 11, NOVEMBER 1995

. L, 0.1 km - tox=5nm 5 . V, = VJL, = lpm) - 0.3 V E 90 0

VG-VFB~+ which is a flat band voltage associated with the n+ polysilicon. Substituting (16) into (15), we obtain

100

d24f(x)
dx2

$gf

- $f(x)
A2

qNA
5

A~FB
2(1+

*)

(17)

-E
U)
Q) L

CJ)

80 70

where X is the natural length having the same physical meaning as X in [19], [20] but unique to the device given by

s 0
5
E

Introducing a variable

60-

Z 50
(17) reduces to

Fig. 9. Simulated dependenceof S-swing of p+-p+ double-gateand n+-p+ double-gate devices on SO1 thickness.

d277(x) 77(x) = 0, dx2 + T

The boundary conditions for the equation are

When VGexceeds K h 2 , the contribution of the channel associated with the p+ gate to the conduction becomes significant.

v.

SCALING THEORY

First, we evaluated the short channel effect using FLAPS (Fig. 9). When the SO1 thickness increases, subthreshold (22) = l?D = V S V D swing (S-swing) increases, but the magnitude is less for n+--p+ double-gate SO1 MOSFETs than that of p+-p+ where (Pj(0) is the built-in potential between source and double-gate SO1 MOSFETs. Therefore, n+-p+ double- neutral channel region given by gate SO1 MOSFETs are superior to p+-p+ double-gate SO1 MOSFETs in terms of short channel effect immunity, although p+-p+ double-gate SO1 MOSFETs are superior to single gate SO1 or bulk MOSFETs. N D is the doping concentration in the source and drain regions. To discuss this subject in more detail, we solved twoThen (20) is solved as dimensional potential distribution analytically, and obtained qs sinh 70 sinh ) ( ; an analytical expression for the short channel effects. The (24) 7(x) = sinh following analysis is similar to the previous method [191, [20], [29] applied to single-gate or p+-p+ double-gate SO1 The position x, where df is minimum and q5f at xm are MOSFETs. It is repeated here because the derivation is different in some parts reflecting the different device. The Poisson equation for potential, 4, is

(v) +
(F)

4f(Xm)

= $fO

+2 m j E e - Z

(26)

where N A is the channel doping concentration, and the yaxis is perpendicular and the x-axis is parallel to the channel (Fig. 1). Using the parabolic potential profile in the vertical direction as Young used [30] and applying the boundary conditions so that the potentials and electric flux are the same at the both gate oxide-SO1 interfaces, we obtained potential expression of

where 4 f o is the surface potential corresponding to that of long channel device and is qNA 2 A~FB (27) 4 f O = 4gf - -A Si

Assuming that the S-swing is dominated by is derived as

4 f m ,the S-swing

S=

81% ( I D )

In10 1 - -~ - p a+,(zm)

avc

In 10
where the origin is set at the SOYgate oxide interface on the n + polysilicon side. (Pf is the potential at y = 0, cbsr is

SUZUKI AND SUGII: ANALYTICAL MODELS FOR n+-p+ DOUBLE-GATE SO1 MOSFETS

1945

n QI

40
-Analytical model Numerical (p+- p' gate) O Numerical (n*- p+ gate)

>
Y

30
20 10

E
C

80.

L,

= 0.1

pm

'5
E
c
U) Q)

tOx 5 nm

*
0

70'

V, = 0.05 V

60

50 100 150 Silicon thickness (nm)

200

Fig. 10. Comparison with the analytical and numerical data for S-swing dependence on LG.

Fig. 1 1 . Relationship between SO1 and gate oxide thicknesses for various gate lengths.

When drain voltage is small, (28) reduces to

n

15

a
U

E
C

10

This is exactly the same expression for p+-p+ double-gate SO1 MOSFET [29] except for X which is

2 L
a
0

t/>
5

- 1.0

- i
I

.E

n
0 0

0.6 V

*According to our theory, if LG/(2X) is the same, the sswing is the same for p+-p+ and n+-p+ double-gate devices. This means that the n+-p+ double-gate device suffers less from short channel effects than the p+-p+ double-gate devices because X of n+-p+ double-gate SO1 MOSFET's of (18) is always smaller than that of p + - ~ +double-gate SO1 MOSFET's of (30), which is explained as the following: Punch through current flows along the surface for n+-p+ double-gate but it flows at the center of SO1 in the p+-p+ double-gate SOI, and the potential is controlled more strongly at the surface. The analytical model agrees well with the numerical data (Fig. 10). Our results show that we should design the device so that LG/(2X) is more than 3. Once the desired LG/(2X)is determined (we chose 3), the relationship between tox and tsi is obtained directly from the equation LG/(2X) = 3 (Fig. 11). tox and tsi for a given LG should be selected in the lower region of the corresponding LG curve. The allowable region decreases with decreasing LG and is wider for n+-p+ doublegate SO1 MOSFET's than for p+-p+ double-gate devices. Considering a device with an LG of 0.1 pm. The gate oxide thickness of this device is expected to be 3 nm [4], and we should set tsi to 15 nm to obtain an appropriate K h . This (tox,ts;) point is in the allowable region in Fig. 11. The analytical model for 10 using the above device parameters agrees well with the numerical data (Fig. 12). Since the

0.4 V

"

0.5 Drain voltage (V)

Fig. 12. comparison with the analytical and numerical data for 'VD-ID characteristics of a 0.1 p m LG device.

analytical model neglects the short channel effect, this good agreement means that we can regard devices as long-channel devices even for this gate length if the device is designed adhering the scaling theory.

VI. COMPARISON EXPERIMENTAL WITH DATA

We fabricated the device using a bonded SO1 substrate [23], [24]. The gate oxide thickness was 9 nm, and the SO1 thickness was 40 nm. Although the model is developed for nMOSFET's, it is applicable to pMOSFET' s by changing signs appropriately, and symmetrical characteristics are expected reflecting the symmetrical device structure for n- and pM0SFET's. The S-swing model explains well the experimental dependence of S-swing on the gate length (Fig. 13). We used an average electric dependent mobility model developed for bulk MOSFET's [31], [32]. In our device, the channel doping concentration is as low as 1015 ~ m - ~ ,

1946

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 1 1 , NOVEMBER 1995

100

5
0

E
C .-

0 Q

>

90 80

Experiment (nMOS)

z - 4
v

nMOS L = 0.96 pm , W =10pm

vGsCop

VGstep= 0.4 V

s!
0
C

3
2 1
0

v)

3 70

=I

E
O c 60
v)

g!
0

C ,
B
3
v)

50

O I

0.5

1.o

Gate length (pm)

Drain voltage (V)

Fig. 13. Comparison with the analytical model for gate length dependence of S-swing with experimental data. TABLE I MOBILITY MODEL

PARAMETERS FOR W A T S

W =10pm

and the electric field associated with the depleted charge is negligible. We also neglect the mobility associated with impurity scattering because we are analyzing strong inversion regions. Watt's mobility model has the same expression for p- and nMOSFET given by
1 -=-+kff

E 0.5
0.0 0

1 2 Drain voltage (-V)

(b)

1
psr

pph

Fig. 14. Comparison with the analytical drain current model with experimental data: (a) nMOSFET, and (b) pMOSFET.

where P p h is the mobility associated with phonon scattering, and psr is that associated with surface roughness scattering and each is given by

The effective electric field is

E e f f=

{ iEs 3ES

for nMOSFET} forpMOSFET .

(35)

(33)
The parameter are different for p and n MOSFET's, and are given in Table I. Neglecting the depleted charge, the surface electric field is given by

(34)

Note that the threshold voltage is different for front and back gates, and the pertaining electric field and effective electric field are also different. In the derivation of (13), the transversal electric field dependence of mobility is considered [27]. An analytical drain current model agrees well with experimental data for both p- and nMOSFET's with an LG of 0.96 pm (Fig. 14(a) and (b)). Therefore, Watt's mobility model is applicable to our device even though it was developed for bulk MOSFET's. This agrees with a recent investigation on mobility of fully depleted SO1 MOSFET's [33]. From these results, we do not need a unique mobility model for this device. Disagreement occurred between theory and experiment at VG of 2 V for an nMOSFET. Since we observe negative

SUZUKI AND SUGII: ANALYTICAL MODELS FOR n+-p+ DOUBLE-GATE

so1 MOSFETS

1947

resistance at this VG,the disagreement is caused by the selfheating effect [34], [35]. VII. SUMMARY We proposed n+-p+ double-gate SO1 MOSFETs, and established the theory for this device: threshold voltage, conductive charge, current voltage characteristics, and scaling theory. The device has two threshold voltages related to the n+ and p+ gates, K h l and KhZ, respectively. depends on tox and tsj and is less than 0.3 V at tsi/tox = 5. KhZ is independent of tox and ts; and is about 1.O V. Therefore, when the gate voltage VGexceeds 1 V, both channels contribute to the conduction, but when VG is less than 1 V, p+ gate only plays a role of controlling Vthl. We derived conduction charge concentration assuming linear potential distribution and verified the validity of the model by comparing it with numerical data. We also showed that the charge sheet approximation for inversion layer charge is valid. We regarded this device as two transistors with different threshold voltages connected in parallel, and proposed a drain current model. The analytical model agrees well with numerical data even for the deep submicron devices designed adhering the scaling theory. We also showed that the analytical model agrees well with experimental data, and that Watts mobility model is also applicable to this device. Assuming that the minimum potential determines the subthreshold swing, we derived an analytical expression for the dependence of S-swing on device parameters, and showed how we design tox and tsi with decreasing LG. In conclusion, n+-p+ double-gate SO1 MOSFETs suffer less from short channel effects. Using these devices, we can overcome the scaling limits of bulk MOSFETs and design devices with an LG of less than 0.1 pm while maintaining an ideal S-swing and proper V&.
ACKNOWLEDGMENT

We thank Dr. S. Hijiya and Dr. T. Itoh for their encouragement.

REFERENCES [I] R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. L. Blanc, Design of ion-implanted MOSFETs with very small physical dimensions, IEEE J. Solid-state Circuits, vol. SC-9, pp. 256-268, 1974. [2] J. R. Brews, W. Fichtner, E. H. Nicollian, and S. M. Sze, Generalized guide for MOSFET miniaturization, IEEE Electron Device Len.,vol. EDL-1, pp. 2 4 , 1980. [3] P. Chatterjee, W. R. Hunter, T. C. Holloway, and Y. T. Lin, The impact of scaling laws on the choice of n-channel or p-channel for MOS VLSI, IEEE Electron Device Lett., vol. EDL-1, pp. 220-223. 1980. [4] G. Baccarani, M. R. Wordeman, and R. H. Dennard, Generalized scaling theory and its application to a 114 micrometer MOSFET design, IEEE Trans. Electron Devices, vol. ED-31, pp. 452462, 1984. [5] T. Y. Chan, P. K. KO, and C. Hu, Dependence of channel electric field on device scaling, IEEE Electron Device Lett., vol. EDL-6, pp. 551-553, 1985. [6] T. Sehgawa and Y. Hayashi, Calculated threshold-voltage charactenstics of an XMOS transistor having an additional bottom gate, Solid-state Electron., vol. 27, pp. 827-828, 1984.

[7] J. P. Colinge, M. H. Gao, A. R-Rodriguez, and C. Claeys, Siliconon-insulator gate-all-around device, in I990 IEDM Tech. Dig., pp. 595-598. [8] D. Hisamoto, T. Kaga, and E. Takeda, Impact of the vertical SO1 DELTA structure on planar device technology, IEEE Trans. Electron Devices, vol. 38, pp. 1419-1424, 1991. [9] H. Hone, S. Ando, T. Tanaka, M. Imai, Y. Arimoto, and S. Hijiya, Fabrication of double-gate thin-film SO1 MOSFETs using wafer bonding and polishing, in I991 SSDM Tech. Dig., pp. 165-167. [lo] T. Tanaka, H. Horie, S . Ando, and S. Hijiya, Analysis of p+ doublegate thin-film SO1 MOSFETs, in I991 IEDM Tech. Dig., pp. 683-6 86. [ 111 D. J. Frank, S. E. Laux, and M. V. Fischetti, Monte Carlo simulation of a 30- nm dual-gate MOSFET How short can Si go?, in I991 IEDM Tech. Dig., pp. 553-556. [12] F. Balestra, S. Cristoloveanu, M. Benachir, and T. Elewa, Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance, IEEE Electron Device Len., vol. EDL-8, pp. 4 1 M 1 2 , 1987. [13] S. Venkatesan, G. W. Neudeck, and R. F. Pierret, Dual-gate operation and volume inversion in n-channel SO1 MOSFETs, IEEE Electron Device Lett., vol. 13, pp. 4446, 1992. [I41 A. Terao and F. van de Wiele, An analytical model for GAA transistors, Microelectron. Eng., vol. 15, pp. 233-236, 1991. [15] P. Francis, A. Terao, D. Flandre, and F. van de Wiele, Characteristics of nMOS/GAA (Gate-All-Around) transistors near threshold voltage, Microelectron. Eng., vol. 19, pp. 815-818, 1992. [I61 J. Brini, M. Benachir, G. Ghibaudo, and F. Balestra, Threshold slope of the volume-inversion MOS transistor, ZEE Proc. G, vol. 138, pp. 133-136, 1991. 1171 K. Suzuki, T. Tanaka, Y. Tosaka, H. Hone, Y. Arimoto, and T. Itoh, Analytical surface potential expression for thin-film double-gate SO1 MOSFETs, Solid-state Electron., vol. 37, pp. 327-332, 1994. [18] K. Suzuki, S. Satoh, T. Tanaka, and S. Ando, Analytical models for symmetric thin-film double-gate silicon-on-insulator metal-oxidesemiconductor-field-effect-transistors,Jpn. J. Appl. Phys., vol. 32, pp. 4916-4922, 1993. [I91 R. H. Yan, A. Ourmazd, and K. F. Lee, Scaling the Si MOSFET; from bulk to SO1 to bulk, IEEE Trans. Electron Devices, vol. 39, pp. 17041710, 1992. [20] K. Suzuki, Y. Tosaka, T. Tanaka, H. Hone, and Y. Arimoto, Scaling theory for double-gate SO1 MOSFETs, IEEE Trans. Electron Devices, 40, pp. 2326-2329, 1993. [21] S. Satoh, H. Oka, and N. Noriaki, Bipolar circuit simulation system using two-dimensional simulator, Fujitsu Sci. Tech. J . , vol. 24, pp. 456463, 1988. [22] J. M. Hwang and G. Pollack, Novel p o l y s i l i c o f l i structure for fully depleted SOYCMOS, in 1992 IEDM Tech. Dig , pp. 345-348. [23] T. Tanaka, K. Suzuki, H. Hone, and T. Sugii, Ultrafast operation of Vth -adjusted p+-n+ double-gate SO1 MOSFETs, IEEE Electron Device Lett., vol. 15, pp. 386-388, 1994. (241 K. Suzuki, T. Tanaka, Y. Tosaka, H. Hone, and T. Sugii, High-speed and low-power n+-p+ double-gate CMOS, IEICE Trans. Electron., E78-C, pp. 360-367, 1995. 1251 J. A. Geurst. Theon,of IGFET near and beyond pinch-off, Solid-state -~ -~ Electron., vol. 9, pi. 129-142, 1966. [26] J. R. Brews, A charge sheet model of MOSFET, Solid-State Electron., vol. 21, pp. 345-355, 1978. [27] C. G. Sodini, P. K. KO, and J. L. Moll, The effect of high fields on MOS device and circuit performance, IEEE Trans. Electron Device, vol. ED-31, pp. 1386-1393, 1984. [28] D. L. Scharfetter and H. K. Gummel, Large-signal analysis of a silicon diode oscillator, IEEE Trans. Electron Devices, vol. ED-16, pp. 6 4 7 7 , 1969. [29] T. Tosaka, K. Suzuki, and T. Sugii, Scaling-parameter-dependent model for subthreshold swing S in double-gate SO1 MOSFETs, IEEE Electron Device Lett., vol. 15, pp. 466468, 1994. [30] K. K. Young, Analysis of conduction in fully depleted SO1 MOSFETs, IEEE Trans. Electron Devices, vol. 36, pp. 504-506, 1989. [31] J. T. Watt and J. D. Plummer, Universal mobility-field curves for electrons and holes in MOS inversion layers, in 1987 Symp. VLSI Tech. Dig., 81-82. pp. [32] S. Takagi, M. Iwase, and A. Tonumi, On the universality of inversionlayer mobility in n- and p-channel MOSFETs, in I988 IEDM Tech. Dig., pp. 398401. [33] J. Wang, N. Kistler, J. Woo, and C. R. Viswanathan, Mobility-field behavior of fully depleted SO1 MOSFETs, IEEE Electron Device Lett., vol. 15, pp. 117-119, 1994.

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[34] K. E. Goodson and M. I. Flik, Effect of microscale thermal conduction on the packing limit of silicon-on insulator electronic devices, IEEE Trans. Electron Devices, vol. 15, pp. 715-722, 1992. [35] L. T. Su, K. E. Goodson, D. A. Antoniadis, M. I. Flik, and J. E. Chung, Measurement and modeling of self-heating effects in SO1 nMOSFETs. in 1992 IEDM Tech. Dig., 357-360. pp.

Kunihiro Suzuki 91) was bom in Aomori, 1959. He received BS. and Japan, in M.S. degrees in electronics engineering from Tokyo Institute of Technology in 1981 and 1983, respectively. He joined Fujitsu Laboratories Ltd., Atsugi, Japan, in 1983, and has been engaged in the design and modeling of high-speed bipolar and SO1 MOS transistors.

Toshihiro Sugii was born in Kyoto, Japan, in November 1956. He received the B.S., M.S., and Ph.D degrees in electronics engineering from the Tokyo Institute of Technology, Tokyo, Japan, in 1979, 1981, and 1991, respectively. In 1981, he joined Fujitsu Laboratories Ltd., Atsugi, Japan, where he has been engaged in the research and development of VLSI devices and processes. His research interests are in Siheterojunction bipolar transistors and sub-quarter rmcron CMOS devices. Dr. Sugii is a member of the Japan Society of Applied Physics.