Chapter 5 Static Timing Analysis

Static Timing Analysis
Instructor: Tel: Email: 03-5773693 ext.149 cschen@cic.org.tw

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Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
Timing Analysis
Dynamic Timing Analysis (DTA) Static Timing Analysis (STA)
Dynamic Timing Analysis

So-called Simulation
Input vectors are applied during the simulation time Simulator calculates the logic value and delays
Disadvantages of DTA
Virtually impossible to do exhaustive analysis

Vector creation takes too long Incomplete timing coverage
Hard to discern the cause of failure because the function and timing are analyzed at the same time Requires more memory and CPU resources over STA

Long simulation time Capacity limited
Static Timing Analysis (1/2)

A method for determining if a circuit meets timing constraints without having to simulate clock cycles Three main steps
Break the design into sets of timing paths Calculate the delay of each path (create timing graph) Check all path delays to see if the given timing constraints are met
IN
D Q QN D Q QN
OUT
CLK
Static Timing Analysis (2/2)
IN
Q QN
Q QN
OUT
CLK
Static Timing Analysis Reduction
IBMs Hitchcock (70s) observed that you could exhaustively test all behaviors within a single clock cycle
Advantages of STA
Exhaustive timing coverage Does not require input vectors More efficient than DTA in memory and CPU resources
Faster operation Capacity for millions of gates
Disadvantages of STA
For synchronous logic only Difficult to learn Tricky constraints beyond the boundaries of single clock flip-flop design chips:
Multiple clocks False paths Latches Multi-cycle paths
Lack of consistent conventions
Review Main Steps of STA

Break the design into sets of timing paths Calculate the delay of each path (create timing graph) Check all path delays to see if the given timing constraints are met
Four Types of Timing Paths
Start Point: clock pin of sequential device End Point: data input pin of sequential devices
Start Point: primary input port End Point: data input pin of sequential devices
Start Point: clock pin of sequential device End Point: primary output port
Start Point: primary input port End Point: primary output port
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Timing Path Example

How many start points are in this design? How many end points are in this design? How many timing paths are in this design?
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Create Timing Graph

Netlist is represented as directed acyclic graph (DAG) Delay values associated with links (Cells & Nets) are calculated Create the timing graph of arrival time (AT) Create the timing graph of required time (RT) Create the slack graph
Timing is met when slack is greater than or equal to zero (RT should always be after AT)
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Timing Graph Arrival Time

1.45
0.3 0.1 0.4
0.55 1.3 0.1 1.2 0.65 0.20.85 0.1 0.2 0.7 0.2 0.9 1.0 0.1 0.1
0.1 1.55 0.15
Tarr = 0.1
0.2
0.15
Timing Arc
0.3 0.4
0.1 1.3
0.2 0.1 0.2 0.6
Tarr = 0.1
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Timing Graph Required Time
0.3 0.1 0.4 0.1 0.2 0.15
1.4 0.55 1.25 0.1 0.1 0.15 0.1
Treq = 1.5
0.05
1.15 0.65 0.20.85 0.1 0.2 1.4 0.65 0.2 0.95 0.25 0.35 0.1 0.2 0.1 0.2 0.55
0.1
Tarr = 1.5
setup time case

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Slack Graph
0 0 0 -0.05 -0.05 -0.05 -0.05 -0.55 -0.05 0 0 -0.05
-0.05 -0.05
-0.05 -0.05
0.2
Slack = Required Time Arrival Time

setup time case
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Block-based vs. Path-based STA (1/2) Block-based Path-based

Block-based: timing information is associated with discrete design elements (ports, pins, gates)
Slack is calculated on every design element
Path-based: timing information is associated with topological paths (collections of design elements)
Used in Primetime
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Block-based vs. Path-based STA (2/2) Block-based Path-based

AT=2 3 1 AT=5
Path-based:
2 1 3 2 3 1 RAT=10 2+2+3 = 7 (OK) 2+3+1+3 = 9 (OK) 2+3+3+2 = 10 (OK) 5+1+1+3 = 10 (OK) 5+1+3+2 = 11 (Fail) 5+1+2 = 8 (OK)
AT=2
AT=2 RAT=5
3 1 AT=5
AT=5 RAT=4
2 1
AT=6 RAT=5
AT=7 RAT=7
Block-based:
3 2 RAT=10
AT=11 RAT=10
3 1
AT=9 RAT=8
Critical path is determined as collection of gates with the same, negative slack: In our case, we see one critical path with slack = -1
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Timing Arcs
Describes the timing relationship between two nodes When traversing the design structure to update AT and RT, STA is actually traversing through timing arcs from node to node Defined in cell library
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Combinational Arcs
Combinational arcs (Timing delay)
Combinational arcs are the default arcs Each combinational arc has one of three timing senses Timing senses are specified in the library or automatically derived from the logic function
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Setup Timing Arcs

Setup arcs (Timing check)
Constrains the time before the active clock edge when the data needs to be stable

setup_rising setup_falling
CK
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Hold Timing Arcs

Hold arcs (Timing check)
Constraints for the time after the active clock edge when the data still needs to be stable

hold_rising hold_falling
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Edge Arc Types

Edge arcs (Timing delay)
After a launching clock edge, the clock node is converted to a data node

falling_edge rising_edge
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Preset and Clear Types

Preset and Clear arcs (Timing delay)
After an active asynchronous signal occurs, the time the data appears at the output of the register

positive_preset / negative_preset positive_clear / negative_clear
These arcs are often disabled
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Recovery Types
Recovery arcs (Timing check)
The amount of time before an active clock edge an asynchronous signal needs to be inactive

recovery_rising recovery_falling
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Removal Arcs
Removal arcs (Timing check)
The amount of time after an active clock edge an asynchronous signal needs to be inactive

removal_rising removal_falling
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Three State Arcs

Three state enable & disable arcs (Timing delay)
Special timing relationship for three state activation

three_state_enable three_state_disable
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Minimum Pulse Width Types

Width arcs (Timing check)
The amount of time a signal needs to remain stable

nochange_high nochange_low
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Timing Verification Items

Timing Checks
Setup time Hold time Recovery time Removal time Minimum pulse width Glitch detection (clock gating)
User-defined
Design Rule Checks

Max capacitance Max transition Max fan-out
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Clock Gating Checks

D Q QN D Q QN
Enable CLK Setup Margin

CLK Enable Enable
U1
Hold Margin
Distorted Clock Waveform

Gated_Clock Enable
Glitch due to late arrival time of Enable

Gated_Clock
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Data Preparation for STA

Gate-level Netlist Design Data Block Models Back-annotated Parasitic Interconnect Data Estimated Wire Load Models
STA
Descriptions of Clocks Cell Library Library Data Operating Conditions Timing Exceptions Timing Constraints Boundary Conditions
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Library Data
Cell Delay model
Linear model Non-linear model
Operating conditions
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Linear Cell Delay Model
delay time (ns)
T0
Cell Delay = T0 + Ac * Cload
output capacitance load (pf)

T0 : cell pin to pin intrinsic delay (delay without any loading) Ac : drive impedance
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Non-linear Cell Delay Model Non-linear

Delay values are stored in the delay tables Delay tables
Cell delay Transition delay Vin
50% 50%
Vout
20% 80%
I1 I2 Dtransition(I1)
Dc Req
Dtransition(I2) I3 Ceq
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Dcell(I2)
Delay Tables
Cell Delay Transition Delay
Output Capacitance 0.1 0.2
Dcell(I2) = f(Dtransition(I1), Ceq) Dtransistion(I2) = g(Dtransition(I1), Ceq)
Input Transition 0 0.123 0.222 0.5 0.234 0.432 1 0.456 0.801
index1: input transition Index2: output capacitance
Vin I1 I2 Dtransition(I1)
Dc Vout Dtransition(I2) Req Ceq

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I3
Dcell(I2)
Select the Correct Delay Table

According to output transition direction
rise table fall table invert (positive_unate) noninvert (negative_unate) nonunate
Output transition direction depends on unateness
R or F R
The worst case delay is selected
Consider the clock edge for sequential cells

edge_rising edge_falling
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Operating Conditions
The process, voltage, and temperature (PVT) ranges a design encounters Specified in the technology library Cell and interconnect delays are scaled
Dscale = D (1 + P K P )(1 + V KV )(1 + T K T ) P = Pr ocess nom _ process / V = Voltage nom _ voltage T = Temperature nom _ temperature
delay Worst Typical Best Process Voltage Best Temperature 36 delay Worst Typical Best delay Worst Typical

STA
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Define Timing Constraints

Design rule constraints
Set fan-out constraints Set capacitance constraints Set transition time constraints
Design optimization constraints

Define clock specification Specify boundary conditions (I/O timing requirements) Specify combinational path delay requirements Specify timing exceptions
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Define Clock Specification

We need to accurately specify the clock including the clock routing details in the early design stage in order to achieve timing convergence What should be defined?
Period Waveform Latency

Source latency Network latency Jitter Skew
Uncertainty

All register-to-register path are constrained now

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Clock Period & Waveform

Period: Clock cycle time Waveform: Clock rise and fall time Example:
Period: 10ns Rise time: 0ns Fall time: 5ns
clock 0 5 10
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Clock Latency
A very important part of the clock is the routing effects:
Off Chip cause:
Source latency (delay): the timing a clock signal takes to propagate from its ideal waveform original point to the clock definition point Budgeted network latency (delay) : the time the clock signal takes to propagate from the clock definition point to the clock pin of the sequential cells Actual insertion delay D Q
QN
On Chip cause:
network latency source latency (min_rise : max_rise : min_fall : max_fall)

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Clock Uncertainty Definition

The maximum difference between the arrival of clock signals at sequential cells in one clock domain or between domains
P1
FF
P4
FF
P2 P3
FF
Arrival(P1) Arrival(P2) Arrival(P3) Arrival(P4)
= = = =
0.5ns 1ns 1.2ns 1.3ns
uncertainty = 1.3 0.5 = 0.8ns

FF
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Clock Uncertainty
A very important part of the clock is the routing
Off Chip impact:
Jitter: typically a small value Budgeted skew Actual skew
On Chip impact:

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Ideal and Computed Clocks

Off chip clock effects are fixed throughout flow:
Source Latency Jitter
On chip routing is estimated till clock tree routing

Budgeted network latency Budgeted skew
On chip routing is calculated after clock tree routing

Actual insertion delay (network latency) Actual skew
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I/O Constraints
After constraining clock, we still need to constrain the I/O
Only comboin needs a "budgeted" arrival time Only combout needs a "budgeted" required time
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Boundary Conditions
Input driving cell Input transition time Output capacitance load Input delay Output delay
D Q QN
b
5pf
Driving Cell INV01
Output Capacitance Load Input Transition Time
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Input & Output Delay

An input delay is the specification of an arrival time at an input port relative to a clock edge An output delay represents an external timing path from am output or inout port to a register
Input delay = Delayclk-Q + a
Q
Input Block
My Design
Output Block Output delay = c
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Constraint Combinational Path Delay

Set a target maximum delay for output ports Override the default single-cycle timing for paths Set a target minimum delay for output ports Override the default hold relation in a sequential path
IN
Logic
Out
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False Path Multi-cycle path
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False Path
Why are there false path constraints in a design?
A path may exist in the circuit but never be used in its normal functional operation A functional path may exist but the timing is very slow or irrelevant A block may be reused and certain signal functions are no longer required A path may exist in the circuit but no combination of input vectors may ever exercise it A combinational loop exists in the design that needs to be broken
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Unexercised Path
A path may exist in the circuit but never be used in its normal functional operation
A test register PROBE is inserted in the circuit to enable chip debugging in the field. Data can be read through the probe register. Data can be written from the probe register. Probing would not occur at speed. (An alternative to scan)
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False Path
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Irrelevant Path
A functional path may exist but the timing is so slow or irrelevant
The chip uses a synchronized synchronous reset. The reset cycle has a huge number of cycles before it needs to settle.
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Asynchronous Path
A functional path may exist but the timing is so slow or irrelevant
I have metastabilization registers between those two asynchronous clock zones
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False Path
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IP Reuse
A block may be reused and certain signal functions are no longer required
This piece of logic is a custom adder. With design re-use, often the blocks contain all of the potentially useful functions. When the design is implemented in a chip, often particular signals are not implemented
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False Path
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Logically Impossible Path

A path may exist in the circuit but no combination of input vectors may ever exercise it
A signal cannot travel from the Q output of a_reg through the two muxes to b_reg PrimeTime attempts to automatically detect "logically impossible false paths (requires many CPU cycles) These situations are quite rare
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False Path
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Combinational Loops
A combinational loop exists in the design that needs to be broken
Most STAs cant leave combinational loops in the design, as a race condition will occur PrimeTime dynamically breaks combinational loops.
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Break Combinational Loops

Break any reset arc (unusually specified) Break a three-state enable arc Break at the first loop re-entry point Break arcs in the library
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False Path Multi-cycle path
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Multicycle Paths
Multicycle paths occur because the designer knows that the particular logic function will not be used till a later cycle
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STA
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Interconnect Data
Estimated delay information for nets based on a wire load model is used before P&R Back-annotated (Actual) delay information based on the P&R result is often described in the form of
SDF (timing information) Standard Delay Format
SDF triplet: (min:typ:max)
RSPF Reduced Standard Parasitic Format DSPF Detailed Standard Parasitic Format SPEF Standard Parasitic Exchange Format
SPEF also has syntax that allows the modeling of capacitance between different nets, so it is used by the crosstalk analysis tool
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Wireload Model
Very inaccurate!
wire_load (500) ( resistance : 3.0 capacitance: 1.3 area: 0.04 slop: 0.15 fanout_length ( 1 , 2.1 ) fanout_length ( 2 , 2.5) fanout_length ( 3 , 2.8) fanout_length ( 4 , 3.3) /* R per unit length*/ /* C per unit length */ /* area per unit length */ /* extrapolation slope*/ /* fanout-length pairs */
500um x 500um 1000um x 1000um
Cwire = (fanout=3, length =2.8) x capacitance coefficient (1.3) = 3.64 load units Rwire = (fanout=3, length =2.8) x resistance coefficient (3.0) = 8.4 resistance units AreaNet = (fanout=3, length =2.8) x area coefficient (0.04) = 0.112 net area units
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Wireload Modes
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Parasitic Model During P&R

Compute wire length
Ideal Manhattan Model Computed Manhattan Model Global Routing Model
Compute parasitic value

Linear parasitic model Table lookup parasitic model
Calculate wire delay

Elmore Model Final Layout Model
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Ideal Manhattan Model
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Computed Manhattan Model
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Global Routing Model
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Table Lookup Parasitic Model

Table-Look-Up (TLU) Capacitance model
CapTable
cap_value = f(configuration, width, spacing) Assign CapTable to the reference layer according to the configuration Capacitances are categorized into bottom, top and lateral group
CapModel
M2 M1 Poly
configuration1
air
top lateral substrate bottom
configuration2
configuration3
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Elmore Model
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Final Layout Model

AWE (Extraction Based) Model
p1 , p2 Poles r1 , r2 - Residues
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Perform Static Timing Analysis

Gate-level Netlist Block Models Cell Library Operating Conditions Back-annotated Parasitic
Specify design data & libraries
Estimated Wire Load Models
Specify interconnect Specify timing constraints Check Timing

Constraint Violation Reports Path Timing Reports
Descriptions of Clocks Boundary Conditions Timing Exceptions
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STA Example 1 (Assumptions)

Check setup time violations Assume all gates have 3ns max rise delay and 2ns min rise delay Assume all gates have 2ns max fall delay and 1ns min fall delay Assume all nets have 2ns max delay and 1ns min delay 3ns CLK-Q delay 1ns setup time (Ts) 1ns hold time (Th)
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STA Example 1 (Timing Constraints)

Clock definition
Clock period: 14ns (Dclkp) Clock source latency: 2ns (Dclks) Clock network latency: 3ns (Dclkn) Clock uncertainty: 1ns (Dclku)
IO constraints
Input delay of A, B, C: 1ns (Da , Db , Dc) Output delay of Y: 3ns (DY)
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STA Example 1 (Timing Paths)
Timing Path 1 Timing Path 2 Timing Path 3

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STA Example 1 (AT of Path1 - Rise)

Timing path 1: PI to clock data input
Arrival time at end point: Da+2+3+2+3+2 = 13ns
launch edge 0 13 14 capture edge AT target clock (ideal) source clock (ideal)
2 3 R 2
AT = 13 2
Why are the delay values chosen?
R 3
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STA Example 1 (AT of Path1 - Fall)

Arrival time at end point: Da+2+2+2+3+2 = 12ns
launch edge 0 12 14 capture edge AT target clock (ideal) source clock (ideal)
2 2 F 2
AT = 12 2
R 3
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STA Example 1 (RT of Path1 - R/F)

Required time at end point: Dclkp + Dclks + Dclkn - Dclku - Ts = 14+2+3-1-1 = 17ns
launch edge 0 14 target clock (ideal) 16 target clock (source) source clock (ideal)
capture edge 19 target clock (source+network) 18 RT 17

target clock (source+network +uncertainty) setup time
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STA Example 1 (Slack of Path1 - Rise)

Slack at end point: RT - AT = 17-13 = 4ns Timing is met since slack is greater than 0
R 2 3 R 2 R 3 2
AT = 13 RT = 17
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STA Example 1 (Slack of Path1 - Fall)

Slack at end point: RT - AT = 17-12 = 5ns Timing is met since slack is greater than 0
AT = 12 RT = 17 2 F 2 R 3 2
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Timing path 2: clock to clock data input
Arrival time at end point: Dclks + Dclkn +3+2+3+2+3+2 = 20ns
source clock (ideal) 0 5 launch edge 14 19 20 AT source clock (source +network)
AT = 20 3 R2 3 R 2 3 2 R
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source clock (ideal) 0 5 launch edge 14 19 AT source clock (source +network)
AT = 19 3 F2 2 F 2 3 2 R
87

Required time at end point: Dclkp + Dclks + Dclkn - Dclku - Ts = 14+2+3-1-1 = 17ns
launch edge 0 5 14 16 source clock (source+ network) target clock (ideal) target clock (source)
capture edge 19 target clock (source+network) 18 RT 17

target clock (source+network +uncertainty) setup time
88

Slack at end point: RT - AT = 17-20 = -3ns Timing is not met since slack value is negative
AT = 20 3 3 RT = 17 R 2 3 2 R
R2
89

AT = 19 RT = 17 3 F2 2 F 2 3 2 R
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Timing path 3: clock to PO
Arrival time at end point: Dclks + Dclkn +3+2+3+2= 15ns
source clock (ideal) 0 5 launch edge 14 15 source clock (source +network)
AT
3 R 2 3
AT = 15 R 2
91

source clock (ideal) 0 5 launch edge AT 14 source clock (source +network)
3 F 2 2
AT = 14 F 2
92

Required time at end point: Dclkp - DY = 14-3 = 11ns
launch edge 0 5 RT 11 14 source clock (source+ network) target clock (ideal) output delay
3 F 2 2
RT = 11 F 2
Q QN
93

Slack at end point: RT - AT = 11-15 = -4ns Timing is not met since slack value is negative This is the critical path
3 R 2 3
AT = 15 RT = 11 3 R 2
QN D Q
94

3 F 2 2
AT = 14 RT = 11 F 2 3
D Q QN
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STA Example 2 (Assumptions)

Check hold time violations Assume all gates have 3ns max rise delay and 2ns min rise delay Assume all gates have 2ns max fall delay and 1ns min fall delay Assume all nets have 2ns max delay and 1ns min delay 3ns CLK-Q delay 1ns setup time (Ts) 1ns hold time (Th)
96
STA Example 2 (Timing Constraints)

Clock definition
Clock period: 14ns (Dclkp) Clock source latency: 2ns (Dclks) Clock network latency: 3ns (Dclkn) Clock uncertainty: 1ns (Dclku)
IO constraints
Input delay of A, B, C: 1ns (Da , Db , Dc) Output delay of Y: 3ns (DY)
97
STA Example 2 (Timing Paths)
Timing Path 1 Timing Path 2 Timing Path 3

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STA Example 2 (AT of Path1 R/F)

Arrival time at end point: Da+1 = 2ns
launch edge 0 2 capture edge AT Next Data AT = 2
D Q QN
source clock (ideal) 14 target clock (ideal) Why are the delay values chosen?
R/F 1 1
99

Required time at end point: Dclks + Dclkn + Dclku + Th = 2+3+1+1 = 7ns
launch edge 0 7 target clock (ideal) target clock (source) target clock (source+network) capture edge RT hold time
source clock (ideal)
target clock (source+network +uncertainty)
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STA Example 2 (Slack of Path1 R/F)

Slack at end point: AT - RT = 2-7 = -5ns Timing is not met since slack value is negative This is the critical path
Q QN
R/F 1 1 AT = 2 RT = 7
101

source clock (ideal) 0 5 launch edge 14 AT 19 20 source clock (source +network) Next Data AT = 15 3 R1 2 R 1 2 1 R Why are the delay values chosen?
102

source clock (ideal) 0 5 launch edge 14 source clock (source +network) Next Data AT = 14 3 F1 1 F 1 2 1 R Why are the delay values chosen?
AT
103

Required time at end point: Dclks + Dclkn + Dclku + Th = 2+3+1+1 = 7ns
launch edge 0 7 target clock (ideal) target clock (source) target clock (source+network) capture edge RT hold time
source clock (ideal)
target clock (source+network +uncertainty)
104

Slack at end point: AT - RT = 15-7 = 8ns Timing is met since slack is greater than 0
AT = 15 RT = 7 3 2 R 1 2 1 R
R1
105

Slack at end point: AT - RT = 14-7 = 7ns Timing is met since slack is greater than 0
AT = 14 RT = 7 3 F1 1 F 1 2 1 R
106

source clock (ideal) 0 5 launch edge 12 AT Next Data source clock (source +network)
3 R 1 2
AT = 12 R 1
107

Arrival time at end point: Dclks + Dclkn +1+1+1= 11ns
source clock (ideal) 0 5 launch edge 11 AT Next Data source clock (source +network)
3 F 1 1
AT = 11 F 1
108

Required time at end point: - DY = -3ns
launch edge -3 0 source clock (source+ network) target clock (ideal) RT output delay
F 1 1
RT = -3 F 1
Q QN
109

Slack at end point: AT - RT = 12-(-3) = 15ns Timing is met since slack is greater than 0
AT = 12 R 1 2 RT = -3 R 1
D Q QN
110

Slack at end point: AT - RT = 11-(-3) = 14ns Timing is met since slack is greater than 0
AT = 11 F 1 1 RT = -3 F 1 3
Q QN
111
Handling Multiple Clocks

Determine the least common multiple (LCM) of the 2 clock periods first and then find the setup and hold relationship
112
Setup Relationships
Find the Setup Relationship between A rising to B rising The setup relationship is the closest distance between the launching clock edge (A) to the receiving clock edge (B)
113
Hold Relationships
Find the Hold Relationship between A rising to B rising The hold relationship is the closest distance between the launching edge (A) to the previous receiving edge (B)
114
STA with Latches

Latches and Flip-Flops are both registers or "storage devices Latches are level sensitive instead of edge triggered
115
Time Borrowing Example 1

If these were flip flops, timing would not be met at b_reg With time borrowing, the middle latch can borrow time from the next stage and meet timing!
116

Can time borrowing eliminate negative slack?
No, the final data missed the active edge of c_reg.
117

No, c_reg is a flip-flop and the data misses c_regs edge
118

Yes! In fact there is extra time before the activating edge of c_reg
119

No. The earliest b_reg can launch the data is at time 5. c_reg will receive the data too late
120
Four Types of Analysis

Single operating condition analysis
Worst operating condition Typical operating condition Best operating condition
Simultaneous best-case/worst-case analysis On-Chip variation Case analysis
121
Single OC Analysis
Typically, you need to perform timing analysis for at least two operating conditions to ensure that the design has no timing violations
Best case (minimum path report) (Hold Time Check) Worst case (maximum path report) (Setup Time Check)
CIC 0.18um library example

fast.lib typical.lib slow.lib
122
Best/Worst Case Analysis

For most of STA tools, you can simultaneously perform timing analysis for the best-case and worstcase operating conditions.
Max paths analyzed with worst case OC (Setup Time Check) Min paths analyzed with best case OC (Hold Time Check)
Min-max values can be also specified for

SDF back-annotated delays Input and output delays Wire load models Net resistance-capacitance Clock latency/transition Driving cell
123
On-Chip Variation Analysis On-Chip

Delays have uncertainty due to the variation of PVT across large dies On-chip variation allows you to account for the delay variations due to PVT changes across the die, providing more accurate delay estimates.
124
Case Analysis
Timing analysis with specified logic value conditions on pins or ports Logic constants are propagated to avoid unnecessary timing path analysis (3 paths in this example)
conditional combinational timing arc
F2
F 2 2 0 2 F 0
125
STA in Cell-based Design Flow Cell-based

After each run of synthesis
Synopsys Design Compiler / Cadence Ambit Magma Blast RTL / Blast Fusion
After each run of physical optimization

Synopsys Physical Compiler / Synopsys Saturn Synopsys Astro / Cadence SE / Cadence SOC Encounter
After each run of P&R

Synopsys Apollo / Astro Cadence SE / Cadence SOC Encounter Magma Blast Fusion
STA sign-off
Primetime
126

Chapter 5 Static Timing Analysis

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Chapter 5 Static Timing Analysis

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Static Timing Analysis

Instructor: Tel: Email: 03-5773693 ext.149 cschen@cic.org.tw

Dynamic Timing Analysis

Vector creation takes too long Incomplete timing coverage

Long simulation time Capacity limited

Static Timing Analysis (1/2)

Static Timing Analysis (2/2)

Static Timing Analysis Reduction

Lack of consistent conventions

Review Main Steps of STA

Four Types of Timing Paths

Timing Path Example

Create Timing Graph

Timing Graph Arrival Time

0.3 0.1 0.4

0.1 1.55 0.15

0.2 0.1 0.2 0.6

Timing Graph Required Time

0.3 0.1 0.4 0.1 0.2 0.15

1.4 0.55 1.25 0.1 0.1 0.15 0.1

setup time case

Slack = Required Time Arrival Time

Block-based vs. Path-based STA (1/2) Block-based Path-based

Block-based vs. Path-based STA (2/2) Block-based Path-based

Setup Timing Arcs

Hold Timing Arcs

Edge Arc Types

Preset and Clear Types

positive_preset / negative_preset positive_clear / negative_clear

These arcs are often disabled

Three State Arcs

Minimum Pulse Width Types

Timing Verification Items

Design Rule Checks

Clock Gating Checks

Enable CLK Setup Margin

Distorted Clock Waveform

Glitch due to late arrival time of Enable

Data Preparation for STA

Linear Cell Delay Model

delay time (ns)

Cell Delay = T0 + Ac * Cload

output capacitance load (pf)

Non-linear Cell Delay Model Non-linear

Dcell(I2) = f(Dtransition(I1), Ceq) Dtransistion(I2) = g(Dtransition(I1), Ceq)

Input Transition 0 0.123 0.222 0.5 0.234 0.432 1 0.456 0.801

index1: input transition Index2: output capacitance

Dc Vout Dtransition(I2) Req Ceq

Select the Correct Delay Table

Output transition direction depends on unateness

The worst case delay is selected

Consider the clock edge for sequential cells

Data Preparation for STA

Define Timing Constraints

Design optimization constraints

Define Clock Specification

Source latency Network latency Jitter Skew

All register-to-register path are constrained now

Clock Period & Waveform

network latency source latency (min_rise : max_rise : min_fall : max_fall)

Clock Uncertainty Definition

Arrival(P1) Arrival(P2) Arrival(P3) Arrival(P4)

0.5ns 1ns 1.2ns 1.3ns