PROGRAMMABLE FLASH MEMORY

Description

The AT89S52 is a low-power, high-performance CMOS 8-bit micro controller with 8K bytes of insystem programmable Flash memory. The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry- standard 80C51 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful micro controller that provides a highly flexible and cost-effective solution to many embedded control applications. The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.

PIN CONFIGURATION OF AT89C52

BLOCK DIAGRAM OF AT89C52

Pin Description OF AT89C52

VCC, Supply voltage. GND Ground.

Port 0
Port 0 is an 8-bit open drain bi directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 can also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.

Port 1

Port 1 is an 8-bit bi directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively. Port 1 also receives the low-order address bytes during Flash programming and verification.

Port 2

Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during

fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.

Port 3
Port 3 is an 8-bit bi directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 also serves the functions of various special features of the AT89S52.Port 3 also receives some control signals for Flash programming and verification.

RST

Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.

ALE/PROG
Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the micro controller is in external execution mode.

PSEN
Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.

EA/VPP External Access Enable

EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.

XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2
Output from the inverting oscillator amplifier.

2.5 Special Function Registers

A map of the on-chip memory area called the Special Function Register (SFR). Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect . User software should not write 1s to these Unlisted locations,since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.

Timer 2 Registers:
Control and status bits are contained in registers T2CON and T2MOD for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.

Interrupt Registers:
The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the sixinterrupt sources in the IP register.

Dual Data Pointer Registers:

To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.

Power Off Flag:

The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to 1 during power up. It can be set and rest under software control and is not affected by reset.

Watchdog Timer (One-time Enabled with Reset-out)

The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 13-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write01EH and 0E1H

in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running .The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.

Using the WDT

To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 13-bit counter overflows when it reaches 8191 (1FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 8191-machine cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 96xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.

WDT During Power-down and Idle

In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt, which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFRAUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the User should always set up a timer that will

periodically exit IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.

UART
The UART in the AT89S52 operates the same way as the UART in the AT89C51 and AT89C52.

Timer 0 and 1.1

Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52

Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON. Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON.Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.

Capture Mode
In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1- to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and

RCAP2L, respectively. In addition, the transition atT2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt.

Auto-reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 4). Upon reset, the DCEN Bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin. Timer 2 automatically counting up when DCEN=0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture Mode RCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled. Setting the DCEN bit enables Timer 2 to count up or down. In this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2count up. The timer will overflow at 0FFFFH and set theTF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored inRCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.

Baud Rate Generator

Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 2). Note that the baud rates for transmit and receive can be different if Timer2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into

its baud rate generator mode. The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2Hand RCAP2L, which are preset by software. Timer2s determines the baud rates in Modes 1 and 3 overflow rate according to the following equation .The Timer can be configured for either timer or Counter operation. In most applications, it is configured for timer operation (CP/T2 = 0). The timer operation is different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency). Where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. It is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an interrupt. Note too, that if EXEN2 is set, a 1-to-0transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus, when Timer2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt. Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors.

Interrupts
The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timers interrupts (Timers 0, 1, and 2), and the serial port interrupt. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. It shows that bit position IE.6 is unimplemented. Timer 2 interrupt is generated by the logical OR of bits TF2and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set atS5P2 of the cycle in

which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.

References

1. The 8051 Micro controller and Embedded Systems Using Assembly and C

- Muhammad Ali Mazidi, Janice Gillispie Mazidi and Rolin D.McKinlay.

2. Microcontroller AT89C52 Data Sheet. 3. Embedded Microcontrollers - Todd D. Morton

Block diagram of Latch:

Description: In this block diagram one port of the 89S52 is used to connect to the two latches Leds are connected to one latch 1 and Lcd is connected to latch 2.we have to connect more number of devices to the microcontroller. The microcontroller have less number of ports are there then we use the latch. The main advantage of the latch to use the multiplexed I/O lines means by using port 1 pins are connect to the one device in the same way port 1 pins are connected to the another device so we can drive the two devices at same port this is called multiplexed I/O lines. In latch 1 st pin is output enable (active low) depending upon this control the devices the output enable (OE) pin is connected vcc then corresponding device is drive and OE is connected to ground the corresponding drive is not working.

Schematic diagram of Latch

In this circuit use the AT 89S52, 74LS373, LEDs and LCD. Here port 1 is used to connect to the Latch (74LS373) and at same time connected to another latch. The 74LS373 latch 20 pin ic in which 8-data input lines and 8-data output lines. By using latches and maintain two devices to display the data. One latch displays the LCD data and another latch displays the Led blinking. In this circuit Co, C1 are used to which latch is displays the data. Suppose Leds are blinking that time C0 glows in the same way C1 glows Lcd displays the data.

74LS373
The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. The SN74LS374 is a high-speed, low-power Octal D-type Flip-Flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops. The SN74LS374 is manufactured using advanced Low Power Schottky technology and is compatible with all ON Semiconductor TTL families. Eight Latches in a Single Package 3-State Outputs for Bus Interfacing Hysteresis on Latch Enable Edge-Triggered D-Type Inputs Buffered Positive Edge-Triggered Clock Hysteresis on Clock Input to Improve Noise Margin Input Clamp Diodes Limit High Speed Termination Effects

D0-D7 Data Inputs LE Latch Enable (Active HIGH) Input

CP Clock (Active HIGH Going Edge) Input OE Output Enable (Active LOW) Input O0 O7 Outputs

LCD Module

An HD44780 Character LCD is an industry standard liquid crystal display (LCD) display device designed for interfacing with embedded systems. These screens come in common configurations of 8x1 characters, 16x2, and 20x4 among others. The largest such configuration is 40x4 characters, but these are rare and are actually two separate 20x4 screens seamlessly joined together. The low power supply (2.7 to 5.5v) of the hd44780. These screens are often found in copiers, fax machines, laser printers, industrial test equipment, networking equipment such as routers and storage devices, etc. These are not the kind of screens one would find in a cell phone, portable television, etc. They are limited to text only, with 8 customizable characters. Character LCD s can come with or without back lights. Back lights can be LED, fluorescent, or electro luminescent. Here we are used LM20400.The ability to display numbers, characters,and a few characters. Incorporation of a refreshing controller into the Lcd, thereby relieving the cpu of the task of refreshing the LCD.Ease of programming for characters and graphics. Character LCD s use a standard 16-pin interface. If the screen has a back light, it will have 16 pins. The pin outs are as follows:

Pin assignment
The pin assignment standard for character LCD-modules with a maximum of 80 characters and for character LCD-modules with more than 80 characters.

Table, Pin assignment for <= 80 character displays Pin number 1 2 3 4 Symbol Level I/O Function vs s V cc V ee RS 0/1 I Power supply (GND) Power supply (+5V) Contrast adjust 0 = Instruction input 1 = Data input 0 = Write to LCD module 1 = Read from LCD module Enable signal Data bus line 0 (LSB) Data bus line 1 Data bus line 2 Data bus line 3 Data bus line 4 Data bus line 5 Data bus line 6 Data bus line 7 (MSB)

5 6 7 8 9 10 11 12 13 14

R/W E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7

0/1 1, 1->0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1

I I I/O I/O I/O I/O I/O I/O I/O I/O

15 LED BL A - - Vcc 16 LED BL K - - GND

Character LCD s can operate in 4-bit or 8-bit mode. In 4 bit mode, pins 7 through 10 are unused and the entire byte is sent to the screen using pins 11 through 14 by sending a at a time.

LCD Command Codes

Code Command o LCD Instruction (Hex) Register 1 Clear display screen 2 Return home 4 Decrement cursor (shift cursor to left) 6 Increment cursor (shift cursor to right) 5 shift display Here we are used LM20400y right 7 shift display left 8 Display off, cursor off A Display off, cursor on C Display on, cursor off E Display on, cursor blinking F Display on, cursor blinking 10 Shift cursor position to left 14 Shift cursor position to right 18 Shift the entire display to the left 1C Shift the entire display to the right 80 Force cursor to beginning of 1st line C0 Force cursor to beginning of 2nd line 38 2 lines and 5*7 matrix 30 1 lines and 5*7 matrix

Lcd pin descriptions:

VCC, VSS, and VEE: While Vcc Vss provide +5v and ground, respectively; VEE is used for
controlling LCD contrast.

RS, register select:

There are two very important registers inside the LCD.The RS pin is used for their selection as follows. If RS=0,the instruction command code register is selected, allowing the user to send a command such as clear display, cursor at home, etc. If RS=1 the data register is selected, allowing the user to send data to be displayed on LCD.

R/W (read/write):
R/W input allows the user to write information to the LCD or read information from it.R/W=1 when reading; R/W=0 when writing.

E (enable):
The enable pin is used by the LCD to latch information presented to its data pins .When data is supplied to data pins, a high to low plus must be applied to this pin in order for the LCD to latch to the data present at the data pins. This pulse must be a minimum of 450 ns wide.

D0-D7:
The 8-bit data pins, D0-D7, are used to send information to the LCD or read the contents of the Lcd's internal registers. To display letters and numbers, we send ASCII codes for the letters A-Z,a-z and numbers 0-9 to these pins while making RS=1. There are also instruction command codes that can be sent to the LCD to clear the display or force the cursor to the home position or blink the cursor. We also use RS=0 to check the busy flag bit to see if the LCD is ready to receive the information. The busy flag is D7 and can be read when R/W=1 and RS=0,as follows: if R/W=1,RS=0.When D7=1(busy flag =1), the LCD is busy taking care of internal operations and will not accept any new information. When D7=0,the LCD is ready to receive new information.

Program:
#include<reg52.h> #include<intrins.h> sfr LCDDATA=0x90; sbit RS = P3^2; sbit E = P3^3; void delay(unsigned int); void LCDInstWrite(unsigned char); void LCDDataWrite (unsigned char); void Lcdcmd(unsigned char); void LcdInit(); void Delay(); sbit c0=P3^4; sbit c1=P3^5; unsigned char st[ ]= {'E','S','S','E','N','C','E'}; unsigned char st1[ ]= {'A','N','A','N','T','A','P','U','R'}; void main() { unsigned int i; while(1) { c0=1; c1=0; for(i=0;i<=0xff;i++) { P1=i; Delay(); } delay(5000); c0=0; c1=1; LcdInit(); //LCDDataWrite('R','M','A','N','A','T','H'); Lcdcmd(0x80); for(i=0;i<7;i++) { delay(250); LCDDataWrite(st[i]) ; } Lcdcmd(0xC0); for(i=0;i<9;i++) { delay(250); LCDDataWrite(st1[i]); } }//while }//main

/*************************************************************************************************** LCD INSTRUCTION WRITE ****************************************************************************************************/ void LCDInstWrite(unsigned char instruction) { RS = 0; E = 0; LCDDATA = instruction; E = 1; _nop_(); _nop_(); _nop_(); E = 0; delay(0xff); } /***************************************************************************************************** LCD INITIALISATION ******************************************************************************************************/ void LcdInit() { LCDInstWrite(0X30); delay(0xff); LCDInstWrite(0x30); delay(0xff); LCDInstWrite(0x30); delay(0xff); LCDInstWrite(0x38); LCDInstWrite(0x0C); LCDInstWrite(0x01); LCDInstWrite(0x06); // Auto increment cursor position }

/*************************************************************************************************** LCD CHARACTER DISPLAY ****************************************************************************************************/ void LCDDataWrite(unsigned char character) { RS = 0; E = 0; LCDDATA = character; E = 1; RS = 1; _nop_(); _nop_(); _nop_(); E = 0;

delay(0x1ff); } /**************************************************************************************************** Delay loop ****************************************************************************************************/ void delay(unsigned int itime) { while((itime--)!=0); } void Delay() { unsigned int z; for(z=0;z<=20000;z++); }

Keil Processing:

Step 1: Create New Project and write a program save with .C

Step 2: Right click on Source Group 1 and select add files to group Source Group

Step 3: Compile the program. Bottom of this screen shows the zero errors and zero warnings .

Step 4: Right click on Target select option for Target Target 1

Step 5: select the Target give the Clock frequency.

Step 6: Select the Output and click Create Hex file.

Step 7: Select Debug and click on Start debug.

Step 8: Click on Peripherals and Select the Ports.

Hex file:
:03000000020003F8 :0C000300787FE4F6D8FD75811902004AF0 :10015B000711455353454E43450908414E414E54F3 :04016B004150555258 :10008F00D2B4C2B5E4F518F519851990120193058C :10009F0019E51970020518D394FFE518940040E98B :1000AF007F887E13120188C2B4D2B51201197F80E6 :1000BF00120000E4F518F5197FFA7E00120188741A :1000CF00112519F8E6FF1201450519E5197002050A :1000DF0018C39407E518940040DE7FC0120000E4B7 :1000EF00F518F519C3E5199409E518940050917F97 :1000FF00FA7E0012018874082519F8E6FF120145EF :0A010F000519E51970DE051880DA05 :10017000C2B2C2B38F90D2B3000000C2B37FFF7E81 :0401800000020188F0 :100119007F301201701201847F3012017012018444 :100129007F301201701201847F381201707F0C1226 :0C01390001707F011201707F060201704E :10014500C2B2C2B38F90D2B3D2B2000000C2B37FA5 :06015500FF7E010201889B :040184007FFF7E007B :0B018800EF1FAC0670011E4C70F62249 :0E019300E4FFFE0FBF00010EBE4EF8BF21F5C7 :0101A100223B :10000F0002008FE493A3F8E493A34003F68001F278 :10001F0008DFF48029E493A3F85407240CC8C333F2 :10002F00C4540F4420C8834004F456800146F6DFC1 :10003F00E4800B010204081020408090015BE47EF5 :10004F00019360BCA3FF543F30E509541FFEE493B6 :10005F00A360010ECF54C025E060A840B8E493A37D :10006F00FAE493A3F8E493A3C8C582C8CAC583CAA8 :10007F00F0A3C8C582C8CAC583CADFE9DEE780BE60 :01016F00008F :00000001FF

SUPERPRO: This is Dumper we are generating the Hex file from the keil Software. This Hex file
is Dump into Atmel 89C52 IC Through SUPERPRO.