Digital Subscriber Line (xDSL)

xDSL Agenda

Introduction Benefits & Applications Market Dynamics Technology & Equipment Xilinx Solutions Summary

xDSL 2

Introduction

Broadband Access
High speed connection to the Internet

Greater than 128Kbps Always on! Simultaneous up-Link and down-link communication Overcomes Internet frustrations Made possible by digital modems

Leading broadband access technologies

xDSL, cable, satellite, ISDN digital modems

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xDSL Introduction
xDSL is the term for the Broadband Access technologies based on Digital Subscriber Line (DSL) technology
x signifies that there are various flavors of DSL

Provides always-on, high-speed data services over existing copper wires to residences & businesses
POTS service and DSL coexist on same copper line

Lower rate xDSL (up to 1.5 Mbps) is gaining popularity in the residential market; will get faster and cheaper High performance xDSL (up to 52 Mbps) targets business and high-end users
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Benefits & Applications

Benefits High-speed data service
DSL typically >10x faster than 56-kbps analog modem

Always on connection
No need to dial-up

Uses existing copper wires

Co-exists w/ POTS service

Reasonably priced today and getting cheaper

Applications High speed Internet access SOHO Multimedia, Long distance learning, gaming Video on Demand VPN VoDSL

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Speed Benefits

Average Download Times

Connection Speed 28.8 kbps 56 kbps ISDN (144 kbps)
DSL (1.5Mbps)

Web Page (30KBytes) 9 seconds 4.5 seconds 2 seconds <1 seconds

3 minute Music File (3MBytes) 15 minutes 7.5 minutes 3 minutes 15 seconds

30 second Video/Movie (50 MBytes) 4 hours 2 hours 55 minutes 5 minutes

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Market Dynamics

xDSL Market
Market Drivers

Increasing demand for high-speed internet Decreasing component costs Standardization for increased vendor interoperability Competition from alternate access technologies

Challenges
Speed, ease and cost of deployment Applications and new services Steep competition from other access technologies
Cable Modem, Satellite, Fixed Wireless and others
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Worldwide xDSL Equipment Market Forecast

12000 10000 2187 Revenue ($M) 8000 2084 6000 1954 4000 2000 0 2000 2001 2002 2003 2004 2005 2006 2007 1303 4096 5083 6182 7038 7800 8448 8730 1665 2036
Source: Frost & Sullivan, 12/2001

2096

1667

3519

Central Office Equipment

Customer Premises Equipment

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xDSL Technology & Equipment

DSL Overview

xDSL Modem (Internal or external)

Splitter (Voice & Data)

freq
xDSL 12

DSL Downstream

DSL Upstream

Voice

A - Rack of xDSL Line Cards B - Voice routed over PSTN C - Multiplexed Internet access

Asymmetric xDSL
Asymmetric => faster downstream rate vs. upstream
Suitable for applications such as web-browsing, MP3 downloading, Video on demand (VoD)

Types of asymmetric DSL

Asymmetric DSL (ADSL)
The original and most popular Other asymmetric DSL technologies derived from ADSL Universal ADSL (UDSL), a.k.a. G.Lite or DSL Lite Expedites and reduces cost of deployment process by moving the splitting process from the CP to the CO Splitter-less nature slows the bit rate considerably

xDSL 13

Asymmetric xDSL
Rate-Adaptive DSL (RADSL)
Detects highest possible line rate & adjusts accordingly

Very High Bit-rate DSL (VDSL)

Used to get high speed over short local loops Typically used in conjunction with Fiber to the Curb (FTTC) Still in development phase

xDSL 14

Symmetric xDSL
Symmetric => downstream & upstream rates are equal
Suitable for office type apps like Video conferencing

Types of symmetric xDSL

Symmetric DSL (SDSL)
Based on HDSL but single pair Spectral compatibility an issue (crosstalk & interference) High bit-rate DSL (HDSL) The first of the symmetric DSL technologies Uses multiple wire pairs (2 or 3) to achieve high bit rates

xDSL 15

Symmetric xDSL
HDSL 2
Single-pair version of HDSL More standards driven to improve interoperability and spectrally compatible with other loop services (ISDN, T1, HDSL) also takes into consideration diminishing amount of copper pairs Single-pair HDSL (SHDSL) Similar to HDSL 2, but more generalized Business class DSL for transporting T1/E1, ISDN, ATM, and IP

ISDN DSL (ISDL)

DSL over ISDN; okay to pass through repeaters & DLCs Always-on, flat rate billing, and transmit data over data network
xDSL 16

DSL Technologies
DSL Type
ADSL (Asymmetrical) UDSL( a.k.a. G.lite, DSL Lite) RADSL (Rate Adaptive) VDSL (Very High Bit Rate) IDSL (ISDN over DSL) SDSL (Symmetrical) HDSL (High Bit Rate) HDSL (High Bit Rate) HDSL2 SHDSL (Single-pair HDSL)

Download
1.5 - 8 Mbps 1.5 Mbps Variable to 7 Mbps 26 Mbps to 52 Mbps 144 kbps 144 kbps to 2 Mbps 1.544 Mbps 2.048 Mbps 1.544 Mbps 192 kbps to 2.312 Mbps

Upload
16 kbps to 640 kbps 384 kbps Variable to 640 kbps 3 Mbps to 6 Mbps 144 kbps 144 kbps to 2 Mbps 1.544 Mbps 2.048 Mbps 1.544 Mbps 3 Mbps to 6 Mbps

Distance (feet)
9K to 18K 12K to 18K 18K to 25K 1K to 3 K 18K (more w/ repeater) (more w/ repeater) 11.5K to 22K 12K on 2 pairs 12K on 3 pairs 12K on 1 pair 1K to 3 K

xDSL 17

ADSL Broadcast Solution

Satellite, cable or terrestrial Descrambler

Broadcast Translator PC Scrambler IP Router & ATM Switch DSLAM POTS Splitter ADSL Modem CPE

Set-top box, hard disk & TV

VoD Server & Software

Internet Proxy

Telephone Smart Card

ADSL Central Office

Home

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ADSL Equipment

Two groups of equipment

Central Office - DSL Access Multiplexer (DSLAM), Repeaters Customer Premise - DSL Modems, Gateways, Network Interface Card (NIC), splitters and filters
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DSLAM
DSLAM is usually found in a Central Office xDSL line cards are installed in a DSLAM to terminate incoming xDSL signals The DSLAM then combines multiple xDSL access lines into one high speed line The muxed traffic is converted into ATM cells which gets sent over an ATM backbone
Buffer & Switch Policing & Monitoring ATM PHY ATM backbone

xDS L Processing Card xDS L Line Card

xDS L Line Card

M U X

Processor

Memory

Memory

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Generic DSL Line Card for DSLAM Applications

Processor
SSTL-2/3 Translators

DSL Channels

DSL Driver /Receiver Chip(s)

HDLC Controller PCI

System Controller

Memory

PLLs/ Clock Management

Hot Swap Controllers

PCI Backplane Interface

GTL/GTL+ Transceivers

High Performance Backplane

xDSL 21

DSL Modem/Gateway
A xDSL modem is the device found at the customers premise which is used to transmit & receive xDSL signals Could be an external box or a network interface card placed inside a computer An xDSL Gateway combines the functionality of a modem and router

xDSL 22

DSL Modem Evolves to the Residential Gateway

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DSL CPE/Modem
Digital Signal Processor DSL Transceiver Equalizer, ReedSolomon FEC Encoder/Decoder, Interleaver, Modulator, Demodulator, Packet Format Logic Interface Memory Line Driver/ Receiver Line Driver, Receiver & Amplifiers Analog Front End A-to-D & D-to-A Converters, Filters, Amplifiers

To line & POTS splitter

HDLC Framer

System Controller

PCI Backplane Interface Clock Generator & DLLs

10/100 Base-TX Ethernet MAC USB Dev ice Controller USB Transceiv er

MII

10/100 Base-TX Transceiv er UTP

RJ-45

xDSL 24

DSL Modem Residential Gateway

HomePNA MII 10/100 Base-TX Transceiver 10/100 BaseTX Ethernet MAC

8 M Hz Oscillator
DRAM

UTOPIA or ISA Expansion Bus Interface

DRAM Controller

Clock Generator & DLLs 32-bit Processor Network Interface Block UTOPIA I/F or ATM

DSL Driver/ Receiver Chipset

PCI Bus Interface

8 KB Internal SRAM

Hasher List M anager

PCI
xDSL 25

DSL Modem Residential Gateway

HomePNA MII 10/100 Base-TX Transceiver 10/100 BaseTX Ethernet MAC

UTOPIA or ISA Expansion Bus Interface

DRAM

32-bit Processor

8 M Hz Oscillator UTOPIA I/F or ATM Network Interface Block

DRAM Controller

DSL Driver/ Receiver Chipset

PCI Bus Interface

8 KB Internal SRAM

Hasher List M anager

Clock Generator & DLLs

PCI

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Xilinx Solutions

The Spartan-3 Platform

A New Class of Spartan FPGAs

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Guaranteed Density Migration

Seamless migration across densities No expensive re-layout Position of VCC & GND remains the same Higher I/O count for higher density
200 K System Gates
FT256 package
5X Density Range

1 Million System Gates

VCC & GND User I/O

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Maximizing I/O Advantages

Delivering Minimum Die Size, Maximum I/Os
Die size reduced by 50% 130nm Conventional Conventional Process Migration Process Migration 30% of I/O capability lost Die size reduced by 50% 130nm Migration with Migration with Staggered Pads Staggered Pads I/O pads preserved with staggered pads
xDSL 30

90nm

Lowest Cost Parallel Interconnect Solutions

PCI 32/33 effective cost as low as $.38* Physical interfaces and system elements
24 I/O standards, DDR I/O registers, DCMs

Ideal for bridging functions

PCI 32/33 and 64/33

PCI 32-bit, 33 MHz as low as $.38*

Click here to learn more about the Xilinx Connectivity Solution

* Based on pricing for 2004, 250K units xDSL 31

Unrivaled Cost Points for High Performance DSP

Up to 330 billion MACs/sec
Spartan-3 device under $100* delivers up to 276B MACs/sec

Embedded DSP Capability

Up to 104 18bit Multipliers!

Simple and Familiar DSP Design Flow

18 Bit 36 Bit 18 Bit

Click here to learn more about the Xilinx DSP Solution

* Based on pricing for 2004, 250K units xDSL 32

MicroBlaze & Spartan-3 FPGAs

The Industrys Lowest Cost Soft Processor Solution

Effective cost as low as $0.73*

Complete solution includes HW, SW, tools and design examples: Embedded Design Kit (EDK) support

Click here to learn more about the Xilinx Processing Solution

* Based on pricing for 2004, 250K units xDSL 33

Configurable Logic Block (CLB)

Flexible Logic Building Blocks
4 slices per CLB
COUT COUT

2 SLICEM contain Memory 2 SLICEL are Logic only

SLICEL S3 X1Y1 SLICEL S2 X1Y0

Wide-input functions
16:1 multiplexer in 1 CLB 32:1 multiplexer in 2 CLBs, 1 level

Switch Matrix SLICEM S1 X0Y1 SHIFT SLICEM S0 X0Y0 CIN

Fast arithmetic functions

2 look-ahead carry chains per CLB column

Four 16-bit addressable shift registers

Cascadable

General routing via switch matrix

Plus fast direct routing
CIN

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Embedded Multipliers
High Performance 18-bit x 18-bit Multipliers
Flexibility
From 12 to 104 embedded multipliers 18 x 18 bit Signed or 17 x 17 bit Unsigned
18 Bit 36 Bit 18 Bit

operation 2s complement signed operation 4 to 18 bit operands Combinational & pipelined options

Enabling Real-time DSP Processing

Build up to 104 18 x 18 MACs Up to 26 complex 18 x 18 multiplies

High Performance DSP

1:1 association with block RAM

Click here to learn more on the Xilinx DSP Solution

xDSL 35

Embedded Memory
Maximizing Memory Bandwidth and Flexibility
DSP coefficients Scratch Pad Small FIFOs Wide/Shallow Cache tag memory Large FIFOs Packet buffers Video line buffers Deep/Wide
Spartan-3 True Dual-Port Block RAM

External

Distributed RAM Bytes Megabytes

Block RAM Kilobytes

High-speed memory interface Excellent for large memory requirements

xDSL 36

Port B

Port A

Block RAM
Multiple Configurations

Independent port A and B configuration Support for data width conversion including parity bits
Configuration 16K x 1 8K x 2 4K x 4 2K x 9 1K x 18 512 x 36 Depth 16Kb 8Kb 4Kb 2Kb 1Kb 512 Data bits 1 2 4 8 16 32 Parity bits 0 0 0 1 2 4

Configurations available on each port

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Distributed RAM
Flexible LUT Structure
64b 32b Dual Port RAM 1 CLB

Can be used as Logic, RAM, ROM, or shift register

1 CLB = 32bit Dual Port RAM configurations:16x1 1 CLB = 64bit Single Port RAM configurations:16x1, 32x1, 48x1 and 64x1 1 CLB = 64bit Shift Register

64b RAM16 SRL16 LUT

16b Single Port RAM 1 CLB

64b
16b

Cascadable with built-in CLB routing Shallow and wide memory enables fast access time Applications
Linear Feedback Shift Register, Schedule
multiplies, Small FIFO, Digital delay lines

Shift register
1 CLB

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System Clock Management

Eight global clocks
8 8

8 Clocks
8 8
xDSL 39

Available in all quadrant All global clocks will be

routable to any CLB

Four DCMs
Two on top & two on bottom

Inputs to DCM supplied from any global clock from same side of device

Digital Clock Manager (DCM)

DCM DCM

Clock phase de-skew 50% Duty cycle correction DLL performance

25Mhz to 325Mhz 100ps Jitter

Phase Shift

0, 90, 180, 270 CLK Period/256 m/n clock multiply & divide m= 2 to 32, n= 1 to 32

DCM

DCM

Temperature compensation
4 DCMs located at top and bottom of the Block RAM columns

xDSL 40

Digital Frequency Synthesizer

Digital Frequency Synthesizer
Period Calculator DFS Outputs
CLKIN
(for Reference)

CLKIN

CLKFX CLKFX180

e.g. M = 3, D=1

Synthesize any frequency within DFS operating range

Freq.CLKOUT = (M D) x Freq.CLKIN Where, M = 2 to 32 and D = 1 to 32

CLKFX and CLKFX180 (180 phase shift) outputs can be optionally phase aligned to CLK0 output of DLL Output frequency constant across temperature & voltage Outputs have 50/50 duty cycle guaranteed

xDSL 41

Digital Phase Shifter

Digital Phase Shifter
Delay chain
Positive Shift

CLKOUT (Any)
Negative Shift

CLKIN

Place clock edge anywhere within +/- clock period Amount of phase shift = (PS/256) x periodCLKIN Where, -255 < PS < +255 Fixed or variable modes Phase Shift amount constant across temperature & voltage Phase Shift affects all DCM outputs

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Comprehensive I/O Connectivity

B a n k 7 B a n k 6

Bank 0

Bank 1
B a n k 2 B a n k 3

Single ended and differential

784 single-ended, 344 differential pairs 622 Mb/sec LVDS 23 I/O standards, 8 flexible I/O banks PCI 32/33 and 64/33 support Eliminate costly bus transceivers Multiple package options

Bank 5

Bank 4

Voltages: 3.3V, 2.5V, 1.8V, 1.5V, 1.2V On Chip Digitally Controlled Impedance

8 I/O banks enable multiple simultaneous standards Chip-to-Chip Interfacing: Backplane Interfacing:

LVDS GTL

LVCMOS GTL+ PCI

LVTTL BLVDS

High-speed Memory Interfacing: HSTL SSTL

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Generic DSL Line Card

DS3134 CN8478

$10 - $120
DSL Channels

Bt8471/2 PSB2110 PM7380

$16 - $65
MPC107 GT64130

Processor
SSTL-2/3 Translators

DSL Driver /Receiver Chip(s)

HDLC Controller PCI

System Controller

$4

Memory
PCI9610 PCI9054 S5933 S5920 GT64115 GTL/GTL+ Transceivers

PLLs/ Clock Management

$3
Hot Swap Controllers

PCI Backplane Interface

$12 - $25

$3
High Performance Backplane

$6

xDSL 44

Generic DSL Line Card

Logic and Interface Savings By Using SpartanIIE FPGAs
Processor XC2S100E $8.85
DSL Channels
SSTL-2/3 Translators

DSL Driver /Receiver Chip(s)

HDLC Controller PCI

System Controller

Memory

PLLs/ Clock Management

Hot Swap Controllers

XC2S100E $8.85

PCI Backplane Interface

GTL/GTL+ Transceivers

High Performance Backplane

xDSL 45

IP Solution for HDLC

High Performance module for the HDLC protocol Support for up to 32 full duplex channels, total data rate >40Mb/s Low cost, fixed function netlist cores
Single-Channel Core: HDLC1 32-Channel HDLC Core: HDLC32 Optimized for Virtex, Virtex-E, Virtex-II, Spartan-II, Spartan-IIE

Licensed from Amphion Semiconductor Spartan-IIE + HDLC Controller IP = Programmable HDLC Controller Solution
xDSL 46

HDLC Core Features

Fully Compliant with ITU Q.921, X.25, ISO/IEC 3309, ISDN Channels B & D 8 or 16-bit address insertion and detection selectable Programmable 16 & 32-bit CRC (FCS) Both cores suited for multiple HDLC scaling Full duplex operation, with 32 channel multiplex capability T1/E1 stream support using External mux/de-mux Generic 8 bit host interface for control and status registers Fully synchronized with bit-rate

xDSL 47

HDLC Block Diagram

xDSL 48

LogiCORE PCI Block Diagram

xDSL 49