Recent Developments in Electrical Metrology for MOS Fabrication

Gate Engineering Channel Engineering Source-Drain Extension Engineering

George A. Brown SEMATECH Mark C. Benjamin Solid State Measurements,Inc.

Gate Engineering
George A. Brown SEMATECH

Introduction Gate Dielectrics

Brief Roadmap Review Traditional Gate Dielectric Electrical Metrology Measurements, analysis, and limitations Improved Methods and Recent Developments Critical C-V measurement parameters High frequency Low series resistance test structures Adequate area resolution UHFCAP structure Multi-frequency C-V, D- characteristics Interface State (Dit) Measurement: charge pumping In-line C-V Measurements

Summary

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ITRS Roadmap for High Performance Gate Dielectrics (2004 update)

1.E+05 14 13

EOT
1.E+04

Jg,simulated (oxynitride) Jg,limit

12 11 10 9 8

Jg (A/cm2)

EOT (A)

1.E+03

7 6 5 4 3 2 1 0 2005 2007 2009 2011 2013 2015 2017

1.E+02

Beyond this point of cross over, oxynitride is incapable of meeting the limit (Jg,limit) on gate leakage current density

1.E+01 2003

Calendar Year

Scaling beyond 1 nm, 103 A/cm2 is almost upon us!

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Evolution of gate dielectric electrical metrology

Parameter

Traditional Measurement Technique 100 kHz/1 MHz MOS C-V 100 kHz/1 MHz MOS C-V Quasi-static C-V MOS C-V Hysteresis

Traditional Analysis Technique Classical Poisson's Law Models Classical Poisson's Law Models Classical Poisson's Law Models Vfb

Shortcomings for Advanced Devices

Improved Measurement Technique

Improved Analysis Technique

Oxide thickness, CET Oxide thickness, EOT Interface State Density, Dit Oxide Charge Tgrapping

Low-Rs test C-V distortion from high structures, UHF gate leakage C-V Failure to account for quantum confinement, poly depletion

Multi-element equivalent circuits Schrodinger solvers for EOT

Pulse level, rise time Gate leakage Charge pumping to separate bulk dominates quasi-static Brew's Dit trapping from Dit data inaccurate, poorly defined for high-k Pulsed transient Id-Vg Pulse rise time analysis

New methodologies must be developed to deal with the characteristics of radically scaled gate dielectric stacks.
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Measurement of 0.5 nm EOT Gate Stacks with High Leakage

High leakage gate stacks are modeled as parallel

RC equivalent circuits.
To resolve the capacitance, use of higher

Gp

Cp

frequencies will reduce the capacitive impedance, making that element dominate the parallel resistance/conductance.
But this only works if there is negligible parasitic

Q = Cp/Gp

series resistance in the test structure. Use of higher frequencies if series resistance is present only makes the capacitive impedance of interest negligible in comparison with Rs.

Gp

Cp

Rs

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Requirements for EOT Measurement of High Leakage Gate Stacks

1. Capacitor test structure design with minimum series

resistance. Topside electrical contact to the capacitor substrate is required to eliminate the wafer chuck from the measurement circuit.
2. Use of measurement frequencies high enough to reduce the

effect of the parallel conductance of the gate stack. Dissipation factor must be reduced sufficiently to permit accurate measurements.
3. Geometric resolution of the test structure effective area must

be adequate to assure accurate and precise definition of EOT.

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1-Port Philips UHF MOSCAP Design

active

poly

Designed for low series resistance Uses 3-point (G-S-G) UHF probe head 720 - 1.0x2.6 m capacitor elements Right and left ground pads connect p-well to S/D.
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Multi-Frequency MIS C-V Measurements on the Philips UHF MOSCAP 2 nm SiO2 TiN gate electrode
2.0E-11

UHF Capacitor Test Structure: High Frequency C-V Performance 3.5E-11 3.0E-11 Lot-wafer 3052109-18: 40 cycles HfO2; HF-NH3 preclean 2

0.7 nm EOT HfO poly gate

Effective Area = fit = 8.74x10cm2 2 A(eff) for EOT 8.7x10-6 -6 cm

Capacitance [F]

1.5E-11

1.0E-11

5.0E-12

100KHz 1MHz 4MHz 10MHz 20MHz 50MHz 100MHz

-2 -1 0 1
3090511-01

2.5E-11 Capacitance [F] 2.0E-11 1.5E-11 1.0E-11

2

0.0E+00

CVC Model Parameters EOT = 7.35 Nsurf = 9.7E17 /cc Vfb = -0.252 V RMS fit error = +/-0.8%

5.0E-12 0.0E+00 -2 -1.5 -1 -0.5 0 0.5 Gate Voltage [V] 1

Voltage [V]

f = 100 kHz f = 1 MHz f = 2 MHz f = 5 MHz f = 10 MHz f = 20 MHz f = 50 MHz f = 100 MHz CVC model 1.5 2

Measurement: Agilent 4294A Precision Impedance Analyzer IV Probe mode

Frequency-invariant C-V data can be obtained in wafer form on 2 nm SiO2 films with properly designed test structures. Some frequency dispersion is seen on more highly scaled high-k devices.

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Three-element Equivalent Circuit Parameter Analysis from Dissipation Factor-Frequency Characteristics

Dissipation Factor vs. Frequency Plot Lot-wafer 3073102-07: STI HfSiO

10

EOT = 17.2
Dissipation Factor at -2V
Ro = 1.4E4 ohms

Extraction of Ro, Rs from D- Plots

For low frequencies, D ~ 1/f:
Go (1 + R G ) R 1 1 D = D-f datas o = (1 + s ) C o Ro C o Ro Ro C o

In the high frequency limit, D ~ f:

D = 1/RoCo
0.1

D = RsCo

D = Rs C o
Rs = 18.4 ohms

Go= 1/Ro
0.01 1.0E+05

Co

1.0E+06

1.0E+07

1.0E+08

Rs

Frequency [Hz]
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10

Dit: Comparison of Charge Pumping Techniques

Fixed Base, Variable Amplitude Charge Pumping (into accumulation)
10
12

3.5 nm HfSiO polySi TH75-2072317/ #08

nFET W/L=10/1m

Fixed Base, Variable Amplitude Charge Pumping (into inversion) These techniques provide alternative ways to characterize traps and trapping processes in high-k films. Information on energy and depth distribution of the traps may be obtained from these curves.

Vbase = 1.0V

Vbase = -1.0V

Nit [#/cycle*cm ]

10

11

10

10

Vpeak = 1.2V
1MHz Nit 100kHz Nit 10kHz Nit

10 -2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

Fixed Amplitude, Variable Base Charge Pumping

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Vbase [V] or Vpeak [V]

11

EM-probe Description
Interface Layer associated with tip contact ~10 to 20

200um

Tip Shaft

Stray capacitance compensated via software

~300 um

~35 um

Small contact area provides superior performance for ultra-thin dielectrics

Slide 050309002 2005 Solid State Measurements, Inc. ALL RIGHTS RESERVED

AFM Indicates No Surface Damage

12

In-line Measurement of CET/EOT with EM-probe

335 30 25 EM-gate CET(Ang.) y = 1.388x - 3.3638 R 2 = 0.9898

20 15 10 Oxynitride Thermal Oxide Oxynitride

5 0 0 5 10 15 nMOS EOT (A)

20

25

Device-correlatable CET/EOT measurements can be made in-line for real-time process control down to ~1 nm.
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Channel Engineering SDE Engineering

Mark C. Benjamin Solid State Measurements, Inc.

Relationship Between Dose and NSURF

NSURF = Average Dopant Density within WEQ

NSURF

N V

WEQ

WMAX

Equilibrium Dose = EQD = N(w)dw from the surface to WEQ = NSURFWEQ = SQRT(2kSSL,INVNSURF/q)
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15

EM-gate Equilibrium CV Comparison

SSM-6100 EM-probe CV versus Implant Dose
6 5 4

Slot 1 1E11 cm-2

Slot 3 2E11 cm-2

Slot 5 5E11 cm-2

C(pF)

3 2 1 0 -3 -1 1 3 5

Slot 7 1E12 cm-2

Slot 9 1E13 cm-2

Slot 11 5E13 cm-2

Slot 13 8E13 cm-2

Slot 15 1E14 cm-2

Vg(V)
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2005 Solid State Measurements, Inc. ALL RIGHTS RESERVED

16

Sensitivity: Nsurf versus Implant Dose

SSM-6100 Nsurf Sensitivity Comparison
1.00E+19

1.00E+18

Nsurf(cm-3)

1.00E+17

1.00E+16

1.00E+15 1.00E+11

1.00E+12

1.00E+13

1.00E+14

Implant Dose (cm-2)

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2005 Solid State Measurements, Inc. ALL RIGHTS RESERVED

17

Major Device and Materials Issues with USJ S/D Structures

Goal: Increase Electrically Active N

and Decrease W Ideal BOX Profile!! NMAX

Sheet Resistance (RS) Surface Carrier Density

Ideal

(NSURF)

Junction Depth (XJ)

N
EOR Defects

Carrier Density Profile

Shape

Actual XJ

Junction Leakage
Sensitive to Implant EOR Damage

W
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18

4pp: Conventional vs EM-Probe

Conventional Four Point Probe s I Force I USL 3 4 d

EMEM-probe Four Point Probe Force s I 1 2 I USL 3 4 d

V 1 2

Semiconductor Substrate Sheet Resistance = R S = CF(V/I)

Semiconductor Substrate Sheet Resistance = R S = CF(V/I)

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2005 Solid State Measurements, Inc. ALL RIGHTS RESERVED

19

EM-probe Description
Interface Layer associated with tip contact ~10 to 20

200um

Tip Shaft

Stray capacitance compensated via software

~300 um

~35 um

Small contact area provides superior performance for ultra-thin dielectrics

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AFM Indicates No Surface Damage

20

EM-Probe CV and IV: Non-penetrating EM-Probe CV and IV is used extensively to measure dielectrics

with thicknesses less than 1 nm.

40

EM-gate Short Term Repeatability Test 8 Angstrom SiON Wafer

Mean = 9.83 Ang. Sigma = 0.051 Ang.

EM-gate IV: Thin Oxides

Stepped Voltage IV, Step Delay = 1000 msec
10-3 10-4 10-5 10-6 10-7
TOX = 30 Ang.

90 Ang. (Slot 7) 30 Ang. (Slot 24) 10 Ang. (Slot 25)

~ 4 to 5 Orders of Magnitude Difference

TOX = 10 Ang.

30

C (pF)

I(A)

20

10-8 10-9 10-10

10

10-11 10-12 10-13

TOX = 90 Ang.

0 -1.8

-1.6

-1.4

-1.2

-1.0

-0.8

-0.6

-0.4

-0.2

10-14 -12

-10

-8

-6

-4

-2

Gate Voltage (V)

Vg(V)

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2005 Solid State Measurements, Inc. ALL RIGHTS RESERVED

21

Basic Principle of Four Point Probe (4pp) Method for RS

IA

2
+ +

VM

Voltmeter: Requires High ZIN, low Input Offset Current

P-type

Semi-Infinite Slab t

Resistivity = = [qp]-1 = RArea/l Resistance = VM/IA

Irvins Curves

Sheet Resistance = /t = CF(VM/IA); = [q N(x)dx]-1

For Probes located far from Edge of Circular Sample, CF = 4.532

xJ W

Defined Structure RS = (V/I)/(L/W) , Units /Square

To eliminate Contact Resistance, Kelvin or Transmission Line(TLM) Structures are Used

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Conventional versus EM-Probe 4pp RS Case 1: P+ USJ Structures

100000

Conventional 4pp EM-gate 4pp

16 nm 28 nm
10000

15 nm

Rs(Ohms/square)

1000

45 nm

45 nm

45 nm

100

Rs vs xj Comparison
Ratio(Method/EM-Probe)
1.2 1 0.8 0.6 0.4 0.2
Conventional 4pp VPS
Hg Probe 4pp

10

#1-1

#1-2

#1-3 0
0 200

#1-4
400 xj (Ang.) 600

#1-5

#1-6

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2005 Solid State Measurements, Inc. ALL RIGHTS RESERVED

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RS NSURF Correlation: General Considerations

Correlation Depends on Activation and xJ
Good Rs Nsurf Correlation
Nsurf Increasing; Higher Activation

Poor Rs Nsurf Correlation

Nsurf ~ Constant

Xj increasing Xj ~ Constant, Diffusionless

W
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W
24

Summary Gate Engineering requires new measurement and analysis

techniques Channel engineering requires new measurement techniques for inline metrology
Equilibrium Nsurf extends usefulness

Source-Drain Extensions (USJ) require new measurement

techniques
Junction leakage requires thought -> Nsurf ?

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2005 Solid State Measurements, Inc. ALL RIGHTS RESERVED

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