2010 23rd International Conference on VLSI Design

An improvised MOS transistor model suitable for Geometric Program based analog circuit sizing in sub-micron technology
Samiran DasGupta
Department of Electronics and Electrical Communication Engineering Indian Institute of Technology Kharagpur 721 302 India Email: samiran 4393@yahoo.co.in

Pradip Mandal
Department of Electronics and Electrical Communication Engineering Indian Institute of Technology Kharagpur 721 302 India Email: pradip@ece.iitkgp.ernet.in

AbstractThis paper presents ways to improve accuracy of performance prediction for geometric program based analog design in submicron regime. Geometric program requires a special monomial form of the device model it uses. The major sources of inaccuracy in this basic model have been identied and it has been shown that slightly relaxing the strict monomial form in order to include second order effects can greatly improve the accuracy. In order to make use of this model we deploy it in collaboration with an iterative solution betterment scheme, by solving the sizing problem as a sequence of geometric programs instead of a single one. We illustrate the efcacy of our scheme through a folded-cascode op-amp sizing example.

I. I NTRODUCTION Analog circuit sizing refers to determining the device sizes and biases of a given circuit so that they satisfy the laid down specications. Automated analog circuit sizing has been an active research area for quite some time and a number of approaches have been proposed over the years. While each of these techniques have their own pros and cons, one approach has been receiving considerable attention of recent. The technique known as geometric programming for automated analog sizing offers some of the most desirable properties of a sizing engine speed, global optima and no user intervention. Owing to these merits the method has found growing popularity and has been applied to size op-amps, PLL, ADC among other circuits. However an important limitation in these former applications is that they have all been done in micron-meter technologies. This is important as geometric program based analog sizing relies on special monomial transistor models (as we shall see shortly). The model used in prior works is expected to run into accuracy problems when used for short channel transistors, thus restricting its usage only in micronmeter technologies. In this paper we describe a scheme to improve the accuracy of prediction in GP based analog sizing. Inspection of the submicron MOS behavior reveals, that for short channel transistors, the drain to source voltage Vds has a signicant inuence on the transconductance gm and the drain to
1063-9667/10 $26.00 2010 IEEE DOI 10.1109/VLSI.Design.2010.31 294

source conductance gd , an effect which had not been properly accounted for in the model used in prior GP applications. The difculty is that GP requires a special functional form of the transistor model in order to be applicable; and it becomes difcult to maintain such a form if the Vds effect is to be included. In this paper we show a simple procedure that can used to include the Vds correction. We also show another way that can help increase the accuracy further the use of piecewise monomial approximation instead of global monomial approximation. We illustrate the efcacy of our scheme through a folded cascode op-amp sizing example in an industry standard 0.18 m CMOS process. The rest of the paper is organized as follows. In Section II we briey cover the background material and other proposed approaches of accuracy improvement. Section III and IV form the main body of the paper where we describe our approach to increase accuracy. We present experimental results in Section V and nally conclude in Section VI. II. BACKGROUND C ONCEPTS AND R ELATED W ORK A. The geometric programming problem A geometric programming problem has the following form minimize f0 (x) subject to gi (x) 1 ci (x) = 1 and xj > 0 where the objective function f0 (x) and each of the inequality constraint functions gi (x) are posynomials of the design variables xj s; and the equality constraint functions ci (x) are monomials of the same. In equation form a monomial function is f (x) = Cxa1 xa2 xa3 ...xan (2) n 1 2 3 where C is a positive constant, ai R and x1 , x2 , x3 ...xn are n real positive variables.f (x) is said to be a monomial (of variables x1 , x2 , x3 ...xn ). A posynomial function is a (1)

(a) Variation of gd with drain voltage

Fig. 1: Folded cascode op-amp topology

(b) Variation of gm with drain voltage

summation of one or more monomial terms. For a more thorough elucidation the reader is referred to [9]. B. The op-amp sizing problem formulated as a GP We will briey try to explain how the op-amp sizing problem can be formulated as a GP, with the circuit in Fig. 1 as the running example. The goal is determine the values of the design variables (the transistor sizes and the bias reference Iref ) that would satisfy all the performance specications while optimizing some cost such as power. Toward that the sizing problem is formulated as a constrained optimization problem, the various constraints apart from satisfying the performance specications also ensure that all transistors are in saturation, the circuit is stable, etc. While the detailed GP formulation of the folded cascode topology may be found in [3], here for illustartive purposes we will only show the gain and unity gain frequency constraints. The gain constraint is shown in (3) where the subscripts refer to the numbering in Fig. 1. Gainspec gd 1 gd 6 gd 4 gd 6 gd 8 gd 10 + + gm 1 gm 6 gm 1 gm 6 gm 1 gm 8 CL 1 gm 1 1 (3)

Fig. 2: The effect of Vds on gd , gm for a 1.32 m/ 0.42 m pmos transistor at Vgs = 450 mV ; on National Semiconductors 0.18m CMOS process

monomial functions of Wi , Li and ID i 1 , then each of the constraints becomes a sum of monomials i.e. a posynomial function of the design variables W , L and ID ; in other words a legal GP constraint as dened in (1). Equation (5) below shows a monomial model of gm and gd which is similar to the widely used model in prior GP applications [5], [3]. Please note that all models shown in this paper are for the saturation region of operation.
a gd = k1 ID1 Lb1 C c1 a gm = k2 ID2 Lb2 W c2

where k3 , a3 , b3 etc. are contants extracted through curve tting with SPICE simulations for a particular process.

(5)

The unity gain frequency constraint can be approximated as U GFspec (4)

where, Gainspec and U GFspec are the gain and unity gain frequency specications respectively. The variables of the optimization problem are the W s, Ls of the various transistors and the bias current Iref . The objective fuction may be taken as area, power, UGF or any of the other performance metrics. C. GP compatible Transistor Models In each of the constraints (3) and (4) we can see that the expression is a sum of fractions where every fraction has a product of gm i and gd i divided by a product of gm i and gd i form. For the other constraints too the same trend can be shown to hold good [3],[5]. Thus, if gm i and gd i were
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The problem with the above model is that although it works well for long channel transistors, it runs into serious accuracy problems when used for short channel devices. For instance when we used it to estimated gm and gd over a large number of samples for a 0.34 m channel length device in our 0.18 m process, we encountered an average error in gd of about 65% . An approach to improve the accuracy that was proposed in [1],[2] is to use posynomial functions to model gm and gd instead of monomial functions. If we look at constraints (3) and (4) we can see that the numerator in each term are occupied by the gd i s while the gm i s sit in the denominator. Thus if gd i and g1 i could be modeled as posynomial functions m then each term in equation (3) becomes a posynomial2 . The use of a posynomial function which is a sum of several monomial functions decidedly improves the accuracy of t over the case of a single monomial function approximation. However, there are two primary limitations to the approach.
1I 2a Di

is the drain current of the ith transistor posynomial a posynomial is also a posynomial.

1) It restricts the scope of application of the method in the sense that it cannot include constraints where a gd i appears in the denominator or a gm i comes in the numerator.3 2) The second difculty is that there is no easy technique available for curve tting data to posynomial functions. In [1] piecewise convex approximation has been used for posynomial tting while [2] uses genetic algorithm. For monomial functions on the other hand the task can be done using highly efcient linear regression. We have improvised a fairly straightforward yet effective scheme for improving accuracy which we describe in the following Section. III. GP MODEL : A N IMPROVISED MODEL FOR gm AND gd IN
THE SUBMICRON REGIME

corresponding to different W,L and Is, then for each curve we will get a gdnorm and gd . If we can model gdnorm and gd separately then we can estimate total gd as
gd = gdnorm gd gd

(6)

The will exhibit the primary monomial dependence on ID and L roughly following the trend predicted by rst order D physics gd IL . We have modeled it using the expression
a3 gd = kgd ID Lb3 W c3 where kg , a3 , b3 , c3 are constants extracted through tting with SPICE data
d

(7)

Note that, we have added an additional W dependence to help improve the accuracy further. The power of the W is small typically about 0.2 on our process. gdnorm was captured using the emperical expression gdnorm = p + q.Vds + r.es(Vds t)
where p, q, r, s and t are constants of tting

In order to improve the accuracy, let us rst identify the main sources of error in the simple monomial model of (5). First, apart from the W ,L,ID dependence, the drain to source voltage Vds too has a signicant inuence on gm and gd (especially for short channel length transistors), an effect which has not been adequately accounted for in (5). Second, even if we ignore the effect Vds , the dependence on W ,L and ID itself are not accurately modeled by the monomial equation (5). Toward that, we have reduced the error in gm and gd two ways: by incorporating an accurate model to account for the inuence of Vds by using piecewise monomial t instead of global monomial t. The ideas are explained below in detail. The Vds variation: In order to appreciate the inuence of Vds on gm and gd let us inspect the curves shown in Fig. 2. These curves show the variation of gd and gm vs. Vds in the saturation region of operation. We can see that the gd changes by approximately 4 times as Vds varies from VDsat to 1.8 V . If ignored this can cause a worst case error of 400%. This explains the large errors we encountered for gd . Please note however, that the monomial dependence of gd on ID and L shown in (5) is much more dominant than the Vds effect (in the saturation region of operation). For instance the ID can vary from A to mA and this will cause gd to change by the order of 103 whereas Vds can make it vary by only about 3 to 4 times. Thus we may well say that the variation of gd has two parts a primary dependency on ID and L and a secondary dependence on Vds . Our plan is to decouple these two parts to improvise a model which uses monomial expression to capture the primary ID and L dependency while using nonmonomial expressions to model the Vds effect. An easy way to do so is illustrated in Fig. 2. On the gd vs. Vds curve, we identify the minimum value of gd (shown highlighted in Fig. 2a). We term it gd . Now, we normalize the gd vs. Vds curve w.r.t. this gd . Let us call the normalized curve gdnorm . Now, if we record a family of gd vs. Vds curves
3 The

(8)

Now, the shape of the gdnorm curve also changes with the gate overdrive voltage Vov and the channel length L; we included these dependencies by approximating p, q, r, s and t as second order polynomial functions Vov and L. The same approach has been followed for gm . gm = gmnorm gm |Vds =0.8 The only difference is that instead of the minimum value we have used the value at Vds = 0.8V (shown highlighted in Fig. 2b) on the gm vs. Vds curve to normalize it. This because unlike gd vs. Vds curve, the gm vs. Vds curve has its minimum in the triode region and as we are interested to model the saturation region of operation only, it is not appropriate to normalize the curves using their minimum values. gm |Vds =0.8 is a monomial just like (7) while gmnorm has been captured by the emperical expression gmnorm = 1 + gm Vds 1 + gm 0.8
gm is a const. of tting.

difculty arises as

1 posynomial

is not a posynomial .

It is the rst order monomial form of the above model that is the important property utilized in the GP formulation. The second order nonmonmiality is introduced to improve the accuracy and as long as it is less dominant in comparison to the rst order behavior it will not affect our GP based sizing scheme. In Section IV we describe a method to handle second order nonmonomiality while doing sizing. Piecewise monomial t: In order to increase the accuracy further, instead of global monomial approximation we have used piecewise monomial approximation by splitting the gate overdrive voltage into ranges and tting local monomial mod els for gd and gm |Vds =0.8 in each of these ranges. The template of the models remains xed and same as (7). The coefcient and the powers vary depending on the gate overdrive voltage range the device is in. The overdrive voltage has been split into 3 regions Vov = 100 200mV , Vov = 200 350mV and Vov = 350 900mV . Figure 3 shows the various piecewise monomial approximations for the pmos transistor in

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evaluated to their numerical values which are incorporated into the coefcient of a simple monomial model used by the GP. Thus, the GP always works with a pure monomial function whose coefecient gets updated according to the values of gdnorm and gmnorm for that iteration. The owchart in Figure 5 shows the formulation of the sizing problem as a sequence of geometric programs. The iterative scheme is similar to the one described in [4] from where we have borrowed it. The various steps are explained below briey.
Fig. 3: Piecewise monomial models for the pmos transistor in various overdrive voltage ranges

(a) global monomial approximation (b) piecewise monomial approximation

Fig. 4: Comparison of percentage error with SPECTRE in gd estimation of the pmos transistor plotted for 350 samples.

the different overdrive voltage ranges. A comparison between the accuracies of global and local approximation is given in Figure 4. These gures show the percentage error of gd with CADENCE SPECTRE simulations for the pmos transistor plotted for 350 samples spread out uniformly on the W, L, I sample space. It can be seen that piecewise monomial model improves the worst case error from 40% to 6% over the global monomial one. Accuracy Comparison: Table I below shows a comparison of performance prediction attained by our GPmodel with prior work [1]. It can be seen that although the error in gm is slightly more, the case for gd has been signicantly improved. It must be noted that our models are not posynomial approximations as [1] and hence have greater scope of application. TABLE I: Max/mean % error comprison: for nmos device
gm gd simple mono model 33.3/17.1 169.3/64.3 [1] 5.4/1.7 39.8/9.4 this work 7.2/3.4 25.3/6.7

Fig. 5: Formulation of the sizing problem as a sequence of geometric programs

1) The rst step is to input the specications for the design. An initial guess of the model parameters is also required in the rst step which includes gdnorm and gmnorm the monomial model constants such as kg ,a3 , b3 , c3 d etc. 2) Once the model parameters are given, using them the coefcients and powers of a pure monomial model(9) are evaluated. The model has been repeated here for convenience.
a gd = k3 ID3 Lb3 C c3 a gm = k4 ID4 Lb4 W c4

(9)

IV. A N ITERATIVE APPROACH TO HANDLE SECOND ORDER

NONMONOMIALITY

In the GPmodel discussed in the previous Section the forms of gdnorm and gmnorm are not monomials. The geometric program sizing formulation however requires exclusive monomial form as shown in Section II-C. In order to address this the sizing has been done using a sequence of GPs instead of a single one. At each iteration the gdnorm and gmnorm are

This means that the constants k3 , a3 , b3 , c3 etc. will be found using the parameters from the previous step e.g. k3 = gdnorm kgd . 3) Using this monomial model the geometric program is solved. It will return a sized netlist i.e. the W s and Ls of the various transistors along with the reference biasing current Iref . 4) Given Iref and the W s and Ls of all the transistors the ensuing dc bias condition of the circuit can be determined. We have deployed a method known as

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relaxed dc analysis[4] for the purpose. This method is explained in the next Section. Thus, at the end of this step, we get the values for all the dc node voltages. Using them we can obtain the drain to source voltage Vds and the overdrive voltage Vov of the various transistors. 5) The drain to source voltage Vds of each transistor is used to evaluate gdnorm and gmnorm . By noting the Vov we decide which overdrive voltage range the transistor is falling into and accordingly select the coefcient and powers of the monomial models for gd and gm |Vds =0.8 . 6) The nal step involves a conditions check block. There can be a variety of criteria that might be used to terminate the iteration. We have chosen to monitor the various performance metrics such as gain, UGF etc. When these values settle within acceptable tolerance with the corresponding values from the previous iteration, the program steps out of loop, to return the nal sized netlist. A. Relaxed DC Analysis In the owchart of Fig. 5 we needed to nd the dc operating condition of the circuit in step 3. Here we describe how, using a method called relxed dc analysis we nd the dc operating point. The technique has been borrowed from [4] where it can be found in greater detail. The method takes Iref and the various W s and Ls as input and gives the dc quiescent point (i.e. the various node voltages and branch currents) as the output. The approach relies on two observations. Most analog circuits use current mirrors for biasing. An important implication of this is that all branch currents of the circuit can be found out from the few basic refernce currents (e.g. in the op-amp circuit in Fig. 1 there is only one Iref . The currents of all the other branches can be determined if we know it). The voltages of all the nodes are dened by the gate to source voltage VGS (the source to gate voltage for pmos tranistors) of the various transistors. The approach thus is to rst nd the currents of all the branches using the reference currents and the W/L ratios. Once the current is known the overdrive voltage and hence the VGS of each transistor can be determined using its aspect ratio. After this, we express all node voltages in terms of the VGS s of the various transistors and thus nd them out. The technique is illustrated below with the running example of a simple miller op-amp circuit shown in Fig. 6. The rst task is to nd the various branch currents. 5 I5 = Iref 0 I1 = I2 =I3 = I4 = I5 /2 6 I6 = I7 = I3 3 The subscripts above refer to transistor numbers. is the acronym used for the aspect ratio W/L. Once ID is known, the VGS of each transistor has to be found from it. We have used the power model shown in

Fig. 6: Simple miller op-amp

(10) for this. ID = k (VGS VT )

4

(10)

We extracted k , VT and using SPICE data for our CMOS process. We noted that when (10) was used to estimate ID with VGS as input, there was an average error of 20-25% (all errors are w.r.t. CADENCE SPECTRE). However the high error is not a concern as we need to estimate VGS with ID as input (not ID from VGS ). With a value of about 1.7 the error in Vov gets reduced to 251/1.7 6%. Thus, once we have the ID s we can get the VGS s within 10% accuracy, which is sufcient for our purposes. Finally the node voltages are expressed in terms of the gate to source voltage of the various transistors. V0 =VGS 0 V1 =Vin VGS 1 V3 =V2 = Vdd VSG 3 V. EXPERIMENTAL RESULTS We made MATLAB implementations of the geometric program formulation for the folded cascode topology shown in Fig. 1 and also for a two stage cascode op-amp topology using our improvised GPmodel and used them to size opamps for varied specications. The minimum channel length used was 0.34 m. Owing to limitation of space we have included only the folded cascode example which is shown in Table II. It shows a comparison of performance estimation between GPmodel and the simple monomial model(5) The last two columns indicate percentage error of each model w.r.t. SPECTRE. We can see that the gain error has been reduced from 79% to 4.3% while the UGF error could be improved from 23% to about 2%. In order to check how well our GPmodel works in collaboration with the iterative betterment scheme of Fig. 5 we monitored the convergence statistics of the loop; the results are shown in Table III. At every iteration the value of each performance is compared with that from the previous iteration and the percentage discrepency is calculated. The maximum among all the discrepencies was used as the metric to stop the iteration. When the max. discrepency dropped below 1% the
4V T was modeled as a quadratic t of body bias and L. This results in very small errors in VT within 3% in our process.

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TABLE II: Error comparison in performance estimation for the folded cascode opamp design
Attained Performance (unit) Gain(ratio) Gain(dB) UGF(MHz) BW(KHz) PM(degrees) Spec. GP model 1000 60 50 50 86.44 simple mon. model 1868 65.43 60.5 34.55 86 Spectre 1046 60.39 49.14 49.35 79 Error(%) w.r.t. Spectre (in magnitude) GP simple mod. mon. 4.3 0.64 1.75 1.32 9.41 78.9 8.34 23.11 30.09 8.86

1000 60 50 60

For the same set of specications, we sized 6 different designs starting from the six different initial guesses. These designs were compared to check the discrepencies between them as is shown in Table V. The nomanclature followed is Des.x is the design corresponding to initial guess In.x The percentage discrepency(in magnitude) among the L, W and node voltages of the corresponding transistors in the designs were compared and the highest among them are reported in Table V. TABLE V: Comparison of nal designs
Name Des.b vs. Des.a Des.c vs. Des.a Des.d vs. Des.a Des.e vs. Des.a Des.f vs. Des.a Max. percentage diff. in Wi 0.0286 0.0425 0.3258 0.0499 0.3252 Max. percentage diff. in Li 0.0166 0.0253 0.1955 0.0301 0.1945 Max. percentage diff. in Vn 0.0025 0.0038 0.0279 0.0045 0.0278

loop would stop. We can see that the design has converged within 6 iterations. We experimented with a large number of specications and noted that tight specications reqired about 14 iterations. Otherwise most specications could be handled in less than 7 iterations or 10 at most. The runtimes are also indicated in the table (on a Intel Dual Core Processor). TABLE III: Convergence statistics for design example
iter. no. 1 2 3 4 5 6 Total CPU time (sec.) 14.03 14.83 14.98 15.39 14.74 15.06 89.03 Percentage discrepency with prev. iteration Gain Unity Gain Phase Qpower Area Freq. Margin -67.63 0.00 0.00 0.00 0.00 0.00 0.01 1.26 -1.03 -0.03 -0.64 -8.2 5.03 0.32 0.18 26.7 -5.88 1.87 -0.67 0.07 90.95 -72.11 18.79 -6.73 -0.57

Please note that the differences reported are in percentage which means they are very very small translating to absolute discrepencies of the order of 106 m. The results essentially signify that wide variation in the initial guess has no effect on the nal solution point. This strongly suggests that the solution obtained is indeed the globally optimal one. VI. C ONCLUSION In this paper we describe an improvised model for gm and gd suitable for geometric program based analog circuit sizing. The model effectively captures the drain voltage dependence on gm and gd which helps to improve accuracy appreciably specially in the submicron regime. The usefulness of the model has been demonstrated through a folded cascode op-amp sizing example on a 0.18 m CMOS process. ACKNOWLEDGMENT The authors would like to thank Michael Grant, Stephen Boyd and Yinyu Ye for making the code of cvx[6] available online. R EFERENCES
[1] J. Kim, J. Lee, L. Vandenberghe, and K. Yang, Techniques for improving the accuracy of geometric-programming based analog circuit design optimization, Proceedings of IEEE International Conference on Computer-Aided Design, pp. 863-870, 2004. [2] V. Aggarwal, U. OReilly, Simulation based reusable posynomial models for MOS transistor parameters, Design, Automation and Test in Europe (DATE), pp. 69-74, 2007. [3] M.M. Hershenson, S.P. Boyd and T.H. Lee, Automated design of folded-cascode op-amps with sensitivity analysis, 5th IEEE Int. Conf. Electron., Circuits Syst., Lisbon, Sep. 1998. [4] P. Mandal and V. Visvanathan, CMOS op-amp sizing using geometric programming formulation,IEEE Trans. Computer Aided Design, vol. 20, pp. 22-28, Jan. 2001. [5] M. M. Hershenson, S. P. Boyd and T. H. Lee, Optimal design of a CMOS op-amp via geometric programming, IEEE Trans. Computer Aided Design, vol. 20, pp. 01-21, Jan. 2001. [6] Michael Grant, Stephen Boyd and Yinyu Ye, cvx users guide, Available at http://www.stanford.edu/ boyd/cvx.

To test the immunity of the nal design point to the initial guess provided, widely varying initial guesses were supplied to the algorithm and the discrepency in the nal design was noted. The initial guess consists of gdnorm , gmnorm and the coefcients and powers of the monomial models of gd and gm |Vds =0.8 We found gmnorm to have a maximum value of approximately 1.5 and a minimum of 0.69; for gdnorm the maximum and minimum were about 4 and 1 respectively. The constants in the monomial models for gm |Vds =0.8 and gd have 3 different sets of values depending on the overdrive voltage range (range1 Vov : 100-200 mV ; range2 Vov : 200-350 mV ; range3 Vov : 350-900 mV ). Based on these extreme values of the parameters we prepared 6 sets of initial guesses as shown in Table IV. TABLE IV: The different initial guesses that were given
Name In.a In.b In.c In.d In.e In.f gm |Vds =0.8 model consts. range 1 range 2 range 3 range 1 range 2 range 3 gd model consts. range 1 range 2 range 3 range 1 range 2 range 3 gmnorm gmnorm 1.5 1.5 1.5 0.69 0.69 0.69 gdnorm gdnorm 4 4 4 1 1 1

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