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To enhance the sub-0.1m transistor performance, aggressive Equivalent Oxide Thickness (EOT) was used for gate oxide. Many works demonstrated the major interest of EOT reduction to improve drive current without damage off-channel ones [1]. However, it has been established that two major issues are limiting gate oxide reduction way: boron penetration inside p-channel during dopants activation [2] [3] and gate oxide leakage [4] [5]. A solution, to moderate simultaneously boron diffusion and gate leakage, is to use an oxynitride for gate oxide material [4]. Several papers exhibit the dangers of gate nitridation option, especially in term of gate oxide integrity and carriers mobility degradation [6]. On our side, we investigated another phenomena induced by oxidizing process: the dopant segregation inducing threshold voltage (Vth) roll-down for narrowest transistors. This work is focused on the strong impact of gate oxide process on narrow width effect due to the acceptors ions segregation inside STI-oxide during the gate oxidation step.

implantation and high dose (1e15at/cm). Dopants were activated during a rapid anneal at 1025C. Table 1 supplies the details of gate oxide trials performed for these experiments. Table1: summary of gate oxide experiments (27 >1@ 3URFHVV LG 3URFHVV IHDWXUHV QP   RTO (pure oxide) RTO 900C 2.0 0 RTO+RTN RTO 900C 1.8 4 RTN 950C RTO+DPN RTO 900C 1.65 8 DPN 35 RTO+DPN+Anneal RTO 900C 1.8 10 DPN 35 Anneal 1000/15 RTN+DPN+Anneal RTN 950C 1.6 14 DPN 35 Anneal 1000/15 A pure oxide, as reference, was realized with Rapid Thermal Oxidation (RTO). All the recipes used RTO as a pre-oxide before an additional nitridation step performed either with RTN or DPN method. Nitridation process used NO gas. Only last trial did not have a pre-oxide option, and used a direct nitridation mode in RTN coupled with a DPN. Table 1 explains main process conditions as temperature and time. The EOT have been extracted from C-V curves after fitting with simulated plot using Schrdinger-Poisson method [7]. The two last split included an additional anneal to stabilize finally the gate material. This anneal was performed under NO gas and consequently, EOT has varied. Nitrogen concentrations were measured by TOF-SIMS method. All trials have been investigated in term of narrow width control and STI-edge current component.



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A standard CMOS process was performed on <100> Si-bulk substrate, including conventional STI, dual gate oxide and cobalt salicide process. Source-drain extensions were built with low energy Arsenic

Figure 1 plots the Vth/Vthw=10m ratio as a function of transistor width (Wg) for each gate oxide process option. The Vth curve normalisation allows checking the Vth-Wg gradient evolution with respect to gate oxide process. More the Vth roll-down is large versus Wg down scaling, more the dopants segregation induced by gate oxidation is important. As shown in figure 1, pure oxide process (RTO) represents the worst case in term of segregation

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consequence. In fact, during pure oxide process, oxide growth occurs under O2 gas, whereas nitridation step uses generally NO chemistry. Thanks to a favourable Nitrogen/Oxygen gas ratio, recipes including a nitridation part have a lower segregation power than RTO ones.
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the global oxidizing power. It is worth pointing out that additional oxidizing anneal introduction damages the Kb*/ Kb* w=10m ratio. Best behaviour in term of narrow width effect is got by pure O2-free option (RTN+DPN+NO anneal). Thus it seems important to introduce an empirical parameter representing the oxidation power (OP) of gate oxide process described by equations (1) 23 = 722 .Y22 + 712 .Y 12 (1.a) with

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Fig 1: RNCE as function of gate oxide process. DPN process (triangle symbol), RTN process (diamond symbol) and RTO process (square symbol). To evaluate the charge concentration inside the channel close to the STI-edge region, some body factor (Kb) measurements were performed for each gate oxide process option. Due to the significant difference of EOT between each split (see table 1), we are normalized the standard body factor by the equivalent gate oxide thickness, Kb*=Kb/EOT. Moreover, to control the Vth gradient, an additional normalization versus the body factor of large device was used, Kb*/ Kb* w=10m. By plotting the normalized Kb*/ Kb* w=10m ratio with respect to transistor width, we are able to compare the strength of segregation phenomena which occurred during the gate oxide process. Figure 2 underlines this comparison.
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Where TO2 and TNO represent the process temperature of O2 step and NO-nitridation steps respectively. Kinetic process of O2 and NO steps are determined by time (TO2 and TNO) and oxidation speed (vO2 and vNO respectively). The tow and parameters are fitting parameters and depend on kind of oxidation. Figure 3 describes the correlation between the empirical oxidation power OP and the Kb*/ Kb* w=10m (Wg) gradient.
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Correlation graph extracted from figure 3 demonstrates clearly that a mean to limit the unsuitable segregation mechanism during gate oxidation process is to use NO gas ratio instead of pure O2 chemistry. Next paragraph checks the consequences of gate oxidation recipe features in term of sub-threshold current.



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ratio versus Wg shape as a function Fig 2: Kb / Kb of gate oxide process. The parasitic segregation effect is higher as the Kb*/ Kb (Wg) gradient is important. Moreover, this ratio evolution is directly proportional to the effective active charge at the STI-edge site. Clearly, nitridation steps enable to reduce the acceptors dopant segregation toward trench oxide, probably thanks to a significant reduction
* w=10m

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The global off-state current (Itotaloff) of a conventional MOS transistor is a summary of several leakage currents origins (see equation (3))
RII , WRWDO , FKDQQHO + , MXQFWLRQ + , JDWH + , HGJH (3)

Where Ijunction and Igate represent the parasitic junction leakage and gate leakage respectively. Ichannel is the usual

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channel leakage depending on both threshold voltage (Vth) and sub-threshold slope (S); this current is the ideal off-state current fully adjustable thanks to implants. Finally, Iedge includes the STI-edge current component generated inside the channel along trench edge, as described in figure 4. This component is a constant offset more sensitive in case of narrowest transistors. However, both STI process and segregation mechanisms are able to modify the value of this offset.

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Fig 6: Iedge/Ichannel ratio evolution as a function of gate process and temperature. As shown in figure 6, the Iedge/Ichannel ratio is significantly reduce in case of RTN or DPN process cases, i.e. including a NO step. As for Vth behaviour, best point is found for direct RTN nitridation coupled with DPN, i.e. a process without pure O2 step. We can notice that the edge component of leakage current is decreased as temperature increases. At high temperature, junction leakage becomes more important and drives the global off-state current. The junction part is also included inside the channel part modifying the Iedge/Ichannel ratio at high temperature. Figure 7 exhibits edge current evolution as a function of temperature.
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Fig 4: Off-state current component through the channel. Ichannel controlled by Vth and Iedge controlled by STI corner shape and gate oxidation process. In our case, if we consider that both junction leakage and gate leakage are identical whatever the split. Consequently, equation (3) becomes
RII , WRWDO = , FKDQQHO .: J + , HGJH .QHGJH (4)

with nedge representing the number of STI-edge inside the transistor (generally nedge=2). In order to extract the Iedge component for each gate oxide process and determine the impact of nitridation, we used a specific test structure with a constant effective Wg and including a variable edges number, as described in figure 5.

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Fig 7: Iedge current dependency with respect to temperature for each gate oxide process options. These plots supply activation energy of gate oxide process. Main results are summed up inside table 2. Table 2: Activation energy of edge current *DWH R[LGDWLRQ SURFHVV $FWLYDWLRQ (QHUJ\ (D RTO (pure oxide) -0.398 eV RTO + RTN -0.288 eV RTO + DPN -0.312 eV RTO + DPN + anneal -0.384 eV RTN + DPN + anneal -0.283 eV Activation energy of edge current is related to the bulk-drain junction doping level. Greater is the Ea, lower

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Fig 5: test structure description to work out the Iedge component versus gate oxide process. This kind of structure enables to enhance the edge current component generated close to the STI-edge. Using the element of figure 5, an Iedge/Ichannel ratio comparison has been established between the gate oxide process options.

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is the junction doping level and consequently lower is the bulk concentration. Thus, greater is the Ea, higher is the segregation effect. As shown in table 2, pure oxide process reached the higher activation energy correlated to the stronger dopants segregation mechanism. As found for Iedge/Ichannel ratio, optimum process is the full nitrided ones. To well understand the origin of the segregation differences between gate oxide process, we are plotted the Iedge/Ichannel ratio versus the oxidation power parameter, OP. Results are presented in figure 8. On this graph the substantial correlation found between the feature of gate oxide process and the percentage of edge current demonstrates the strong impact of gate oxide process on STI-edge behaviour. Thus, to limit the dopants segregation inside STI oxide during gate oxidation step, it is important to reduce the time and/or the temperature of pure O2 phases.
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[2] R.B. Flair, Anomalous B penetration through ultra thin gate oxides during rapid thermal annealing, IEEE Electron Device Letters, Vol. 20, N9, pp. 466470, September 1999. [3] H.P.Tuinhout HW DO., Effects of gate depletion and born penetration on matching of deep sub micron CMOS transistors, IEDM Techn. Digest, pp. 631-634, 1997. [4] Y.Si, X.Wang and T.P.Ma, Electrical properties of high quality ultra thin nitride/oxide stack dielectrics, IEEE Transactions on Electron Devices, Vol. 46, N2, pp 362-368, February 1999. [5] B.Yuwono HW DO., Reliability of ultra thin oxides and nitride films in the 1nm to 2nm range, Microelectronic Engineering, Vol. 48, pp. 51-54, 1999. [6] M.Takayanagi and Y.Toyoshima, Importance of Si-N atomic configuration at Si/Oxynitride interfaces on the performance of scaled MOSFETs, IEDM Techn. Digest, pp. 401-403, 1998. [7] C.Raynaud, J.L.Autran and M.Bidaud,analysis of MOS device capacitance voltage characteristics based on the self-consistent solution of the Schrdinger and Poisson equations , MRS Symposium, Vol. 592, Boston 1999.

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Fig 8: Iedge/Ichannel ratio law versus OP of gate oxide process. In conclusion, an adapted nitridation process, compatible with gate oxide integrity requirements and carriers mobility performance, allows both a gate leakage reduction [4] and a RNCE improvement very useful for Static RAM consumption limitation.



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A complete characterisation of gate oxidation impact on channel-dopants segregation has been performed. RNCE behaviour and current leakage have been investigated. Temperature dependency has been established. The role of gas ratio, on dopant segregation, used inside the gate oxide recipe has been demonstrated, and the interest of nitrided process, either RTN or DPN, to limit the RNCE was performed.



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[1] F.Ootsuka HW DO., A highly dense high performance 130nm node CMOS technology for large scale system on ship applications, IEDM Tech. Digest, pp. 575-579, 2000.

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