Professional Documents
Culture Documents
August 1995
Features
Y Y Y Y
TRI-STATE outputs on the I O port D and Q output sink capability of 64 mA Guaranteed 4000V minimum ESD protection Functionally and pin equivalent to the LS794
Package Description 20-Lead (0 300 Wide) Molded Dual-In-Line 20-Lead (0 300 Wide) Molded Small Outline JEDEC
Logic Symbol
Connection Diagram
DIP and SOIC
TL F 10652 1
TL F 10652 2
TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation
TL F 10652
RRD-B30M105 Printed in U S A
Truth Table
Inputs CP L or H or v L or H or v OE L H L H Q Qn Qn Qn D Outputs D Output Q Input Output Q Input
u u
In this case the output of the register is clocked to the inputs and the overall Q output is unchanged at Qn
Logic Diagram
TL F 10652 3
Voltage Applied to Output In HIGH State (with VCC e 0V) b 0 5V to VCC Standard Output b 0 5V to a 5 5V TRI-STATE Output Current Applied to Output in LOW State (Max) Twice the Rated IOL (mA) ESD Last Passing Voltage (Min) 4000V
4000V
Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs
Units
VCC
20 08
b1 2
IIN e b18 mA IOH e b3 mA IOH e b15 mA IOL e 64 mA VIN e 2 7V VIN e 7 0V (OE CP) VIN e 5 5V (Dn) VOUT e VCC IID e 1 9 mA All Other Pins Grounded VIOD e 150 mV All Other Pins Grounded VIN e 0 5V (OE CP)
Units
VCC
Conditions VOUT e 0V VOUT e 2 7V (Dn) VOUT e 0 5V (Dn) IID e 1 9 mA All Other Pins Grounded VIOD e 150 mV All Other Pins Grounded VOUT e 5 25V VO e HIGH VO e LOW VO e HIGH Z
mA mA mA
70
b 650
00
IOD
Output Circuit 74F Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current
3 75
mA
00
100 65 80 80
mA mA mA mA
AC Characteristics
74F Symbol Parameter Min fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ ts(H) ts(L) th(H) th(L) tw(H Max Clock Frequency Propagation Delay CP to Qn Output Enable Time Output Disable Time Setup Time HIGH or LOW Bus to Clock Hold Time HIGH or LOW Bus to Clock Clock Pulse Width HIGH or LOW 90 25 25 23 20 10 10 40 40 15 15 58 58 70 80 85 10 0 70 70 TA e a 25 C VCC e a 5 0V CL e 50 pF Typ Max 74F TA VCC e Comm CL e 50 pF Min 90 25 25 20 20 10 10 40 40 15 15 58 58 80 90 90 10 5 80 80 Max MHz ns ns ns ns ns ns Units
Ordering Informaton
The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follow 74F Temperature Range Family 74F e Commercial Device Type Package Code P e Plastic DIP S e Small Outline (SOIC) 794 S C X Special Variations X e Devices shipped in 13 reels Temperature Range C e Commercial (0 C to a 70 C)
20-Lead (0 300 Wide) Molded Small Outline Package JEDEC (S) NS Package Number M20B
20-Lead (0 300 Wide) Molded Dual-In-Line Package (P) NS Package Number N20A
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National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications