Professional Documents
Culture Documents
Ver.1.3, Revision 2
3.10 Window for selecting type of HDL code and symbol name . . 45
3.11 Window for selecting no of bits in counter and counting mode 46
3.12 Window for selecting up counting or down couting mode . . . 47
3.13 Window for selecting other options in counter . . . . . . . . . 48
3.14 Finish window in selecting counter . . . . . . . . . . . . . . . 49
3.15 Counter in block diagram file . . . . . . . . . . . . . . . . . . 50
3.16 Window for saving block diagram file . . . . . . . . . . . . . . 51
3.17 Symbol for input . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.18 Block diagram of the system . . . . . . . . . . . . . . . . . . . 53
3.19 Window to start analysis and synthesis . . . . . . . . . . . . . 54
3.20 Window to start functional simulation netlist . . . . . . . . . . 55
3.21 Window for creating vector waveform file . . . . . . . . . . . . 56
3.22 Window for giving input and output to vector waveform file . 57
3.23 Window for saving vector waveform file . . . . . . . . . . . . . 58
3.24 Window for simulator settings . . . . . . . . . . . . . . . . . . 59
3.25 Window for end time setting . . . . . . . . . . . . . . . . . . . 61
3.26 Window for giving clockvalue . . . . . . . . . . . . . . . . . . 62
3.27 Window for starting simulation . . . . . . . . . . . . . . . . . 63
3.28 Simulated waveform . . . . . . . . . . . . . . . . . . . . . . . 64
3.29 Full system . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.30 Window for assigning pin no to clock pin . . . . . . . . . . . . 66
3.31 Assign pin no to clock input pin . . . . . . . . . . . . . . . . . 67
3.32 Window for assigning pin no to pwm pin . . . . . . . . . . . . 68
3.33 Assign pin no to pwm pin . . . . . . . . . . . . . . . . . . . . 69
3.34 System with all pins assigned . . . . . . . . . . . . . . . . . . 70
3.35 To change the device settings . . . . . . . . . . . . . . . . . . 71
3.36 Device settings menu . . . . . . . . . . . . . . . . . . . . . . . 72
3.37 Unused pins setting . . . . . . . . . . . . . . . . . . . . . . . . 73
3.38 Start compilation . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.39 Start programming . . . . . . . . . . . . . . . . . . . . . . . . 75
3.40 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
1.1 Introduction
There is a rising interest in using digital control in power electronic applica-
tions. Digital controllers can be implemented by many means such as Digital
signal Processors(DSP), Application specific Integrated Circuits(ASICS) and
Field Programmable Gate Arrays(FPGA). All different ways of implementing
digital control are explored in this chapter. Their specific advatages and dis-
advantages are discussed. On the basis of that, a suitable device for designing
digital controller is selected. Before introducing different type of controllers,
an idea of the system and few examples of power electronic systems are given
and why controllers are required for such systems is discussed.
System
Excitation
Input Device of Output
the Load
system
Load input
The system is that which takes certain inputs and gives outputs in a desired
2 Digital Control in Power Electronic Applications
manner. In the system shown in the Fig. 1.1, the system device takes one
excitation input and delivers one output to the load. This kind of systems are
called Single Input Single Output system. If the output and input are more
than one then they are called Multi Input Multi Output systems. The output
of the system device changes due to the change in the excitation input and
also due to changes in the load. Since load has similar influence (changing the
output of the system device) on the system device as the excitation input, it
is also considered to be one of the input to the system. Load and excitation
input causes disturbances to the system output and they are also called as
disturbance inputs.
There are two ways for the designer to get the desired output from the
system device. One is by changing the input excitation to the device or by
changing the load. Usually in practical systems the load is not decided by the
designer, so only way to get the desired output is by changing the excitation
input to the system. To get required outputs from the system, an excitation
Load input
Excitation Desired
Input Excitation Input Device of Output
the Load
Device system
Control
Input K Sensor
Controller of the system Output
feedback
Controller
Ref output
device and a controller are introduced as shown in Fig. 1.2. The excitation
device shown in Fig. 1.2 process the excitation input according to the control
input from the controller and delivers to the system device to get the desired
output.
The controller takes reference output and output feedback from the system
as inputs and produces control inputs to the excitation device. If there is a
change in the reference to the controller or in the output of the system, the
control input to the excitation device is changed to achieve the desired output.
In this arrangement load disturbances also changes the control input to the
excitation device and maintains the output feedback equal to the reference
output. In a practical system to get desired output with changes in operating
conditions a controller as shown in Fig. 1.2 is necessary.
The system shown in Fig. 1.2 can be a
1.2 Block diagram of the system 3
1. Electrical system
2. Mechanical system
3. Electro-Mechanical system
4. Thermal system etc
i y ib
SCIM
K1
R Y B K1
K2
Controller ω fb
ω ref
User interface
Pulses
Il
Vo,ref
Controller
Vo
• Analog platform
• Digital platform
1.4 Conclusion
The generic idea of a system and why controller is required is explained. In
particular some examples of power electronic systems are also explained. The
different platforms for implementing control of Power Electronic Systems are
explored and found that digital controller with FPGA is more advantageous
1.4 Conclusion 7
2.1 Introduction
In this chapter, the minimum requirements of FPGA based digital platform
for control of power electronic systems is explained. Following that for the
new users a block diagram level idea of FPGA and their configuration method
is explained. Then the details of the developed board is provided.
PC with
Quartus FPGA BOARD BLOCK DIAGRAM
tool
Digital I/O
Analog output
Clock from DAC
20 MHz
12 bit ADC
AD7864 Sensed analog
bipolar type signal input
to ADC
; : ;
< =< !
!
! ?
=
> ?> 6
6
77 6
77 6677
;:
;:
:
; : ;
<
<
= < =
! !
!
! >
! ! >
? > ?
6 6
6
6 7 6
6 7 67
@ A
A
@ A
@ A
@ A
@ A
@:
@
A @
A @
A @
A @
A @
A = A
@ <= A
@ @
A @
A @
A @
A ? A
@ >? A
@ @
A @
A @ A@
A
@ A
A
@ A
@ A
@ A@
;A
@;
:;A
@ @
A @
A @
A @
A @
A <
= A
@ <= A
@ @
A @
A @
A @
A >
? A
@ >? A
@ @
A @
A @ A@
A
: ;:
< =< #
=
" "
?
5
4 5 4455
;
:
; : ;
=
<
= < = "
# " #
#
"
# " #" ?
" # >
? > ?
4 4
4
4 5 5 4
4 5 5 45
H I
I
H I
H I
H I
H :IH ;:I
H I
H I
H I
H I
H I
H < I
H =< I
H I
H I
H I
H I
H > I
H ?> I
H I
H I
H I
H IH
IH
I
H I
H I
H I
H IH I
:
; : ; H I
H I
H I
H I
H I
H I
<
= H I
< = H I
H I
H I
H I
H I
>
? H I
> ? H I
H I
H I
H IH
: ; : ;
< = < = $
% $
% $
% $
% $ % $ %
> ? > ?
2 3 3
2 3 3 2233
:
; : ;
<
= < = $ %
%
$ %$ >
? > ? 2
2
3 2
3 23
CB
C
B C
B C
B C
B C
B;: C
B;: C
B C
B C
B C
B C
B =
< C
B =< C
B C
B C
B C
B C
B ?
> C
B ?> C
B C
B C
B C
B CB
CB
C
B C
B C
B C
B C
B;: C
B;: C
B C
B C
B C
B C
B =
< C
B =< C
B C
B C
B C
B C
B ?
> C
B ?> C
B C
B C
B C
B CB
89
89
8
9 8
9 8 9 8 9 : ;:
;
=
&
' &
0 1 1
0 1 1 0011
8 9
8 98 :
; :;
<
= <= '
& '
& '& >
? >? 0
0
1 0
1 01
ED
E
D E
D E
D E
D E
D;: E
D;: E
D E
D E
D E
D E
D =
< =< D
E D
E D
E D
E D
E D
E > ?>
?
D
E D
E D
E D
E D ED
E
ED
E
D E
D E
D E
D E
D;: E
D;: E
D E
D E
D E
D E
D =
< E
D =< E
D E
D E
D E
D E
D ?
> E
D ?> E
D E
D E
D E
D ED
:
; : ;
<
= < = (
) (
) (
) (
) ( ) ( ) >
? > ?
. / /
. / / ..//
;
=
( )
)
( )( ?
.
.
/ .
/ ./
GF
G
F G
F G
F G
F :G
F:
;:G
F :;G
F
G F
G F
G F
G F
G < G
<
F =< G
<= G
F F
G F
G F
G F
G > G
>
F ?> G
>? G
F F
G F
G F GF
G
F G
G
F G
F G
F G
F ;G
F;
: ;:
F F
G F
G F
G F
G F
G = G
< =< +
=
F F F
G F
G F
G F
G ? G
> ?> ,
,
?
F F F
G F
G F GF
G
:
; : ;
<
= < = * *
+ *
+ *
+ * + * + >
? > ?
, - -
, - - ,,--
;
: ;:
=
< =< +
* +
* +* ?
> ?> ,
,
- ,
- ,-
Logic element
Vertical interconnect
Horizontal interconnect
JKJ
K
J
K JK
J
K JK
K
J
K JK
K
J
K JK
K
J
K JK
K
J
K JK
K
J
K JK
K
JK
JK
JK
JK
JK
JK
JK
JK
JK
JK
JK
JK
JK
JK
JK
JK
JK
JK
JK
JK
JK
JK
JK
JK
JK
JK
JK
JK
JK
JK
JK
JK
KJKJ
NO
J J J J J J J J J J J J J J J J J J J J J J J KJ Q
NON
ONONON
O
R S
R S
R SR
R SR
T UT
U
T UT
U
PQ
P PQ
QPQP
QPQP
ON
ON
ONON R
S R
S R S T
U T U PQ
P QPQP
NON
ONON
O
R S
S
R SR T UT
U
P
Q PQ
Q
QPQP
ON
ON
ONON R
S R
S R S T
U T U PQ
P QPQP
NON
ONON
O
R S
S
R SR T UT
U
X YX Q
Y
P
Q PQ
QPQP
ON
N O V WV
W P
ON
NON
ONONON W
O
V WV R S
S
R SR T UT
U
X YX Q
Y
PQ
PQ
QPQP
ON
N O V WV
W
R
S R
S R S T
U T U X
Y X Y P P
Q QPQP
ON
NON
ONONON W
O
V WV R S
S
R SR T UT
U
X YX Q
Y
PQ
PQ
QPQP
ON
N O V WV
W R
S R
S R S T
U T U X
Y X Y P P
Q QPQP
ON
NON
ONONON W
O
V WV R S
S
R SR T UT
U
X YX Q
Y
PQ
P QPQP
ON
ONON W
V WV R S
S
R SR T UT
U
X YX Q
Y
PQ
PQ
QPQP
ON
NON
ONON W
O
V WV R
S R
S R S T
U T U X
Y X Y P P
Q QPQP
ON
ONON W
V WV R S
S
R SR T UT
U
X YX Q
Y
PQ
PQ
QPQP
ON
NON
ONON W
O
V WV R
S R
S R S T
U T U X
Y X Y P P
Q QPQP
ON
N O V WV
W R S
S
R SR T UT
U
X YX Q
Y
PQ
P QPQP
ON
NON
ONONON W
O
V WV R S
S
R SR T UT
U
X YX Q
Y
PQ
PQ
QPQP
ON
N O V WV
W R
S R
S R S T
U T U X
Y X Y P P
Q QPQP
ON
NON
ONONON W
O
V WV R S
S
R SR T UT
U
X YX Q
Y
PQ
PQ
QPQP
ON
N O V WV
W R
S R
S R S T
U T U X
Y X Y P P
Q QPQP
ON
NON
ONONON
O
R S
S
R SR T UT
U
PQ
P QPQP
ON
ONON R S
S
R SR T UT
U
PQ
PQ
QPQP
ON
NON
ONON
O
R
S R
S R S T
U T U P P
Q QPQP
ON
ONON R S
S
R SR T UT
U
PQ
PQ
QPQP
ON
N ON M
O
R
S R
S R S T
U T U P P
Q QPQP
LM
LM
LM
L LM
L LM
L LM
L LM
L LM
L LM
L LM
L LM
L LM
L LM
L LM
L LM
L LM
L LM
L LM
L LM
L LM
L LM
L LM
L LM
L LM
L LM
L MLML
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L ML
Memory blocks
Logic elements
Phase locked loop circuit(PLL)
Input/Output element
on the board. A female mating connector has to be used to give the power
supply. Verify the power connections carefully before giving power to the
board. The female mating connector is also provided with the board.
2. Cyclone FPGA:
This is the heart of the board in which all the algorithms are implemented.
The Cyclone IC details are given table below.
Name FPGA
Part No EP1C12Q240C8
Manufacturer ALTERA
No of Pins 240
Package PQFP
No of Logic elements 12,080
No of PLL 2
Maximum clock frequency using PLL 275 MHz
Power supply required for core 1.5V(VCCINT)
Power supply required for I/O 3.3V(VCCIO)
Power supply required for PLL circuit 1.5V(VCCPLL)
IC No in the schematic U1(page no 1)
3. Configuration device:
Configuration device helps in configuring the FPGA in Active Serial (AS)
mode of configuration. The details of configuration IC are shown in table.
Name EEPROM
Part No EPCS4I8N
Manufacturer ALTERA
No of Pins 8
Package SOIC
Power supply required 3.3V
IC No in the schematic U25(page no 9)
Jumper
Pin No 1
is available at the end of the board. The board is covered by the box,
in that a suitable opening is left to connect Byteblaster-II cable to
connector J4. The cable can be connected and box can be closed.
Before removing or inserting the Byteblaster-II cable make sure that
powersupply is switched off. For JTAG mode, jumper settings are as
shown in table.
U1
EP1C12Q240C8
U1:29 U1:153
Dedicated clock(CLK1) Dedicated clock(CLK2)
Name ADC
Part No AD7864 AS-1
Manufacturer ANALOG DEVICES
No of pins 44
Package MQFP
Power supply 5V
Input analog voltage levels -10V to +10V
No of channels 4
Conversion time 1.6µs per channel
IC no in schematic U2, U3, U4, U5
1 1DIR
U1:184 3 CONVST DB0 43 2 1B1 1A1 47 U1:166
U1:183 4 CS DB1 42 3 1B2 1A2 46 U1:167
U1:182 5 RD DB2 41 5 1B3 1A3 44 U1:168
+15V U1:183 6 WR DB3 40 6 1B4 1A4 43 U1:169
7 SL1 DB4 39 8 1B5 1A5 41 U1:170
50 ohm 50 ohm
8 SL2 U2 DB5 38 9 1B6 U8 1A6 40 U1:173
AIN1 IN1
+5V 9 SL3 AD7864AS−1 DB6 34 11 Buffer 38
1B7 1A7 U1:174
0.1uF
10 SL4 DB7 33 12 1B8 1A8 37 U1:175
−15V
11 H/S SEL DB8 32 13 2B1 2A1 36 U1:176
+15V IN1 DB9 31 14 2B2 2A2 35 U1:177
21 VIN1A
50 ohm 50 ohm DB10 30 16 2B3 2A3 33 U1:178
AIN2 IN2 DB11 29 17 2B4 2A3 32 U1:179
44 19 30
0.1uF IN2 EOC 2B5 2A3 U1:180
19 VIN2A 20 2B6 29
−15V 2A3
22 2B7 2A3 27
+15V IN3 23 2B8 2A3 26
16 VIN3A
24 2DIR
50 ohm 50 ohm
AIN3 IN3
IN4
0.1uF 14 VIN4A
1
−15V BUSY
2
FRSTDATA
+15V
AGND
50 ohm 50 ohm
AIN4 IN4
U1:* Means output from FPGA
0.1uF
U1:* Means input to FPGA
−15V
DGND
1 1DIR
U1:165 3 CONVST DB0 43 2 1B1 1A1 47 U1
U1:164 4 CS DB1 42 3 1B2 1A2 46 U1
U1:163 5 RD DB2 41 5 1B3 1A3 44 U1
U1:162 6 WR DB3 40 6 1B4 1A4 43 U1
+15V
7 SL1 DB4 39 8 1B5 1A5 41 U1
50 ohm 50 ohm 8 SL2 U3 DB5 38 9 1B6 U9 1A6 40 U1
AIN5 IN5 +5V AD7864AS−1 DB6 34 11 Buffer
9 SL3 1B7 1A7 38 U1
0.1uF 10 SL4 DB7 33 12 1B8 37 U1
1A8
−15V 11 H/S SEL DB8 32 13 2B1 2A1 36 U1
IN5 DB9 31 14 2B2 2A2 35 U1
+15V 21 VIN1A
DB10 30 16 2B3 2A3 33 U1
50 ohm 50 ohm
IN6 DB11 29 17 2B4 2A3 32 U1
AIN6
44 19 30
IN6 EOC 2B5 2A3 U1
0.1uF 19 VIN2A 20 2B6 29
2A3
−15V
22 2B7 2A3 27
IN7 23 2B8 2A3 26
+15V 16 VIN3A
24 2DIR
50 ohm 50 ohm
AIN7 IN7
IN8
0.1uF 14 VIN4A
1
BUSY
−15V 2
FRSTDATA
+15V
AGND
50 ohm 50 ohm
AIN8 IN8 U1:* Means output from FPGA
0.1uF
U1:* Means input to FPGA
−15V
DGND
1 1DIR
U1:135 3 CONVST DB0 43 2 1B1 1A1 47 U1:117
U1:134 4 CS DB1 42 3 1B2 1A2 46 U1:118
U1:133 5 RD DB2 41 5 1B3 1A3 44 U1:119
+15V U1:132 6 WR DB3 40 6 1B4 1A4 43 U1:120
7 SL1 DB4 39 8 1B5 1A5 41 U1:121
50 ohm 50 ohm
AIN9 IN10 8 SL2 U4 DB5 38 9 1B6 U10 1A6 40 U1:122
+5V 9 SL3 AD7864AS−1 DB6 34 11 Buffer
0.1uF 1B7 1A7 38 U1:123
−15V 10 SL4 DB7 33 12 1B8 1A8 37 U1:124
11 H/S SEL DB8 32 13 2B1 2A1 36 U1:125
+15V IN9
21 VIN1A DB9 31 14 2B2 2A2 35 U1:126
50 ohm 50 ohm DB10 30 16 2B3 2A3 33 U1:127
AIN10 IN9 DB11 29 17 2B4 2A3 32 U1:128
44 19
0.1uF IN10 EOC 2B5 2A3 30 U1:131
−15V 19 VIN2A 20 2B6 2A3 29
22 2B7 2A3 27
+15V
IN11 23 2B8 2A3 26
16 VIN3A
50 ohm 50 ohm 24 2DIR
AIN11 IN11
0.1uF IN12
−15V 14 VIN4A
1
BUSY
2
+15V FRSTDATA
50 ohm 50 ohm
AIN12 IN12 AGND
0.1uF U1:* Means output from FPGA
−15V
U1:* Means input to FPGA
DGND
1 1DIR
U1:116 3 CONVST DB0 43 2 1B1 1A1 47
U1:114 4 CS DB1 42 3 1B2 1A2 46
+15V U1:113 5 RD DB2 41 5 1B3 1A3 44
U1:112 6 WR DB3 40 6 1B4 1A4 43
50 ohm 50 ohm
IN13 7 SL1 DB4 39 8 1B5 41
AIN13 1A5
8 SL2 U5 DB5 38 9 1B6 U11 1A6 40
0.1uF +5V AD7864AS−1 DB6 34 11 Buffer
−15V 9 SL3 1B7 1A7 38
10 SL4 DB7 33 12 1B8 1A8 37
+15V 11 H/S SEL DB8 32 13 2B1 2A1 36
IN14
50 ohm 50 ohm IN13
21 DB9 31 14 2B2 2A2 35
VIN1A
AIN14 DB10 30 16 2B3 2A3 33
0.1uF DB11 29 17 2B4 2A3 32
−15V 44 19 30
IN14 EOC 2B5 2A3
19 VIN2A 20 2B6 29
2A3
+15V IN15 22 2B7 27
2A3
50 ohm 50 ohm IN15 23 2B8 2A3 26
16 VIN3A
AIN15 24 2DIR
0.1uF
−15V IN16
IN16 14 VIN4A
1
BUSY
+15V
2
FRSTDATA
50 ohm 50 ohm
AIN16 AGND
0.1uF
−15V U1:* Means output from FPGA
DGND
Name DAC
Part No AD5447
Manufacturer Analog Devices
No of pins 24
Package SOIC
Power supply +10V ref
output analog voltage levels -10V to +10V
No of channels 2
Conversion time 0.8µs settling time
IC no in schematic U6 and U7(page no 5 and page no 6)
18
U1:194 DB0
17
U1:193 DB1
16 2
U1:188 DB2 IOUTA IOUT1
15
U1:187 DB3
14 24
U1:186 DB4 IOUTB IOUT2
13
U1:185 DB5
12
U1:201 DB6
11
U1:202 DB7 U6
10 AD5447
U1:203 DB8
9
U1:206 DB9
8
U1:207 DB10
7
U1:208 DB11
U1:197 CS
U1:200 R/W
U1:213 CH_A/B
18
U1:194 DB0
17
U1:193 DB1
16 2
U1:188 DB2 IOUTA IOUT1
15
U1:187 DB3
14 24
U1:186 DB4 IOUTB IOUT2
13
U1:185 DB5
12
U1:201 DB6
11
U1:202 DB7 U7
10 AD5447
U1:203 DB8
9
U1:206 DB9
8
U1:207 DB10
7
U1:208 DB11
U1:195 CS
U1:196 R/W
U1:213 CH_A/B
8. Connectors: In the FPGA board mainly two types of connectors are given:
The Universal Serial Bus (USB) has evolved to the standard interconnect be-
tween computers and peripherals. It can operate at very high speed rates(12Mb/s
to 480Mb/s). USB1T11AMTCX (universal Serial Bus Transceiver) is used as
a USB. It is capable of transmitting and receiving serial data at both full
speed (12Mb/s) and low speed (1.5Mb/s) data rates. USB interfacing circuit
diagram(as shown in 2.18) and I/O pins assignment is shown in Table 4.7
32 Analog and Digital Interfaces
+3.3V
+3.3V +3.3V
+3.3V 1.5K 10K
1.5K
J6 +3.3V J7 J8 J9
321 1 1 1
2 2
2 3
0.1uF
1 MODE VCC 14
U1:60 2 OE VMO/FSEO 1213 U1:58
U1:61 3 RCV VPO 11 U1:59
U1:62 4 D+ D+_USB
5 VP U33
U1:63 VM D− 10 D−_USB
6 SUSPEND SPEED 9 J21
7 GND NC 8 1
D−_USB 2
USB1T11AMTCX D+_USB 3
4
154−4100
USB_TYPE−B_CONNECTOR
system. CAN interfacing circuit diagram(as shown in Fig 2.19) and I/O pins
assignment is shown in Table 4.8
120 ohm
120 ohm
IO32 100K
0.1uF 1 TXD RS 5
2 GND CANH 6
3 1
VCC CANL 7 2
+5V 4 RXD SHDN 8 3
IO56 4
MAX3050ASA 5
6
30pF 100nF 7
8
RJ45 CONNECTOR
2.8 Conclusion
In this chapter, the minimum requirements of the digital controller for control-
ling power electronic systems with FPGA is explained. The details of the devel-
oped board is also given. In the following chapter the usage of the Quartus-II
tool (Design tool of ALTERA for programming FPGA) is explained. With
this design tool how to program the developed FPGA board is explained in
the next chapter.
34 Analog and Digital Interfaces
Chapter 3
3.1 Introduction
In this chapter, the usage of Quartus-II (a design tool of ALTERA) is ex-
plained. The required design is done using this design tool, the final compiled
output file is used for programming the FPGA using byteblaster-II cable or
USB-blaster cable. The usage of Quartus-II tool and programming the FPGA
is explained through a small example in this chapter. The example taken here
is for generating chopper PWM with constant reference. The following section
explains the design methodology of FPGA using Quartus-II.
36 Quartus System Software
2. Step 2:
It may display ” folder does not exist ” window as shown in Fig. 3.2, so
click ” Yes ” to create the folder of the name ” chopperpwm ”. After that
click ” Next ” to proceed.
3. Step 3:
Next window will appear as shown in Fig. 3.3. As we dont have any past
design libraries to include click ” Next ” to proceed.
4. Step 4:
Next window will appear as shown in Fig. 3.4.In this window select the
device used on the target board. The Family should be ” CYCLONE ”,
the specific device will be ” EP1C12Q240C8 ”, this is of PQFP package,
Speed grade of ” 8 ”, Pin count is of 240.
5. Step 5:
Next window will appear as shown in Fig. 3.5. As we are not going to
use any other tool, click ” Next ” to proceed.
6. Step 6:
Next window will appear as shown in Fig. 3.6. This shows the summary
of the project that we have started. Click ” Finish ” to end the project
wizard.
7. Step 7:
Go to ” File ” menu and click ” New ” to create the design file, the win-
dow will appear as shown in Fig. 3.7. Then clik on” Block diagram or
schematic file ” to open new block diagram design file.
8. Step 8:
The block diagram file as shown in Fig. 3.8 will appear. In that to get
various components click ” Symbol tool ” as shown in Fig. 3.8.
9. Step 9:
For the Project let us take a counter. After clicking on symbol tool a
windows as shown in Fig. 3.9 appears. In the ” Name ” column type
” lpm counter ”. Click ” ok ” on the window.
Figure 3.10: Window for selecting type of HDL code and symbol name
46 Quartus System Software
11. Step 11: Next window will appear as shown in Fig. 3.11. Let us take
” 12 ” bits as the no of bits for the ” lpm counter ”. select the options for
the counting as ” Up only ”. Click ” Next ” to proceed.
Figure 3.11: Window for selecting no of bits in counter and counting mode
3.2 Design methodology 47
Figure 3.22: Window for giving input and output to vector waveform file
58 Quartus System Software
4.1 Introduction
The FPGA board is designed in a generic way so that we can develop cus-
tom applications on it. For each application, we need to design an interface
properly. In this chapter an interface card which is designed for the real time
simulation application is discussed.
A Real Time System Simulator (RTSS) need to receive analog and digital
signals and output the processed signals. It is intended to have a user interface
so that inputs can be given and various system parameters can be changed
without the intervention of a PC based development System, once the model
development is complete. This feature needs a LCD display, keypad and var-
ious I/O pins. In this chapter other facilities such as serial port interfaces
RS232 can be added..
IO41 7 D0
IO42 8 D1
IO43 9 D2
10 D3 2 Line x 16 Charcter
IO44 11 D4
IO45 LCD Display
IO46 12 D5
13 D6
IO47 14 D7
IO48
E R/W RS GND VO VCC
6 5 4 1 2 3 +5V
10K
IO39 IO38 IO37
Figure 4.1: Circuit diagram of LCD interface.
IO33 4 3 2 1
Keypad O/P or FPGA I/P
IO34 8 7 6 5
IO35 12 11 10 9
IO39 16 15 14 13
LCD Initialization
For displaying various characters on the LCD, firstly LCD has to be initialized
properly. This is done by sending some basic instructions with appropriate
delay. After sending each instruction, data corresponding to the displaying
character can be sent. This logic is based on 3.5ms delay for each instruction
and data. LCD delay logic mainly consists of two counters, DFF and various
logic gates. First counter is used for genrating a 3.5ms clock signal which
enables the operation of inbuilt microcontroller of LCD. Second counter is
used for generating the selection lines of multiplexer and this counter output
width is depends on number of displaying character. For example displaying
of 12 characters, 16x1 multiplexer requires in which 12 input lines has to be
used for 12 characters and 4 input lines used for 4 initialization instruction. So
based on that, a 4 bit counter is required. DFF and count-stop logic section
is used for keeping all characters on display. When all the selection lines are
equal to logic ’1’ then count stop output will also be logic ’1’, which disable
the operation of microcontroller for new character display. Logic diagram is
shown in Fig 5.3
Character display
This logic mainly deals with different type of instructions and different char-
acter display. Various instructions used for LCD are as follows:
1. Function Set: It is required for operating the LCD in 1-line mode or 2-
line mode and setting the font size to 5x7 or 5x10. Its hexadecimal values
have to be in between 30h to 3Fh.
82 Interface Board for Real-Time Simulator
s(n)
Count_stop
s(n−1)
s(1)
s(0)
mux_sel[n..0]
Counter
Din Dout
clk DFF Enable
clk_out15
clk_out16
clock clk_out[24..0] −
Counter
Figure 4.3: Logic diagram of instruction and data delay for LCD.
2. Entry Mode Set: It is used for operation of entire shift on or off and
displaying the characters in increment mode or decrement mode. Its
hexadecimal values are from 04h to 07h.
3. Display Clear: After execution of this instruction entire display will be
clear. Its value is 01h.
4. Display on-off control: Its mainly used for display on-off, cursor display
on-off and cursor blink on-off. Its range from 80h to F0h.
After sending all instruction data has to be sent as per requirement. In LCD
we can display any alphabetic letter, various numbers and spacial characters
etc. This logic mainly consists of a multiplexer which input and selection line
depends on number of displaying character. Display of any character requires
three control signals, viz., Register select, Enable and Read/Write. Register
select has to logic ’0’ for sending instruction and logic ’1’ for sending data.
Enable will be decided by the delay section logic and it has to come with
clock. Read/write data has to be always logically ’0’ for writing the particular
charter on the LCD screen. Logic diagram is shown in Fig 5.4
4.3 LCD and Keypad Interface 83
char12[8..0] i16[8..0]
char11[8..0] i15[8..0]
−−−−−
16x1
MUX
LCD_data[8..0]
char3[8..0] i7[8..0]
char2[8..0] i6[8..0]
char1[8..0] i5[8..0]
INT4[8..0] i4[8..0]
INT3[8..0] i3[8..0]
INT2[8..0] i2[8..0]
INT1[8..0] i1[8..0] Register_select
sel[3..0]
stop
Count_stop mux_sel[3..0] Read/Write_bar
LCD_Dealy
Logic Section stop
clk
clock
LCD_Enable
The keypad is wired in matrix form with a switch at the intersection of each
row and column. Pressing a key establishes a connection between a row and
column. Interfacing of sixteen different keys requires four FPGA O/P lines
(arranged in rows) which will be used as a input of keypad and four FPGA I/P
lines (arranged in column) which will be acting as a output lines of key matrix.
The logic circuits are implemented in the FPGA. Digital Implementation of
keypad requires two main sections:
1. Scanning Logic section.
2. De-bouncing Section.
Scanning
It mainly consists of counter, decoder and four AND logic gates. Logic opera-
tion initialized by clock which is the input of counter. At every active edge of
clock, counter enables and gives the outputs ”00”, ”01”, ”10”, ”11”, ”00” and
so on. Counter output is the input of 2x4 decoder. From the corresponding
output of counter, only one decoder output line will be high at a time. Now if
user press any one key then corresponding to that column number will high,
which will be logically ANDed with the particular output of the decoder. Logic
high output of the AND gate shows scanning of particular key. In this logic,
very high-frequency clock is used and key-press time is very high compared to
the clock period. Logical AND operation avoids wrong key detection. Logic
diagram is shown in Fig 4.5
bit0 Scan1
Clock 2 Bit 2X4 Scan2 FPGA
Counter Decoder Scan3 O/P
bit1 Scan4
Key_collumn_no
Key1
Scan1
key2
Scan2
key3
Scan3
Key4
Scan4
De-bouncing
In the process of scanning the keypad to determine which key is pressed, the
scanner must take contact bounce into account. When a mechanical switch is
closed or opened, the switch contact will bounce, causing noise in the switch
output. The contact may bounce for several milliseconds before it settles down
to its final position. This bouncing problem may be avoided by two different
methods:
1. Sequential logic: Truth table for sequential logic is shown in Table 4.6
With reference to the truth table it can be concluded that the next state
is the logical OR operation of Input and Present State. De-bouncing logic
mainly consists of counter, comparator, OR gate and DFF as shown in
Fig 4.6. Counter output is connected to first input of comparator and
other input is set to decimal equivalent 1. Initially comparator output
’alessb’ set to one until counter gets the clock. DFF’s output initially
set to zero because it is asynchronously clearing by comparator output.
Input of the DFF is through the logical OR operation of Present state and
scanning section output for particular key. By this arrangement if once in
a while DFF output becomes logic ’1’ then it will remain ’1’, irrespective
of key bouncing.
2. SR Latch: Truth table for SR latch is shown in Table 4.7.
In this logic ’Set’ input is connected to the key and ’Reset’ is kept open.
According to the truth table if any key pressed then ’set’ input will be
high and output Q(t+1) will be logic ’1’ and now if bouncing occurs then
from the first condition output will remains present state i.e. logic ’1’.
Logic diagram is shown in Fig 4.7.
86 Interface Board for Real-Time Simulator
out out
Din Dout
key_no DFF
clk
clear
clear
clock
2 Bit S[1..0] a[1..0]
Enable Counter 2 Bit alessb clear
Comparator
b=1
Set
Q(t)
Q(t)
Reset
Figure 4.7: Logic diagram for De-bouncing by SR Latch.
Logic digram for two variables voltage and speed is shown in Fig 4.8
voltage
i0
var_key 2x1 variable_out
speed mux
i1 sel
clk_out20 1 bit
counter var_sel
ADD
2x1 MUX
+
i0[n..0]
constant=1 inc/dce_clk add_sub[n..0]
clk_en
i1[n..0]
_
inc_dce
SUB
inc_key inc
clk_out20 inc
inc_dce
dce
dce_key inc/dce_clk
clk_out20 dce
The RS232 interfacing circuit diagram(as shown in 4.10) and I/O pins
assignment is shown Table 4.8
5V 5V
O.1uF
O.1uF
2 V+ VCC
11 T1IN 14 1A 6A
IO40 T1OUT
10 T2IN T2OUT 7 2A 7A
12 R1OUT R1IN 13 3A 8A
IO57 4A
9 R2OUT R2IN 8 9A
1 C1+ 4 5A
C2+
O.1uF 3 C1− C2− 5 O.1uF
6 V−
GND DB9
O.1uF MAX232
4.5 Conclusion
A typical interface card design for the FPGA board has been explained. The
interface card not only brings out the analog and digital I/O channels from
the FPGA main board, but it also provides additional functionality like LCD
and keypad interface. It also houses an RS 232 interface.
Chapter 5
5.1 Introduction
AD5447 is CMOS, 12 bit, dual channel, current output digital to analog con-
verter(DAC). This device operates from 2.5V to 5.5V. In this board 5V power
supply is provided for DAC operation. Its conversion time is 0.8us. AD5447
operates in bipolar mode, providing output range from +Vref(10V) to -Vref(-
10). In this chapter, implementation of DAC interface program inside the
FPGA is discussed.
CS
Ts
R/W
Ts
A B A
CH_A/B
Ts Sampling Time
I/P2[11..0] B[11..0]
Din Dout PLL Section High
Low
Frequency CLK CLK_out
clk Frequency
Clk
DAC Input Selection Clock generation
CS1
Ts
CS2
Ts
R/W1
R/W2
CH
DAC1 A B A B
C D C D
DAC2
Ts Sampling Time
5.3 Conclusion
In this chapter, one method to interface the DAC is described. It is important
to see that the two DACs share the same data bus, and hence the method
96 How to use Digital to Analog converter (AD5447)
CS2
R/W2
PLL Section High Clock_out (n+1) CH_A/B
Low
Frequency CLK_in CLK_out
Frequency
Mux_op[11..0] DAC_IP[11..0]
Clock generation Output Section
I/P1[11..0] A[11..0]
Din Dout
B[11..0]
clk
Clk Mux1[11..0]
A[11..0]
I/P2[11..0] B[11..0]
Din Dout
clk clock_out(n+1)
Clk
Mux2[11..0] Mux_op[11..0]
I/P3[11..0] A[11..0]
Din Dout Mux1[11..0]
D[11..0] clk
clk
Clk Mux2[11..0]
C[11..0]
I/P4[11..0] B[11..0]
Din Dout
clk clock_out(n+1)
Clk
DAC Input Selection
of DAC interface depends on the hardware design of the board. Hence the
described method will be useful for the user to interface the DAC. A similar
VHDL program may also be written for this task.