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FPGA Board Document

Ver.1.3, Revision 2

Department of Electrical Engineering


Indian Institute of Science
Bangalore 560012

Parag Anand Rajne


Jayalakshmi
Ravi Krishna

February 20, 2007


Contents

1 Digital Control in Power Electronic Applications 1


1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Block diagram of the system . . . . . . . . . . . . . . . . . . . 1
1.2.1 Example of an Electro-Mechanical system . . . . . . . 3
1.2.2 Example of an Electrical system . . . . . . . . . . . . . 4
1.3 Different types of controllers . . . . . . . . . . . . . . . . . . . 4
1.3.1 Analog platform . . . . . . . . . . . . . . . . . . . . . . 5
1.3.2 Digital platform . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Analog and Digital Interfaces 9


2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Hardware requirements for FPGA based digital platform . . . 9
2.3 Cyclone FPGA and configuration device . . . . . . . . . . . . 11
2.3.1 Cyclone FPGA architecture . . . . . . . . . . . . . . . 11
2.3.2 Configuration device . . . . . . . . . . . . . . . . . . . 13
2.4 Changes in the features . . . . . . . . . . . . . . . . . . . . . . 14
2.5 Developed FPGA board details . . . . . . . . . . . . . . . . . 14
2.6 USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.6.1 USB connector . . . . . . . . . . . . . . . . . . . . . . 32
2.6.2 Jumpers setting . . . . . . . . . . . . . . . . . . . . . . 32
2.7 CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.7.1 CAN connector . . . . . . . . . . . . . . . . . . . . . . 33
2.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3 Quartus System Software 35


3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.2 Design methodology . . . . . . . . . . . . . . . . . . . . . . . 36

4 Interface Board for Real-Time Simulator 77


4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.2 Analog and digital interface . . . . . . . . . . . . . . . . . . . 77
4.3 LCD and Keypad Interface . . . . . . . . . . . . . . . . . . . . 79
4.3.1 LCD Interface . . . . . . . . . . . . . . . . . . . . . . . 79
2 CONTENTS

4.3.2 Keypad Interface . . . . . . . . . . . . . . . . . . . . . 80


4.3.3 Digital logic implementation of LCD . . . . . . . . . . 81
4.3.4 Interface of Keypad . . . . . . . . . . . . . . . . . . . . 84
4.3.5 Control variable selection by single key . . . . . . . . . 86
4.3.6 Increment and Decrement operation by keypad . . . . 87
4.4 RS232 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

5 How to use Digital to Analog converter (AD5447) 91


5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.2 FPGA implementation of DAC . . . . . . . . . . . . . . . . . 91
5.2.1 Control signals . . . . . . . . . . . . . . . . . . . . . . 93
5.2.2 Logic for DAC operation . . . . . . . . . . . . . . . . . 93
5.2.3 Operation of both DACs together . . . . . . . . . . . . 94
5.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
List of Figures

1.1 Block diagram of the system . . . . . . . . . . . . . . . . . . . 1


1.2 System with controller and excitation device . . . . . . . . . . 2
1.3 Electromechanical system with excitation device and controller 3
1.4 Battery charger system . . . . . . . . . . . . . . . . . . . . . . 4

2.1 Block diagram of FPGA based digital platform . . . . . . . . 10


2.2 Block diagram of FPGA architecture . . . . . . . . . . . . . . 11
2.3 Block diagram of cyclone FPGA . . . . . . . . . . . . . . . . . 12
2.4 Configuration of cyclone FPGA . . . . . . . . . . . . . . . . . 13
2.5 Pins of the jumpers . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6 Clock interface to FPGA . . . . . . . . . . . . . . . . . . . . . 17
2.7 ADC1 interface to FPGA . . . . . . . . . . . . . . . . . . . . 19
2.8 ADC2 interface to FPGA . . . . . . . . . . . . . . . . . . . . 20
2.9 ADC3 interface to FPGA . . . . . . . . . . . . . . . . . . . . 21
2.10 ADC4 interface to FPGA . . . . . . . . . . . . . . . . . . . . 22
2.11 DAC1 interface to FPGA . . . . . . . . . . . . . . . . . . . . . 24
2.12 DAC2 interface to FPGA . . . . . . . . . . . . . . . . . . . . . 25
2.13 Details of buffer1 I/O lines of the FPGA board . . . . . . . . 27
2.14 Details of buffer2 I/O lines of the FPGA board . . . . . . . . 28
2.15 Details of buffer3 I/O lines of the FPGA board . . . . . . . . 29
2.16 Details of buffer4 I/O lines of the FPGA board . . . . . . . . 30
2.17 Details of buffer5 I/O lines of the FPGA board . . . . . . . . 31
2.18 Circuit diagram of USB Interface. . . . . . . . . . . . . . . . . 32
2.19 Circuit diagram of CAN Interface. . . . . . . . . . . . . . . . . 33

3.1 Window for opening new project . . . . . . . . . . . . . . . . 36


3.2 Window showing folder does not exist . . . . . . . . . . . . . . 37
3.3 Window for adding user library . . . . . . . . . . . . . . . . . 38
3.4 Window for specifying FPGA device . . . . . . . . . . . . . . 39
3.5 Window for adding EDA tools . . . . . . . . . . . . . . . . . . 40
3.6 Window for summary of the project . . . . . . . . . . . . . . . 41
3.7 Window for opening new blockdiagram/schematic file . . . . . 42
3.8 Icon for symbol tool . . . . . . . . . . . . . . . . . . . . . . . 43
3.9 Window for selecting counter . . . . . . . . . . . . . . . . . . 44
4 LIST OF FIGURES

3.10 Window for selecting type of HDL code and symbol name . . 45
3.11 Window for selecting no of bits in counter and counting mode 46
3.12 Window for selecting up counting or down couting mode . . . 47
3.13 Window for selecting other options in counter . . . . . . . . . 48
3.14 Finish window in selecting counter . . . . . . . . . . . . . . . 49
3.15 Counter in block diagram file . . . . . . . . . . . . . . . . . . 50
3.16 Window for saving block diagram file . . . . . . . . . . . . . . 51
3.17 Symbol for input . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.18 Block diagram of the system . . . . . . . . . . . . . . . . . . . 53
3.19 Window to start analysis and synthesis . . . . . . . . . . . . . 54
3.20 Window to start functional simulation netlist . . . . . . . . . . 55
3.21 Window for creating vector waveform file . . . . . . . . . . . . 56
3.22 Window for giving input and output to vector waveform file . 57
3.23 Window for saving vector waveform file . . . . . . . . . . . . . 58
3.24 Window for simulator settings . . . . . . . . . . . . . . . . . . 59
3.25 Window for end time setting . . . . . . . . . . . . . . . . . . . 61
3.26 Window for giving clockvalue . . . . . . . . . . . . . . . . . . 62
3.27 Window for starting simulation . . . . . . . . . . . . . . . . . 63
3.28 Simulated waveform . . . . . . . . . . . . . . . . . . . . . . . 64
3.29 Full system . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.30 Window for assigning pin no to clock pin . . . . . . . . . . . . 66
3.31 Assign pin no to clock input pin . . . . . . . . . . . . . . . . . 67
3.32 Window for assigning pin no to pwm pin . . . . . . . . . . . . 68
3.33 Assign pin no to pwm pin . . . . . . . . . . . . . . . . . . . . 69
3.34 System with all pins assigned . . . . . . . . . . . . . . . . . . 70
3.35 To change the device settings . . . . . . . . . . . . . . . . . . 71
3.36 Device settings menu . . . . . . . . . . . . . . . . . . . . . . . 72
3.37 Unused pins setting . . . . . . . . . . . . . . . . . . . . . . . . 73
3.38 Start compilation . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.39 Start programming . . . . . . . . . . . . . . . . . . . . . . . . 75
3.40 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

4.1 Circuit diagram of LCD interface. . . . . . . . . . . . . . . . . 79


4.2 4x4 Matrix diagram of Keypad . . . . . . . . . . . . . . . . . 80
4.3 Logic diagram of instruction and data delay for LCD. . . . . . 82
4.4 Logic diagram of LCD display. . . . . . . . . . . . . . . . . . . 83
4.5 Logic diagram of Keypad Scanning Section. . . . . . . . . . . 84
4.6 Logic diagram for De-bouncing. . . . . . . . . . . . . . . . . . 86
4.7 Logic diagram for De-bouncing by SR Latch. . . . . . . . . . . 86
4.8 Logic diagram for selection of variable. . . . . . . . . . . . . . 87
4.9 Increment and Decrement logic diagram. . . . . . . . . . . . . 88
4.10 Circuit diagram of RS232. . . . . . . . . . . . . . . . . . . . . 89

5.1 Timing diagram of DAC . . . . . . . . . . . . . . . . . . . . . 93


LIST OF FIGURES 5

5.2 Logic diagram of DAC . . . . . . . . . . . . . . . . . . . . . . 94


5.3 Timing diagram of both DACs operation . . . . . . . . . . . . 95
5.4 Logic diagram of both DACs operation . . . . . . . . . . . . . 96
6 LIST OF FIGURES
Chapter 1

Digital Control in Power


Electronic Applications

1.1 Introduction
There is a rising interest in using digital control in power electronic applica-
tions. Digital controllers can be implemented by many means such as Digital
signal Processors(DSP), Application specific Integrated Circuits(ASICS) and
Field Programmable Gate Arrays(FPGA). All different ways of implementing
digital control are explored in this chapter. Their specific advatages and dis-
advantages are discussed. On the basis of that, a suitable device for designing
digital controller is selected. Before introducing different type of controllers,
an idea of the system and few examples of power electronic systems are given
and why controllers are required for such systems is discussed.

1.2 Block diagram of the system

System

Excitation
Input Device of Output
the Load
system

Load input

Figure 1.1: Block diagram of the system

The system is that which takes certain inputs and gives outputs in a desired
2 Digital Control in Power Electronic Applications

manner. In the system shown in the Fig. 1.1, the system device takes one
excitation input and delivers one output to the load. This kind of systems are
called Single Input Single Output system. If the output and input are more
than one then they are called Multi Input Multi Output systems. The output
of the system device changes due to the change in the excitation input and
also due to changes in the load. Since load has similar influence (changing the
output of the system device) on the system device as the excitation input, it
is also considered to be one of the input to the system. Load and excitation
input causes disturbances to the system output and they are also called as
disturbance inputs.
There are two ways for the designer to get the desired output from the
system device. One is by changing the input excitation to the device or by
changing the load. Usually in practical systems the load is not decided by the
designer, so only way to get the desired output is by changing the excitation
input to the system. To get required outputs from the system, an excitation

Load input

Excitation Desired
Input Excitation Input Device of Output
the Load
Device system

Control
Input K Sensor
Controller of the system Output
feedback
Controller
Ref output

Figure 1.2: System with controller and excitation device

device and a controller are introduced as shown in Fig. 1.2. The excitation
device shown in Fig. 1.2 process the excitation input according to the control
input from the controller and delivers to the system device to get the desired
output.
The controller takes reference output and output feedback from the system
as inputs and produces control inputs to the excitation device. If there is a
change in the reference to the controller or in the output of the system, the
control input to the excitation device is changed to achieve the desired output.
In this arrangement load disturbances also changes the control input to the
excitation device and maintains the output feedback equal to the reference
output. In a practical system to get desired output with changes in operating
conditions a controller as shown in Fig. 1.2 is necessary.
The system shown in Fig. 1.2 can be a
1.2 Block diagram of the system 3

1. Electrical system
2. Mechanical system
3. Electro-Mechanical system
4. Thermal system etc

1.2.1 Example of an Electro-Mechanical system

Excitation device System


System device
and load
R
Y + R
Vdc Y
B − B

i y ib
SCIM
K1

R Y B K1

K2
Controller ω fb

ω ref
 User interface

Figure 1.3: Electromechanical system with excitation device and controller

The electromechanical system is shown in Fig. 1.3. System consists of a


Squirrel Cage Induction Motor(SCIM) and a mechanical load connected to
shaft of the motor. SCIM takes electrical energy and converts into mechanical
energy and delivers to the mechanical load. The electrical input to the motor
is from two level voltage source inverter (excitation device), which takes DC
voltage (excitation input) as input and gives three phase balanced AC voltage
to the motor. Input for the two level voltage source inverter is from a uncon-
trolled rectifier (diode bridge) which converts input three phase grid voltage
to DC voltage.
The controller takes ωref from the user and also current, speed from the
motor and produces control pulses required for the two level voltage source
inverter(Excitation device). In this example excitation device is a power elec-
tronic converter which process the input power and delivers the output power
in the required form to the system device. The system consisting of a elec-
tromechanical energy conversion device, mechanical load, power electronic con-
verter and controller is traditionally called as electric drive.
4 Digital Control in Power Electronic Applications

1.2.2 Example of an Electrical system

Excitation device System


Battery

Pulses
Il
  Vo,ref
Controller
Vo

Figure 1.4: Battery charger system

A Battery charging system is taken as an example for an electrical system.


The battery charger system is shown in Fig. 1.4. The system consists of a
Power electronic converter as an excitation device in which the first stage is
uncontrolled diode rectifier, and the second stage is DC-DC converter which
has controllable switches. To charge the battery the controller takes Vo,ref from
the user, battery current Il and battery voltage Vo from the system to produce
the pulses to the DC-DC converter. The battery can be charged in a required
way by controlling the switches of the DC-DC converter. In this example there
is no separate system device and load in the system. Both are one and the
same. The examples mentioned above show that a controller is necessary to
achieve the desired output irrespective of disturbance inputs to the system.
This report focuses on the controller that can be used for the systems in which
the power electronic converter is an excitation device. Different options that
can be used for implementing the controller are discussed below.

1.3 Different types of controllers

The controller can be implemented in following ways.

• Analog platform

• Digital platform

1. Microcontrollers and Digital Signal Processor


2. Field Programmable Gate Arrays
1.3 Different types of controllers 5

1.3.1 Analog platform


Controllers can be implemented using passive components such as resistor,
capacitor and active devices such as operational amplifiers. These type of
controllers sense the quantities from the system as analog voltage and also
takes reference as analog voltages and produces control input to the excitation
device. This type of controllers are called as analog controllers. For different
applications controllers has to be separately designed because same controller
cannot be reconfigured for different applications. This will increase the time
to build the prototype. Application Specific Integrated Circuits(ASIC) are
available for applications such as Current programmed control, controller for
unity power factor rectifier etc.
The advantages of analog controllers are:
1. Low cost if the controller is simple.
2. Easy interpretation of control strategy in analog domain.
The disadvantages of analog controllers are:
1. Reconfigurability of the control is not possible without changing the hard-
ware.
2. Number of passive components used are more.
3. More sensitive to variations in temperature.
4. Reliability of the system is low because no. of components used is large.

1.3.2 Digital platform


In recent days, the usage of digital controllers has considerably increased in
the field of Power Electronics and Drives. The controllers can be realized in
digital domain using Microcontrollers, Digital Signal Processors(DSP), Field
Programmable Gate Arrays(FPGA) etc.

Microcontrollers and DSP

In Microcontrollers and DSP, the hardware such as adder, multiplier, shift


register, counters, memory etc., are present. These hardware resources are
wired in such a way that users can make use of these hardware to realize
the control algorithm. Users can write suitable software instruction which
activates this hardware to do suitable job. The same hardware can be used
many number of times to establish the required task. In this way the resource
of the hardware is fixed and various control algorithms can be implemented
using the same hardware.
The reconfigurability of the control was not possible with analog controllers
and that disadvantage is eliminated in digital platform (using microcontrollers
and DSP)
6 Digital Control in Power Electronic Applications

The main advantages of digital controllers using DSP and Microcontrollers


are:
1. Reconfigurability of the control without changing the hardware.
2. Less passive components are used.
3. Less sensitive to temperature variations.
The disadvantages are:
1. The hardware resources are fixed and it cannot be changed once the
particular DSP/Microcontroller is selected.
2. Design depends more on the hardware architecture of the processor.

Field Programmable Gate Array(FPGA) based digital platform

FPGA has Logic Elements(LEs) as their building blocks. Each LE contains


hardware resources such as gates, flipflops, decoder, counter etc., The hardware
resources available in these LEs are wired every time to realize required logic.
Number of logic elements available indicates logic density of the FPGA. The
hardware resources available in each LE varies according to the manufacturer.
In FPGA the hardware is configurable which was not possible with DSP or
Microcontroller. FPGA provides resources for the user in a more abstract level.
So with these resources any specific hardware such as DSP/Microcontroller
can be configured according to the requirement. The User gets advantage of a
mixed environment (Programmable hardware and fixed hardware environment
such as DSP/Microcontroller)
The main advantages of digital controllers using FPGA are:
1. The reconfigurability of the hardware
2. The user is independent of the architecture of the device
With the above understanding of different platforms, digital controller with
FPGA is better. So to control systems such as shown in Fig. 1.3 and Fig. 1.4
the digital controller using FPGA is selected. The minimum requirements of
the digital controller for controlling any system using power electronic exci-
tation is discussed in the following chapter. On that basis digital controller
platform using FPGA and other interfacing devices is designed.

1.4 Conclusion
The generic idea of a system and why controller is required is explained. In
particular some examples of power electronic systems are also explained. The
different platforms for implementing control of Power Electronic Systems are
explored and found that digital controller with FPGA is more advantageous
1.4 Conclusion 7

than others. In the following chapter the minimum requirements of a digital


platform with FPGA for control of Power Electronics System is discussed.
8 Digital Control in Power Electronic Applications
Chapter 2

Analog and Digital Interfaces

2.1 Introduction
In this chapter, the minimum requirements of FPGA based digital platform
for control of power electronic systems is explained. Following that for the
new users a block diagram level idea of FPGA and their configuration method
is explained. Then the details of the developed board is provided.

2.2 Hardware requirements for FPGA based digital plat-


form
The block diagram of the developed digital platform is shown in Fig. 2.1. This
digital platform consists of cyclone FPGA, configuration device (EEPROM)
and other interfacing devices such as Analog to Digital Converter(ADC), Dig-
ital to Analog Converter (DAC) and digital I/Os which are dedicated I/O pins
of the FPGA device. ADC and DAC are also interfaced using dedicated I/O
pins of the FPGA device.
For control of power electronic systems, analog signals such as voltages
and currents must be sensed. Hence ADC is required. Sometimes there may
be need to send control output in analog form so DAC is required. DAC
can also be used to view some digital signals in analog form for debugging
purposes. Digital I/Os can be used for control output such as gating pulses
to power converter, and also it can be used to interface devices such as ADC,
DAC, LCD display, keyboard etc. These are the minimum requirements of the
FPGA based digital platform for control of power electronic systems. In the
next section, the generic architecture of FPGA and Cyclone device architecture
is explained in detail.
10 Analog and Digital Interfaces

PC with
Quartus FPGA BOARD BLOCK DIAGRAM
tool

Digital I/O

Configuration Cyclone 12 bit DAC


Device FPGA device AD 5447
EEPROM EP1C12Q240C8 bipolar type
EPCS4IN

Analog output
Clock from DAC
20 MHz

12 bit ADC
AD7864 Sensed analog
bipolar type signal input
to ADC

Figure 2.1: Block diagram of FPGA based digital platform


2.3 Cyclone FPGA and configuration device 11

2.3 Cyclone FPGA and configuration device

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F G
F G
F G
F ;G
F;

: ;: 
F F

G F

G F

G F

G F

G = G

< =< +

=
F F F

G F

G F

G F

G ? G

> ?> ,
,

?
F F F

G F

G F GF
G






 

     :

; : ;  

 

 

     <

= < = * *

+ *

+ *

+ * + * + >

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, - -

, - - ,,--
 
  ;
: ;: 
 
  =
< =< +
* +
* +* ?
> ?> ,
,
- ,
- ,-
Logic element
Vertical interconnect
Horizontal interconnect

Figure 2.2: Block diagram of FPGA architecture

Before introducing the Cyclone FPGA a generic architecture of FPGA is


shown in Fig. 2.2. FPGA has logic elements arranged in rows and columns
as shown in Fig. 2.2. The vertical and horizontal interconnects of varying
speeds provides signal interconnects to implement the custom logic. Each logic
element has certain hardware resources which will be utilised by the routing
software to realise the user logic.

2.3.1 Cyclone FPGA architecture


Cyclone FPGA shown in Fig. 2.3 contains a two-dimensional row and col-
umn based architecture to implement custom logic. Column and row inter-
12 Analog and Digital Interfaces

Cyclone FPGA block diagram


JK

JKJ
K
J

K JK
J

K JK

K
J

K JK

K
J

K JK

K
J

K JK

K
J

K JK

K
J

K JK

K
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JK
JK

JK
JK

JK
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JK
JK

JK
JK

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JK

JK
JK

JK
JK

JK
JK

JK
JK

JK
JK

JK
JK

JK
JK

JK
JK

JK
JK

JK
KJKJ
NO
J J J J J J J J J J J J J J J J J J J J J J J KJ Q

NON
ONONON
O
R S

R S

R SR
R SR
T UT
U

T UT
U

PQ

P PQ

QPQP
QPQP
ON

ON
ONON R

S R

S R S T

U T U PQ

P QPQP
NON
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O
R S

S
R SR T UT
U
P

Q PQ

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QPQP
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ON
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NON
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R S

S
R SR T UT
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X YX Q

Y
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Q PQ
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ON
N O V WV

W P
ON

NON
ONONON W

O
V WV R S

S
R SR T UT
U
X YX Q

Y
PQ

PQ
QPQP
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N O V WV
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R

S R

S R S T

U T U X

Y X Y P P

Q QPQP
ON

NON
ONONON W

O
V WV R S

S
R SR T UT
U
X YX Q

Y
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QPQP
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N O V WV

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Y X Y P P

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ONONON W

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V WV R S

S
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P QPQP
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ONON W
V WV R S

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QPQP
ON

NON
ONON W

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V WV R

S R

S R S T

U T U X

Y X Y P P

Q QPQP
ON
ONON W
V WV R S

S
R SR T UT
U
X YX Q

Y
PQ

PQ
QPQP
ON

NON
ONON W

O
V WV R

S R

S R S T

U T U X

Y X Y P P

Q QPQP
ON
N O V WV

W R S

S
R SR T UT
U
X YX Q

Y
PQ

P QPQP
ON

NON
ONONON W

O
V WV R S

S
R SR T UT
U
X YX Q

Y
PQ

PQ
QPQP
ON
N O V WV

W R

S R

S R S T

U T U X

Y X Y P P

Q QPQP
ON

NON
ONONON W

O
V WV R S

S
R SR T UT
U
X YX Q

Y
PQ

PQ
QPQP
ON
N O V WV

W R

S R

S R S T

U T U X

Y X Y P P

Q QPQP
ON

NON
ONONON
O
R S

S
R SR T UT
U
PQ

P QPQP
ON
ONON R S

S
R SR T UT
U
PQ

PQ
QPQP
ON

NON
ONON
O
R

S R

S R S T

U T U P P

Q QPQP
ON
ONON R S

S
R SR T UT
U
PQ

PQ
QPQP
ON

N ON M

O
R

S R

S R S T

U T U P P

Q QPQP
LM

LM
LM

L LM

L LM

L LM

L LM

L LM

L LM

L LM

L LM

L LM

L LM

L LM

L LM

L LM

L LM

L LM

L LM

L LM

L LM

L LM

L LM

L LM

L LM

L MLML
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L M
L ML
Memory blocks
Logic elements
Phase locked loop circuit(PLL)
Input/Output element

Figure 2.3: Block diagram of cyclone FPGA

connects of varying speed provide signal interconnects between Logic Array


Blocks(LAB) and embedded memory blocks. The logic array consists of LABs,
with 10 logic elements in each LAB. An logic element is a small unit of logic
providing efficient implementation of user logic functions. Cyclone family has
devices with logic elements from 2,910 to 20,060 logic elements. Selected device
2.3 Cyclone FPGA and configuration device 13

for the development of digital platform is EP1C12Q240C8 which has 12,060


logic elements.
The Cyclone device consists of embedded memory blocks, which are grouped
into columns across the device in between certain LABs. Cyclone devices offer
between 60 to 288 Kbits of embedded RAM. Each I/O pin of the device is
fed by an I/O element(IOE) located at the end of the LAB rows and colums
around the periphery of the device. Cyclone devices provide global clock net-
work and up to two Phase Locked Loops (PLLs). The global clock network
consists of eight global clock that drive throughout the entire device. In cy-
clone external clock inputs can be maximum up to 100MHz and internally
by using PLLs it can be increased upto 475MHz(for the highest speed grade
cyclone device). The PLL takes minimum input of 20MHz clock input.

2.3.2 Configuration device

PC with Quartus tool

Byte Blaster−II cable or


USB blaster cable

Active serial mode JTAG mode

Configuration Cyclone FPGA


EEPROM device
EPCS4IN EP1C12Q240C8

Figure 2.4: Configuration of cyclone FPGA

Configuration device is an EEPROM which is connected to a personal com-


puter through byteblaster-II (parallel port) or USB blaster (USB port) down-
load cable of ALTERA.The setup is shown in Fig. 2.4 The design of required
logic is done using quartus-II tool and the output file (programmable object
file) of the compilation is downloaded through byteblaster-II or USB blaster
cable to EEPROM. In this process the FPGA does not interact with the con-
figuration device. After the completion of the download, FPGA takes control
and takes data from the configuration device to its internal Random Access
Memory(RAM). According to the information logic elements gets intercon-
nected to the users logic and starts functioning. Loading of the program to
the configuration device is one time process, because it retains the data (EEP-
ROM) when power is swithed off. But FPGA loses its data when power is
14 Analog and Digital Interfaces

switched off, as data is stored in RAM. So everytime when FPGA is powered


on and it acts as master device and takes data from EEPROM. This pro-
cess lasts for 136 clock cycles. The clock frequency used for transferring the
data serially from EEPROM is maximum of 20MHz. Such a configuration is
called as Active Serial(AS) configuration. This mode of configuration is used
to configure FPGA in stand-alone mode.
In development time one can use Joint Test Action Group (JTAG) mode of
configuring in which the data from PC can be downloaded through byteblaster-
II or USB blaster cable to FPGA RAM as shown in Fig. 2.4. In this method
every time when power is switched off the data in FPGA will be lost. so the
downloading of data has to be done every time. In this method of configuration
the FPGA cannot act as stand alone device because development tool and host
PC is always required. This is the method normally used during development
time.
In the developed board, there is a provision for both the configuration i.e.,
Active Serial configuration and JTAG configuration. The FPGA can also be
configured by methods such as Passive Serial configuration, etc.
Users will be familiar with all other interfacing devices in Fig. 2.1 such as
ADC and DAC so the architecture of them are not explained in detail.

2.4 Changes in the features


The following changes are incorporated in the Version 1.3 of the board:
• Number of analog channels is increased from 8 to 16
• DACs are current output DACs with increased speed
• USB transceiver controller placed on-board
• CAN transceiver on-board
The details of all the modules in the board is given in following section.

2.5 Developed FPGA board details


Developed FPGA contains following major components
1. Powersupply for the board:
The board requires +5V(digital) with DGND(digital ground), +5V(analog)
with AGND1(analog ground), and +15V and -15V with AGND2 for its
operation. +5V(analog) and +5V(digital) can also be give from the same
ground. All other levels such as 3.3V, 1.5V, 10V are generated on the
board itself. The connector J5 is the input for the powersupply. The
board is covered by a box, on the box a sticker indicating +5V, DGND,
+5VANA, AGND1 +15V, -15V, AGND2. A male connector is soldered
2.5 Developed FPGA board details 15

on the board. A female mating connector has to be used to give the power
supply. Verify the power connections carefully before giving power to the
board. The female mating connector is also provided with the board.
2. Cyclone FPGA:
This is the heart of the board in which all the algorithms are implemented.
The Cyclone IC details are given table below.

Name FPGA
Part No EP1C12Q240C8
Manufacturer ALTERA
No of Pins 240
Package PQFP
No of Logic elements 12,080
No of PLL 2
Maximum clock frequency using PLL 275 MHz
Power supply required for core 1.5V(VCCINT)
Power supply required for I/O 3.3V(VCCIO)
Power supply required for PLL circuit 1.5V(VCCPLL)
IC No in the schematic U1(page no 1)

3. Configuration device:
Configuration device helps in configuring the FPGA in Active Serial (AS)
mode of configuration. The details of configuration IC are shown in table.

Name EEPROM
Part No EPCS4I8N
Manufacturer ALTERA
No of Pins 8
Package SOIC
Power supply required 3.3V
IC No in the schematic U25(page no 9)

The board is designed for two ways of configuration. Jumpers in page


No.9 of schematic should be set appropriately for configuring FPGA in
JTAG mode or AS mode. For JTAG mode of configuration configuration
device is not required.
The jumper pin numbers are visible after soldering in the board. In
jumper placement to indicate pin.No 1 it will be marked with triangle as
shown in Fig. 2.5.
(A) JTAG mode of configuration:
This mode is usually used in development mode. The factory set
will be in JTAG mode. The Byteblaster -II cable has to be con-
nected to connector J4 (10 pin burgstick connector-page no 9) which
16 Analog and Digital Interfaces

Jumper

Pin No 1

Figure 2.5: Pins of the jumpers

is available at the end of the board. The board is covered by the box,
in that a suitable opening is left to connect Byteblaster-II cable to
connector J4. The cable can be connected and box can be closed.
Before removing or inserting the Byteblaster-II cable make sure that
powersupply is switched off. For JTAG mode, jumper settings are as
shown in table.

Three pin jumper JP1 1 and 2 short by jumper


Three pin jumper JP2 1 and 2 short by jumper
Three pin jumper JP3 1 and 2 short by jumper
Two pin jumper JP4 1 and 2 short by jumper
Three pin jumper JP5 1 and 2 short by jumper
Three pin jumper JP6 1 and 2 short by jumper
Two pin jumper JP7 1 and 2 open(don’t put jumper)
Two pin jumper JP8 1 and 2 open(don’t put jumper)
Two pin jumper JP9 1 and 2 open(don’t put jumper)
Two pin jumper JP10 1 and 2 open(don’t put jumper)
Two pin jumper JP11 1 and 2 open(don’t put jumper)

(B) AS mode of configuration:


This mode is used for stand alone mode of configuration. The Byte-
blaster -II cable has to be connected to connector J10 (10 pin burg-
stick connector-page no. 9) which is available at the near the EEP-
ROM (EPCS4IN) of the board. Please see the top legend of the board
to find the placement. This mode is normally used after development
to configure FPGA in stand alone mode. So once the development
is over box can be opened and the EEPROM can be loaded. After
loading the program power supply can be switched off and cable can
be removed. For AS mode jumper settings are shown in table.
2.5 Developed FPGA board details 17

Three pin jumper JP1 2 and 3 short by jumper


Three pin jumper JP2 2 and 3 short by jumper
Three pin jumper JP3 2 and 3 short by jumper
Two pin jumper JP4 1 and 2 open(don’t put jumper)
Three pin jumper JP5 2 and 3 short by jumper
Three pin jumper JP6 2 and 3 short by jumper
Two pin jumper JP7 1 and 2 short by jumper
Two pin jumper JP8 1 and 2 short by jumper
Two pin jumper JP9 1 and 2 short by jumper
Two pin jumper JP10 1 and 2 short by jumper
Two pin jumper JP11 1 and 2 short by jumper

4. Clock network in the board:


There are four dedicated clock pins in the cyclone device. User can use
different frequency of clocks if required and they need not be synchronised.
The clock network used in the board is shown in Fig. 2.6. In this board
user can use two different frequencies of clock. But in board two 20MHz
clock is used. The minimum input for PLL circuit in FPGA required is
20 MHz. Since both are two different clock crystals in board they are not
synchronised. They need not be synchronised also. The pin numbers in
which clock is connected is shown in Fig. 2.6.

U1
EP1C12Q240C8

20 Mhz U1:28 U1:152 20 Mhz


clock Dedicated clock(CLK0) Dedicated clock(CLK3) clock

U1:29 U1:153
Dedicated clock(CLK1) Dedicated clock(CLK2)

Figure 2.6: Clock interface to FPGA

5. Analog to digital converter:


Analog to digital converter is used to convert Analog signals to digital
signals. The details of ADC are shown in table.
18 Analog and Digital Interfaces

Name ADC
Part No AD7864 AS-1
Manufacturer ANALOG DEVICES
No of pins 44
Package MQFP
Power supply 5V
Input analog voltage levels -10V to +10V
No of channels 4
Conversion time 1.6µs per channel
IC no in schematic U2, U3, U4, U5

The interfacing circuits for ADC1(U2-page no 2 in schematic), ADC2(U3-


page no 3 in schematic), ADC3(U4-page no 4 in schematic) and ADC4(U5-
page no 5 in schematic)are shown in Fig. 2.7, Fig. 2.8, Fig. 2.9 and
Fig. 2.10. In the ADC interfacing diagram Pin no 11 is Hardware/software
select is connected to permanently ground for providing hardware selec-
tion of all analog input channels. Pin no7, Pin no8, Pin no9, Pin no8 are
connected to permanently 5V which are used for selection of all analog
input channel Simultaneously. So there is no need to select any analog
input channel through software programming of FPGA.
2.5 Developed FPGA board details 19

1 1DIR
U1:184 3 CONVST DB0 43 2 1B1 1A1 47 U1:166
U1:183 4 CS DB1 42 3 1B2 1A2 46 U1:167
U1:182 5 RD DB2 41 5 1B3 1A3 44 U1:168
+15V U1:183 6 WR DB3 40 6 1B4 1A4 43 U1:169
7 SL1 DB4 39 8 1B5 1A5 41 U1:170
50 ohm 50 ohm
8 SL2 U2 DB5 38 9 1B6 U8 1A6 40 U1:173
AIN1 IN1
+5V 9 SL3 AD7864AS−1 DB6 34 11 Buffer 38
1B7 1A7 U1:174
0.1uF
10 SL4 DB7 33 12 1B8 1A8 37 U1:175
−15V
11 H/S SEL DB8 32 13 2B1 2A1 36 U1:176
+15V IN1 DB9 31 14 2B2 2A2 35 U1:177
21 VIN1A
50 ohm 50 ohm DB10 30 16 2B3 2A3 33 U1:178
AIN2 IN2 DB11 29 17 2B4 2A3 32 U1:179
44 19 30
0.1uF IN2 EOC 2B5 2A3 U1:180
19 VIN2A 20 2B6 29
−15V 2A3
22 2B7 2A3 27
+15V IN3 23 2B8 2A3 26
16 VIN3A
24 2DIR
50 ohm 50 ohm
AIN3 IN3
IN4
0.1uF 14 VIN4A
1
−15V BUSY
2
FRSTDATA
+15V
AGND
50 ohm 50 ohm
AIN4 IN4
U1:* Means output from FPGA
0.1uF
U1:* Means input to FPGA
−15V
DGND

Figure 2.7: ADC1 interface to FPGA


20 Analog and Digital Interfaces

1 1DIR
U1:165 3 CONVST DB0 43 2 1B1 1A1 47 U1
U1:164 4 CS DB1 42 3 1B2 1A2 46 U1
U1:163 5 RD DB2 41 5 1B3 1A3 44 U1
U1:162 6 WR DB3 40 6 1B4 1A4 43 U1
+15V
7 SL1 DB4 39 8 1B5 1A5 41 U1
50 ohm 50 ohm 8 SL2 U3 DB5 38 9 1B6 U9 1A6 40 U1
AIN5 IN5 +5V AD7864AS−1 DB6 34 11 Buffer
9 SL3 1B7 1A7 38 U1
0.1uF 10 SL4 DB7 33 12 1B8 37 U1
1A8
−15V 11 H/S SEL DB8 32 13 2B1 2A1 36 U1
IN5 DB9 31 14 2B2 2A2 35 U1
+15V 21 VIN1A
DB10 30 16 2B3 2A3 33 U1
50 ohm 50 ohm
IN6 DB11 29 17 2B4 2A3 32 U1
AIN6
44 19 30
IN6 EOC 2B5 2A3 U1
0.1uF 19 VIN2A 20 2B6 29
2A3
−15V
22 2B7 2A3 27
IN7 23 2B8 2A3 26
+15V 16 VIN3A
24 2DIR
50 ohm 50 ohm
AIN7 IN7
IN8
0.1uF 14 VIN4A
1
BUSY
−15V 2
FRSTDATA
+15V
AGND
50 ohm 50 ohm
AIN8 IN8 U1:* Means output from FPGA
0.1uF
U1:* Means input to FPGA
−15V
DGND

Figure 2.8: ADC2 interface to FPGA


2.5 Developed FPGA board details 21

1 1DIR
U1:135 3 CONVST DB0 43 2 1B1 1A1 47 U1:117
U1:134 4 CS DB1 42 3 1B2 1A2 46 U1:118
U1:133 5 RD DB2 41 5 1B3 1A3 44 U1:119
+15V U1:132 6 WR DB3 40 6 1B4 1A4 43 U1:120
7 SL1 DB4 39 8 1B5 1A5 41 U1:121
50 ohm 50 ohm
AIN9 IN10 8 SL2 U4 DB5 38 9 1B6 U10 1A6 40 U1:122
+5V 9 SL3 AD7864AS−1 DB6 34 11 Buffer
0.1uF 1B7 1A7 38 U1:123
−15V 10 SL4 DB7 33 12 1B8 1A8 37 U1:124
11 H/S SEL DB8 32 13 2B1 2A1 36 U1:125
+15V IN9
21 VIN1A DB9 31 14 2B2 2A2 35 U1:126
50 ohm 50 ohm DB10 30 16 2B3 2A3 33 U1:127
AIN10 IN9 DB11 29 17 2B4 2A3 32 U1:128
44 19
0.1uF IN10 EOC 2B5 2A3 30 U1:131
−15V 19 VIN2A 20 2B6 2A3 29
22 2B7 2A3 27
+15V
IN11 23 2B8 2A3 26
16 VIN3A
50 ohm 50 ohm 24 2DIR
AIN11 IN11
0.1uF IN12
−15V 14 VIN4A
1
BUSY
2
+15V FRSTDATA

50 ohm 50 ohm
AIN12 IN12 AGND
0.1uF U1:* Means output from FPGA
−15V
U1:* Means input to FPGA

DGND

Figure 2.9: ADC3 interface to FPGA


22 Analog and Digital Interfaces

1 1DIR
U1:116 3 CONVST DB0 43 2 1B1 1A1 47
U1:114 4 CS DB1 42 3 1B2 1A2 46
+15V U1:113 5 RD DB2 41 5 1B3 1A3 44
U1:112 6 WR DB3 40 6 1B4 1A4 43
50 ohm 50 ohm
IN13 7 SL1 DB4 39 8 1B5 41
AIN13 1A5
8 SL2 U5 DB5 38 9 1B6 U11 1A6 40
0.1uF +5V AD7864AS−1 DB6 34 11 Buffer
−15V 9 SL3 1B7 1A7 38
10 SL4 DB7 33 12 1B8 1A8 37
+15V 11 H/S SEL DB8 32 13 2B1 2A1 36
IN14
50 ohm 50 ohm IN13
21 DB9 31 14 2B2 2A2 35
VIN1A
AIN14 DB10 30 16 2B3 2A3 33
0.1uF DB11 29 17 2B4 2A3 32
−15V 44 19 30
IN14 EOC 2B5 2A3
19 VIN2A 20 2B6 29
2A3
+15V IN15 22 2B7 27
2A3
50 ohm 50 ohm IN15 23 2B8 2A3 26
16 VIN3A
AIN15 24 2DIR
0.1uF
−15V IN16
IN16 14 VIN4A
1
BUSY
+15V
2
FRSTDATA
50 ohm 50 ohm
AIN16 AGND
0.1uF
−15V U1:* Means output from FPGA

U1:* Means input to FPGA

DGND

Figure 2.10: ADC4 interface to FPGA


2.5 Developed FPGA board details 23

6. Digital to Analog converter:


Digital to analog converter is used to convert Digital signals to Analog
signals. The details of the DAC are shown in the table.

Name DAC
Part No AD5447
Manufacturer Analog Devices
No of pins 24
Package SOIC
Power supply +10V ref
output analog voltage levels -10V to +10V
No of channels 2
Conversion time 0.8µs settling time
IC no in schematic U6 and U7(page no 5 and page no 6)

The interfacing circuits for DAC1 (U6-page no 6 in schematic) and DAC2


(U7-page no 7 in schematic) are shown in Fig. 2.11 and Fig. 2.12.
24 Analog and Digital Interfaces

18
U1:194 DB0
17
U1:193 DB1
16 2
U1:188 DB2 IOUTA IOUT1
15
U1:187 DB3
14 24
U1:186 DB4 IOUTB IOUT2
13
U1:185 DB5
12
U1:201 DB6
11
U1:202 DB7 U6
10 AD5447
U1:203 DB8
9
U1:206 DB9
8
U1:207 DB10
7
U1:208 DB11
U1:197 CS
U1:200 R/W
U1:213 CH_A/B

U1:* output from FPGA

Figure 2.11: DAC1 interface to FPGA


2.5 Developed FPGA board details 25

18
U1:194 DB0
17
U1:193 DB1
16 2
U1:188 DB2 IOUTA IOUT1
15
U1:187 DB3
14 24
U1:186 DB4 IOUTB IOUT2
13
U1:185 DB5
12
U1:201 DB6
11
U1:202 DB7 U7
10 AD5447
U1:203 DB8
9
U1:206 DB9
8
U1:207 DB10
7
U1:208 DB11
U1:195 CS
U1:196 R/W
U1:213 CH_A/B

U1:* output from FPGA

Figure 2.12: DAC2 interface to FPGA


26 Analog and Digital Interfaces

7. Digital I/O signals:


There are totally 60 I/O pins provided for the user. All the I/O pins
are taken through a bi-directional buffer. So according to the direction
bit given by FPGA to buffer the I/O signals becomes input or output
to FPGA. Input digital signals to the board should be given in 5V level
and output digital signal from the board will also be at 5V level. The
following are the digital I/O signals that can be used by user for the
applications.
2.5 Developed FPGA board details 27

The first 16 I/O signals are shown in Fig. 2.13.

3.3 V side 5V side


U1:214 1 1DIR
U1:215 47 1A1 1B1 2 IO1
U1:216 46 1A2 1B2 3 IO2
U1:217 44 1A3 1B3 5 IO3
U1:218 43 1A4 1B4 6 IO4
U1:219 41 1A5 1B5 8 IO5
U1:222 40 1A6 1B6 9 IO6
U1:223 38 1A7 1B7 11 IO7
U26
U1:224 37 1A8 Buffer 1B8 12 IO8
U1:237 24 2DIR
U1:225 36 2A1 2B1 13 IO9
U1:226 35 2A2 2B2 14 IO10
U1:227 33 2A3 2B3 16 IO11
U1:228 32 2A4 2B4 17 IO12
U1:233 30 2A5 2B5 19 IO13
U1:234 29 2A6 2B6 20 IO14
U1:235 27 2A7 2B7 22 IO15
U1:236 26 2A8 2B8 23 IO16

U1:224=0 IO1 to IO8 Input to FPGA


U1:224=1 IO1 to IO8 Output from FPGA
U1:237=0 IO9 to IO16 Input to FPGA
U1:237=1 IO9 to IO16 Output from FPGA

Figure 2.13: Details of buffer1 I/O lines of the FPGA board


28 Analog and Digital Interfaces

The next 16 I/O signals are shown in Fig. 2.14

3.3 V side 5V side


U1:238 1 1DIR
U1:239 47 1A1 1B1 2 IO17
U1:240 46 1A2 1B2 3 IO18
U1:2 44 1A3 1B3 5 IO19
U1:3 43 1A4 1B4 6 IO20
U1:4 41 1A5 1B5 8 IO21
U1:5 40 1A6 1B6 9 IO22
U1:6 38 1A7 1B7 11 IO23
U27
U1:7 37 1A8 Buffer 1B8 12 IO24
U1:18 24 2DIR
U14:8 36 2A1 2B1 13 IO25
U1:11 35 2A2 2B2 14 IO26
U1:12 33 2A3 2B3 16 IO27
U1:13 32 2A4 2B4 17 IO28
U1:14 30 2A5 2B5 19 IO29
U1:15 29 2A6 2B6 20 IO30
U1:16 27 2A7 2B7 22 IO31
U1:17 26 2A8 2B8 23 IO32

U1:238=0 IO16 to IO24 Input to FPGA


U1:238=1 IO16 to IO24 Output from FPGA
U1:8=0 IO25 to IO32 Input to FPGA
U1:8=1 IO25 to IO32 Output from FPGA

Figure 2.14: Details of buffer2 I/O lines of the FPGA board


2.5 Developed FPGA board details 29

The next 16 I/O signals are shown in Fig. 2.15

3.3 V side 5V side


U1:64 1 1DIR
U1:65 47 1A1 1B1 2 IO33
U1:66 46 1A2 1B2 3 IO34
U1:67 44 1A3 1B3 5 IO35
U1:68 43 1A4 1B4 6 IO36
U1:73 41 1A5 1B5 8 IO37
U1:74 40 1A6 1B6 9 IO38
U1:75 38 1A7 1B7 11 IO39
U28
U1:76 37 1A8 Buffer 1B8 12 IO40
U1:87 24 2DIR
U1:77 36 2A1 2B1 13 IO41
U1:78 35 2A2 2B2 14 IO42
U1:79 33 2A3 2B3 16 IO43
U1:82 32 2A4 2B4 17 IO44
U1:83 30 2A5 2B5 19 IO45
U1:84 29 2A6 2B6 20 IO46
U1:85 27 2A7 2B7 22 IO47
U1:86 26 2A8 2B8 23 IO48

U1:64=0 IO33 to IO40 Input to FPGA


U1:64=1 IO33 to IO40 Output from FPGA
U1:87=0 IO41 to IO48 Input to FPGA
U1:87=1 IO41 to IO48 Output from FPGA

Figure 2.15: Details of buffer3 I/O lines of the FPGA board


30 Analog and Digital Interfaces

The next 8 I/O signals are shown in Fig. 2.16

3.3 V side 5V side


U1:41 2 1DIR
U1:43 3 1A1 1B1 21 IO49
U1:44 4 1A2 1B2 20 IO50
5 U29 19
U1:45 1A3 1B3 IO51
U1:46 6 1A4 Buffer 1B4 18 IO52
U1:47 7 1A5 1B5 17 IO53
U1:48 8 1A6 1B6 16 IO54
U1:49 9 1A7 1B7 15 IO55
10 1A8 1B8 14

U1:41=0 IO49 to IO56 Input to FPGA


U1:41=1 IO49 to IO56 Output from FPGA

Figure 2.16: Details of buffer4 I/O lines of the FPGA board


2.6 USB Interface 31

The next 8 I/O signals are shown in Fig. 2.17

3.3 V side 5V side


U1:19 2 1DIR
U1:20 3 1A1 1B1 21 IO56
U1:21 4 1A2 1B2 20 IO57
5 U34 19
U1:23 1A3 1B3 IO58
U1:38 6 1A4 Buffer 1B4 18 IO59
U1:39 7 1A5 1B5 17 IO60
8 1A6 1B6 16
9 1A7 1B7 15
10 1A8 1B8 14

U1:19=0 IO49 to IO56 Input to FPGA


U1:19=1 IO49 to IO56 Output from FPGA

Figure 2.17: Details of buffer5 I/O lines of the FPGA board

8. Connectors: In the FPGA board mainly two types of connectors are given:

(A) Analog connector: J22 is a 24 pin right-angled connector which is


compatible with J44 connector of interface board. This is used for
giving 16 analog input through interface board and taking out analog
output of DAC to the interface board.
(B) Digital IO connector: J2 and J3 are the digital IO connector. J2
is the 36 pin bergstick connector and J3 is the 36 pin right-angled
connector which is compatible with J43 connector of interface board.

2.6 USB Interface

The Universal Serial Bus (USB) has evolved to the standard interconnect be-
tween computers and peripherals. It can operate at very high speed rates(12Mb/s
to 480Mb/s). USB1T11AMTCX (universal Serial Bus Transceiver) is used as
a USB. It is capable of transmitting and receiving serial data at both full
speed (12Mb/s) and low speed (1.5Mb/s) data rates. USB interfacing circuit
diagram(as shown in 2.18) and I/O pins assignment is shown in Table 4.7
32 Analog and Digital Interfaces

+3.3V
+3.3V +3.3V
+3.3V 1.5K 10K
1.5K
J6 +3.3V J7 J8 J9
321 1 1 1
2 2
2 3
0.1uF
1 MODE VCC 14
U1:60 2 OE VMO/FSEO 1213 U1:58
U1:61 3 RCV VPO 11 U1:59
U1:62 4 D+ D+_USB
5 VP U33
U1:63 VM D− 10 D−_USB
6 SUSPEND SPEED 9 J21
7 GND NC 8 1
D−_USB 2
USB1T11AMTCX D+_USB 3
4
154−4100
USB_TYPE−B_CONNECTOR

Figure 2.18: Circuit diagram of USB Interface.

Table 2.1: Pin Assignment of USB Interface


Name Pin No FPGA Status
VMO/FESO U1:58 output
VPO U1:59 output
OE U1:60 output
RCV U1:61 input
VP U1:62 input
VM U1:63 input

2.6.1 USB connector


In the FPGA board Type-B connector(J21, page no 13 in schematic) is pro-
vided for USB connection. For proper interfacing between FPGA board and
computer(PC) USB cable is required. This cable contain one side is Type-A
port for PC connection and another side Type-B port for FPGA connection.

2.6.2 Jumpers setting


Before using a USB, some jumpers setting is required. J6, J7, J8, J9 jumpers
(shown in page no 13 in schematic) are assigned for USB operation.

2.7 CAN Interface


Controller Area Network(CAN) is a serial network that was originally designed
for the automotive industry, but has also become a popular bus in industrial
automation as well as other application like controlling and monitoring opera-
tion between devices. In this project CAN is using for controlling other FPGA
operation by one server FPGA. It is two wire, half duplex, high speed network
2.8 Conclusion 33

Table 2.2: Jumpers setting for USB Interface


Three pin jumper J6 1-2 short and 2-3 open Mode selection
Three pin jumper J6 1-2 open and 2-3 short No mode selection
Three pin jumper J9 1-2 short and 2-3 open Speed selection
Three pin jumper J9 1-2 open and 2-3 short No Speed selection
Two pin jumpers J7 and J8 1-2(J7) short, 1-2(J8) open High speed
Two pin jumpers J7 and J8 1-2(J7) open, 1-2(J8) short Low speed

Table 2.3: Pin Assignment of CAN Interface


Buffer Direction Bit FPGA Pin I/O Signal
U1:18 = 1 U1:17 IO32 TXD (transmit data)
U1:19 = 0 U1:20 IO56 RXD (Receive data)

system. CAN interfacing circuit diagram(as shown in Fig 2.19) and I/O pins
assignment is shown in Table 4.8
120 ohm
120 ohm

IO32 100K
0.1uF 1 TXD RS 5
2 GND CANH 6
3 1
VCC CANL 7 2
+5V 4 RXD SHDN 8 3
IO56 4
MAX3050ASA 5
6
30pF 100nF 7
8
RJ45 CONNECTOR

Figure 2.19: Circuit diagram of CAN Interface.

2.7.1 CAN connector


RJ45 connector is provied for CAN connection. Which is shown in page no 15
of schematic by name RJ1.

2.8 Conclusion
In this chapter, the minimum requirements of the digital controller for control-
ling power electronic systems with FPGA is explained. The details of the devel-
oped board is also given. In the following chapter the usage of the Quartus-II
tool (Design tool of ALTERA for programming FPGA) is explained. With
this design tool how to program the developed FPGA board is explained in
the next chapter.
34 Analog and Digital Interfaces
Chapter 3

Quartus System Software

3.1 Introduction
In this chapter, the usage of Quartus-II (a design tool of ALTERA) is ex-
plained. The required design is done using this design tool, the final compiled
output file is used for programming the FPGA using byteblaster-II cable or
USB-blaster cable. The usage of Quartus-II tool and programming the FPGA
is explained through a small example in this chapter. The example taken here
is for generating chopper PWM with constant reference. The following section
explains the design methodology of FPGA using Quartus-II.
36 Quartus System Software

3.2 Design methodology


1. Step 1:
Open the Quartus-II software. Go to ” File ” menu and click on ” Open
a new project wizard ”. The window shown in Fig. 3.1 appears. In that
type the working directory of the project. Type the project name and
top level entity name. Top level entity is the name of the design file used
to compile the project. The usage of top level entity structure will be
understood later, so at present proceed with same name as project name
itself.

Figure 3.1: Window for opening new project


3.2 Design methodology 37

2. Step 2:
It may display ” folder does not exist ” window as shown in Fig. 3.2, so
click ” Yes ” to create the folder of the name ” chopperpwm ”. After that
click ” Next ” to proceed.

Figure 3.2: Window showing folder does not exist


38 Quartus System Software

3. Step 3:
Next window will appear as shown in Fig. 3.3. As we dont have any past
design libraries to include click ” Next ” to proceed.

Figure 3.3: Window for adding user library


3.2 Design methodology 39

4. Step 4:
Next window will appear as shown in Fig. 3.4.In this window select the
device used on the target board. The Family should be ” CYCLONE ”,
the specific device will be ” EP1C12Q240C8 ”, this is of PQFP package,
Speed grade of ” 8 ”, Pin count is of 240.

Figure 3.4: Window for specifying FPGA device


40 Quartus System Software

5. Step 5:
Next window will appear as shown in Fig. 3.5. As we are not going to
use any other tool, click ” Next ” to proceed.

Figure 3.5: Window for adding EDA tools


3.2 Design methodology 41

6. Step 6:
Next window will appear as shown in Fig. 3.6. This shows the summary
of the project that we have started. Click ” Finish ” to end the project
wizard.

Figure 3.6: Window for summary of the project


42 Quartus System Software

7. Step 7:
Go to ” File ” menu and click ” New ” to create the design file, the win-
dow will appear as shown in Fig. 3.7. Then clik on” Block diagram or
schematic file ” to open new block diagram design file.

Figure 3.7: Window for opening new blockdiagram/schematic file


3.2 Design methodology 43

8. Step 8:
The block diagram file as shown in Fig. 3.8 will appear. In that to get
various components click ” Symbol tool ” as shown in Fig. 3.8.

Figure 3.8: Icon for symbol tool


44 Quartus System Software

9. Step 9:
For the Project let us take a counter. After clicking on symbol tool a
windows as shown in Fig. 3.9 appears. In the ” Name ” column type
” lpm counter ”. Click ” ok ” on the window.

Figure 3.9: Window for selecting counter


3.2 Design methodology 45

10. Step 10:


Next window as shown in Fig. 3.10 appears. Select ” AHDL ”(Altera
Hardware Description Language) for the output file to create. If you are
taking first time the counter symbol the name of the output file would be
” lpm counter0 ”. Click ” Next ” to proceed. In the Fig. 3.10 it is shown as
” lpm counter1 ” because i have taken second time counter using symbol
tool.

Figure 3.10: Window for selecting type of HDL code and symbol name
46 Quartus System Software

11. Step 11: Next window will appear as shown in Fig. 3.11. Let us take
” 12 ” bits as the no of bits for the ” lpm counter ”. select the options for
the counting as ” Up only ”. Click ” Next ” to proceed.

Figure 3.11: Window for selecting no of bits in counter and counting mode
3.2 Design methodology 47

12. Step 12:


Next window will appear as shown in Fig. 3.12. Select ” Plain binary ”
as the counting option. No other additional options such as ” Clock en-
able ”,” Carry-in ”,” Carry-out ”,” Count enable ” etc are not required now
for the present project.

Figure 3.12: Window for selecting up counting or down couting mode


48 Quartus System Software

13. Step 13:


Window as shown in Fig. 3.13 will appear. Click ” Next ” as no other
option for the counter is required for the project.

Figure 3.13: Window for selecting other options in counter


3.2 Design methodology 49

14. Step 14:


Window as shown in Fig. 3.14. Click ” Finish ” to end the wizard.

Figure 3.14: Finish window in selecting counter


50 Quartus System Software

15. Step 15:


After ending the wizard an LPM COUNTER as shown in Fig. 3.15 will
appear in block diagram design file.

Figure 3.15: Counter in block diagram file


3.2 Design methodology 51

16. Step 16:


Before proceding with adding other components save the file. Click the
” Save ” symbol and the a window as shown in Fig. 3.16 will appear. Save
this file with top level entity name ” chopper ”. If you are saving with
any other name you should change the top level entity before compiling
the project. Right now save it as ” chopper ” which we have given as top
level entity name in the new project wizard.

Figure 3.16: Window for saving block diagram file


52 Quartus System Software

17. Step 17:


Now again using symbol tool bring other components. Now click on
symbol tool to bring ” Input pin ” to clock of the counter. You will see
a window as shown in Fig. 3.17. Type ” input ” in the ” Name ” column.
Click ” ok ” to bring to block diagram design file.

Figure 3.17: Symbol for input


3.2 Design methodology 53

18. Step 18:


By using symbol tool bring lpm compare in the similar way as lpm counter.
In that ” dataa ” and ” datab ” should be in 12 bits. For comparison select
” aleb ” and also select ” unsigned ” comparison in the options. No other
options would be required for the lpm compare.
Similarly bring lpm constant using symbol tool. select no of bits as 12
bits. use constant value as ” 1024 ”.
Using Symbol tool again bring ” output ” from the library.
Interconnect the system as shown in Fig. 3.18.
Double click on the input and output pin and change their name as
” clock ” and ” pwm ” as shown in Fig. 3.18

Figure 3.18: Block diagram of the system


54 Quartus System Software

19. Step 19:


To start analysis synthesis go to the window as shown in Fig. 3.19. This
option is available in ” Processing ” menu.

Figure 3.19: Window to start analysis and synthesis


3.2 Design methodology 55

20. Step 20:


Functional simulation has to be done to verify the functionality of the
model. So to do simulation the functional simulation netlist has to be
generated. The option for that available in ” processing ” menu as shown
in Fig. 3.20

Figure 3.20: Window to start functional simulation netlist


56 Quartus System Software

21. Step 21:


To do simulation we need to give input to the model.This is given using
Vector waveform file. To create new vector waveform file, goto ” File ”
menu and click ” new ”. The window as shown in Fig 3.21 will appear. In
that select ” other files ” to create vector waveform file. The window as
shown in Fig 3.21. Click ” ok ” to proceed.

Figure 3.21: Window for creating vector waveform file


3.2 Design methodology 57

22. Step 22:


In the vector waveform file to give ” input ” double click on the screen
in ” Name ” a window as shown in Fig. 3.22 will appear. In that type
” clock ” and click ok. And once again double click on the scree same
window as shown in Fig. 3.22 will appear. In that type ” pwm ” and click
ok. In this example ” clock ” is an input and ” pwm ” is an output.

Figure 3.22: Window for giving input and output to vector waveform file
58 Quartus System Software

23. Step 23:


Save the Vector Waveform File you have created for giving input to the
simulation. To save the file a window as shown in Fig. 3.23 will appear.

Figure 3.23: Window for saving vector waveform file


3.2 Design methodology 59

24. Step 24:


Go to ” Assignment ” men go to ” Settings ”, the following window shown
in Fig. 3.24. In that set the simulation as Functional simulation. And
Browse and give the input file as ” chopper.vwf ”. Specify the end time
of the simulation as 1ms and click ” ok ”.

Figure 3.24: Window for simulator settings


60 Quartus System Software

25. Step 25:


End time has to be set at two places,one already we have set. For other
open the Vector waveform file. Go to ” Edit ” menu in which End time
can be set to 1ms. The window for that is shown in following Fig. 3.25.
Turn next page for the Figure.
3.2 Design methodology 61

Figure 3.25: Window for end time setting


62 Quartus System Software

26. Step 26:


Next to simulate we have to give value for the ” clock ” input. In ” Vector
waveform file ” right click on ” clock ” input and give the value as shown
in Fig. 3.26. Type the value as 50ns(20MHz).

Figure 3.26: Window for giving clockvalue


3.2 Design methodology 63

27. Step 27:


To simulate the system go to menu as shown in Fig. 3.27 and press ” start
simulation ”.

Figure 3.27: Window for starting simulation


64 Quartus System Software

28. Step 28:


Simulated waveform is shown in Fig. 3.28. The counter peak value for
12 bit will be 4096, and constant value is 1024, on comparing both with
condition ” aleb ” it produces 25% duty cycle, the time period will be
(4096*50ns) 204.8µs

Figure 3.28: Simulated waveform


3.2 Design methodology 65

29. Step 29:


Output from the board is taken through buffer. To specify the buffer
direction one more output pin of FPGA is required. So use symbol tool
bring one ” output ” symbol and rename as ” dir ”. using symbol tool, type
” vcc ” and bring one ” vcc ” symbol to the design file. connect ” vcc ”
symbol to output pin ” dir ”. The complete system should is shown in
Fig. 3.29.

Figure 3.29: Full system


66 Quartus System Software

30. Step 30:


Before compiling the program, the pin no for the input and output has to
be assigned. Right click on the input pin ” clock ”. The window as shown
in Fig. 3.30 will appear. click on ” Locate in assignment editor ” to assign
the pin.

Figure 3.30: Window for assigning pin no to clock pin


3.2 Design methodology 67

31. Step 31:


The window as shown in Fig. 3.31. The pin no 28 should be assigned,
because 20MHz clock is connected to the ” pin no 28 ” of the cyclone
device physically in the board. This details are available in chapter-2.

Figure 3.31: Assign pin no to clock input pin


68 Quartus System Software

32. Step 32:


Right click on the output pin ” pwm ”. The window as shown in Fig. 3.32
will appear. click on ” Locate in assignment editor ” to assign the pin.

Figure 3.32: Window for assigning pin no to pwm pin


3.2 Design methodology 69

33. Step 33:


The window as shown in Fig. 3.33. The pin no 65 can be assigned, because
it is one of the general purpose I/O in the board. This details are available
in chapter-2.

Figure 3.33: Assign pin no to pwm pin


70 Quartus System Software

34. Step 34:


Similarly assign pin no for output pin ” dir ”. Since we have assigned
Pin No 65 to output pin PWM, we should assign Pin No 64 for the
” dir ” output. The system with all pins appears as shown in Fig. 3.34.
This depends on the buffer associated with the I/O pin. The details are
available in chapter 2.

Figure 3.34: System with all pins assigned


3.2 Design methodology 71

35. Step 35:


In the assignment menu go to device settings, the window is shown in
Fig. 3.35

Figure 3.35: To change the device settings


72 Quartus System Software

36. Step 36:


In the window is shown in Fig. 3.36. A menu as shown in Fig. 3.36 will
appear. Click ” Unused pin ” pin option.

Figure 3.36: Device settings menu


3.2 Design methodology 73

37. Step 37:


In the ” Reserve all unused pin ” section . Please select option as ” As inputs,tristated ”.
Make sure that this first option is selected. The default option will be
” As outputs driving ground ”. The default option will heat up the device
and it may get damaged. Always before programming make sure that
the option ” As inputs,tristated ” is selected. In every project this setting
should be changed when you create the project so that you wont forget
this point. The setting to be selected is shown in Fig. 3.37

Figure 3.37: Unused pins setting


74 Quartus System Software

38. Step 38:


Now start compilation by going to the menu as shown in Fig. 3.38. After
compilation you will get the report of no of logic elements consumed,no
of pins consumed etc.

Figure 3.38: Start compilation


3.2 Design methodology 75

39. Step 39:


Now to start programming go to the window by using the menu as shown
in Fig. 3.39

Figure 3.39: Start programming


76 Quartus System Software

40. Step 40:


The window as shown in Fig. 3.40 will appear.Configure the driver ac-
cording to the instructions given in the following link.
http://www.altera.com/support/software/drivers/
Click on Hardware setup and select BYTE BLASTER. After configuring
driver only this can be done. Then program it using Program/Configure
option. This completes the project of chopperpwm. On completing this
successfully we can see PWM pulses in oscilloscope.

Figure 3.40: Programming


Chapter 4

Interface Board for Real-Time


Simulator

4.1 Introduction
The FPGA board is designed in a generic way so that we can develop cus-
tom applications on it. For each application, we need to design an interface
properly. In this chapter an interface card which is designed for the real time
simulation application is discussed.
A Real Time System Simulator (RTSS) need to receive analog and digital
signals and output the processed signals. It is intended to have a user interface
so that inputs can be given and various system parameters can be changed
without the intervention of a PC based development System, once the model
development is complete. This feature needs a LCD display, keypad and var-
ious I/O pins. In this chapter other facilities such as serial port interfaces
RS232 can be added..

4.2 Analog and digital interface


This section is required for giving analog and digital I/O signals. It contains
various test points for measuring analog input and DAC output of FPGA
board. Details of various connector is shown in Table 5.1 and Table 5.2
78 Interface Board for Real-Time Simulator

Table 4.1: Description of input connectors and test points


Connector No Type Used for Single pin test point
J22 2-Pin Powermate Ain1 J1
J23 2-Pin Powermate Ain2 J2
J24 2-Pin Powermate Ain3 J3
J25 2-Pin Powermate Ain4 J4
J26 2-Pin Powermate Ain5 J5
J27 2-Pin Powermate Ain6 J6
J28 2-Pin Powermate Ain7 J7
J29 2-Pin Powermate Ain8 J8
J30 2-Pin Powermate Ain9 J9
J31 2-Pin Powermate Ain10 J10
J32 2-Pin Powermate Ain11 J11
J33 2-Pin Powermate Ain12 J12
J34 2-Pin Powermate Ain13 J13
J35 2-Pin Powermate Ain14 J14
J36 2-Pin Powermate Ain15 J15
J37 2-Pin Powermate Ain16 J16
J47 2-Pin Relaymate +5V ——
J38 Single pin Aout1 J38
J39 Single pin Aout3 J39
J40 Single pin Aout2 J40
J41 Single pin Aout4 J41
J18 Single pin AGND J18
J19 Single pin AGND J19
J21 Single pin AGND J21
J48 Single pin AGND J48
SGND1 Single pin DGND SGND1
SGND2 Single pin DGND SGND2
SGND3 Single pin DGND SGND3
SGND4 Single pin DGND SGND4

Table 4.2: Digital IO connectors details


Connectors No Type Used for
J49 8-Pin male connector Keypad
J46 16-Pin female connector LCD display
J50 DB-9 female connector RS232 interface
J44 24-Pin Right angle connector ADC and DAC interface
J43 36-Pin Right angle connector Digital I/O
J45 28-Pin Burgstic connector Digital I/O
4.3 LCD and Keypad Interface 79

4.3 LCD and Keypad Interface


4.3.1 LCD Interface
The LCD is interfaced as a write only device, for simplicity. There is no need
to read from the internal registers of the LCD to check whether it is ready or
not. Instead, sufficient delays will be incorporated in writing data to the LCD.
LCD mainly using for showing parameters value like voltage, current, power,
speed etc. These parameters controlled by keypad.

Circuit Diagram is shown in Fig 5.1).

IO41 7 D0
IO42 8 D1
IO43 9 D2
10 D3 2 Line x 16 Charcter
IO44 11 D4
IO45 LCD Display
IO46 12 D5
13 D6
IO47 14 D7
IO48
E R/W RS GND VO VCC
6 5 4 1 2 3 +5V

10K
IO39 IO38 IO37
Figure 4.1: Circuit diagram of LCD interface.

Hardware pin description is shown in Table 4.3

Table 4.3: Hardware Pin Description of LCD


No Symbol No Functions
1 VSS Ground
2 VCC +5V Supply for logic circuit
3 V0 +5V Supply for driving the LCD
4 RS Data/Instruction select
5 R/W Read/Write operation
6 E1 Enable signal for row 1
7-14 DB0-DB7 Data Bus
15 E2 Enable signal for row 2
16 NC Not connected
80 Interface Board for Real-Time Simulator

I/O Pin allocation for LCD is shown in Table 4.4

Table 4.4: Pin Assignment for LCD


Buffer Direction Bit FPGA Pin I/O Signal
U1:64 = 1 73 IO37 LCD Register Select
74 IO38 LCD R/W
75 IO39 LCD Enable
U1:87 = 1 77 IO41 LCD D0
78 IO42 LCD D1
79 IO43 LCD D2
82 IO44 LCD D3
83 IO45 LCD D4
84 IO46 LCD D5
85 IO47 LCD D6
86 IO48 LCD D7

4.3.2 Keypad Interface


The keypad is a 4x4 matrix keypad, which can bring advanced functionality.
For simple applications, however only four basic keys will sufficient.
4x4 Matrix diagram(as shown in Fig 5.2) and I/O pin details is shown in
Table 4.5

FPGA O/P or Keypad I/P

IO33 4 3 2 1
Keypad O/P or FPGA I/P

IO34 8 7 6 5

IO35 12 11 10 9

IO39 16 15 14 13

IO52 IO51 IO50 IO49


Figure 4.2: 4x4 Matrix diagram of Keypad
4.3 LCD and Keypad Interface 81

Table 4.5: Pin Assignment for Keypad


Buffer Direction Bit FPGA Pin I/O Signal
U1:41 = 0 43 IO49 From Key-pad Col (i/p)
44 IO50
45 IO51
46 IO52
U1:64 = 1 65 IO33 To Key-pad Row scan (o/p)
66 IO34
67 IO35
68 IO36

4.3.3 Digital logic implementation of LCD


Digital logic of LCD display requires two main section:
1. LCD Initialization.
2. Character display.

LCD Initialization

For displaying various characters on the LCD, firstly LCD has to be initialized
properly. This is done by sending some basic instructions with appropriate
delay. After sending each instruction, data corresponding to the displaying
character can be sent. This logic is based on 3.5ms delay for each instruction
and data. LCD delay logic mainly consists of two counters, DFF and various
logic gates. First counter is used for genrating a 3.5ms clock signal which
enables the operation of inbuilt microcontroller of LCD. Second counter is
used for generating the selection lines of multiplexer and this counter output
width is depends on number of displaying character. For example displaying
of 12 characters, 16x1 multiplexer requires in which 12 input lines has to be
used for 12 characters and 4 input lines used for 4 initialization instruction. So
based on that, a 4 bit counter is required. DFF and count-stop logic section
is used for keeping all characters on display. When all the selection lines are
equal to logic ’1’ then count stop output will also be logic ’1’, which disable
the operation of microcontroller for new character display. Logic diagram is
shown in Fig 5.3

Character display

This logic mainly deals with different type of instructions and different char-
acter display. Various instructions used for LCD are as follows:
1. Function Set: It is required for operating the LCD in 1-line mode or 2-
line mode and setting the font size to 5x7 or 5x10. Its hexadecimal values
have to be in between 30h to 3Fh.
82 Interface Board for Real-Time Simulator

s(n)
Count_stop
s(n−1)
s(1)
s(0)

clk clk_out[n..0] −−−


Count_stop

mux_sel[n..0]
Counter

Din Dout
clk DFF Enable
clk_out15
clk_out16

clock clk_out[24..0] −
Counter

Figure 4.3: Logic diagram of instruction and data delay for LCD.

2. Entry Mode Set: It is used for operation of entire shift on or off and
displaying the characters in increment mode or decrement mode. Its
hexadecimal values are from 04h to 07h.
3. Display Clear: After execution of this instruction entire display will be
clear. Its value is 01h.
4. Display on-off control: Its mainly used for display on-off, cursor display
on-off and cursor blink on-off. Its range from 80h to F0h.
After sending all instruction data has to be sent as per requirement. In LCD
we can display any alphabetic letter, various numbers and spacial characters
etc. This logic mainly consists of a multiplexer which input and selection line
depends on number of displaying character. Display of any character requires
three control signals, viz., Register select, Enable and Read/Write. Register
select has to logic ’0’ for sending instruction and logic ’1’ for sending data.
Enable will be decided by the delay section logic and it has to come with
clock. Read/write data has to be always logically ’0’ for writing the particular
charter on the LCD screen. Logic diagram is shown in Fig 5.4
4.3 LCD and Keypad Interface 83

char12[8..0] i16[8..0]
char11[8..0] i15[8..0]
−−−−−

16x1
MUX
LCD_data[8..0]
char3[8..0] i7[8..0]
char2[8..0] i6[8..0]
char1[8..0] i5[8..0]
INT4[8..0] i4[8..0]
INT3[8..0] i3[8..0]
INT2[8..0] i2[8..0]
INT1[8..0] i1[8..0] Register_select
sel[3..0]

stop
Count_stop mux_sel[3..0] Read/Write_bar
LCD_Dealy
Logic Section stop
clk
clock
LCD_Enable

Figure 4.4: Logic diagram of LCD display.


84 Interface Board for Real-Time Simulator

4.3.4 Interface of Keypad

The keypad is wired in matrix form with a switch at the intersection of each
row and column. Pressing a key establishes a connection between a row and
column. Interfacing of sixteen different keys requires four FPGA O/P lines
(arranged in rows) which will be used as a input of keypad and four FPGA I/P
lines (arranged in column) which will be acting as a output lines of key matrix.
The logic circuits are implemented in the FPGA. Digital Implementation of
keypad requires two main sections:
1. Scanning Logic section.
2. De-bouncing Section.

Scanning

It mainly consists of counter, decoder and four AND logic gates. Logic opera-
tion initialized by clock which is the input of counter. At every active edge of
clock, counter enables and gives the outputs ”00”, ”01”, ”10”, ”11”, ”00” and
so on. Counter output is the input of 2x4 decoder. From the corresponding
output of counter, only one decoder output line will be high at a time. Now if
user press any one key then corresponding to that column number will high,
which will be logically ANDed with the particular output of the decoder. Logic
high output of the AND gate shows scanning of particular key. In this logic,
very high-frequency clock is used and key-press time is very high compared to
the clock period. Logical AND operation avoids wrong key detection. Logic
diagram is shown in Fig 4.5

bit0 Scan1
Clock 2 Bit 2X4 Scan2 FPGA
Counter Decoder Scan3 O/P
bit1 Scan4
Key_collumn_no
Key1
Scan1

key2
Scan2
key3
Scan3
Key4
Scan4

Figure 4.5: Logic diagram of Keypad Scanning Section.


4.3 LCD and Keypad Interface 85

De-bouncing

In the process of scanning the keypad to determine which key is pressed, the
scanner must take contact bounce into account. When a mechanical switch is
closed or opened, the switch contact will bounce, causing noise in the switch
output. The contact may bounce for several milliseconds before it settles down
to its final position. This bouncing problem may be avoided by two different
methods:
1. Sequential logic: Truth table for sequential logic is shown in Table 4.6

Table 4.6: Truth table of sequential de-bouncing


Present State Input Next State
0 0 0
0 1 1
1 0 1
1 1 1

With reference to the truth table it can be concluded that the next state
is the logical OR operation of Input and Present State. De-bouncing logic
mainly consists of counter, comparator, OR gate and DFF as shown in
Fig 4.6. Counter output is connected to first input of comparator and
other input is set to decimal equivalent 1. Initially comparator output
’alessb’ set to one until counter gets the clock. DFF’s output initially
set to zero because it is asynchronously clearing by comparator output.
Input of the DFF is through the logical OR operation of Present state and
scanning section output for particular key. By this arrangement if once in
a while DFF output becomes logic ’1’ then it will remain ’1’, irrespective
of key bouncing.
2. SR Latch: Truth table for SR latch is shown in Table 4.7.

Table 4.7: Truth table for SR latch


Set Reset Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 Q’(t)

In this logic ’Set’ input is connected to the key and ’Reset’ is kept open.
According to the truth table if any key pressed then ’set’ input will be
high and output Q(t+1) will be logic ’1’ and now if bouncing occurs then
from the first condition output will remains present state i.e. logic ’1’.
Logic diagram is shown in Fig 4.7.
86 Interface Board for Real-Time Simulator

out out
Din Dout
key_no DFF
clk
clear

clear
clock
2 Bit S[1..0] a[1..0]
Enable Counter 2 Bit alessb clear
Comparator
b=1

Figure 4.6: Logic diagram for De-bouncing.

Set
Q(t)

Q(t)
Reset
Figure 4.7: Logic diagram for De-bouncing by SR Latch.

4.3.5 Control variable selection by single key


Only one key is sufficient for changing the control variable. This logic consists
of counter, SR latch and multiplexer. Counter and multiplexer selection de-
pend on the number of variables, for example if number of variables is two,
then a single bit counter and 2x1 multiplexer is sufficient. Counter output will
act as a control signal for multiplexer. Now if user presses the dedicated key
then counter changes state and the particular control variable will be selected
through the multiplexer. Logic diagram for two variables voltage and speed is
shown in Fig 4.8.
4.3 LCD and Keypad Interface 87

Logic digram for two variables voltage and speed is shown in Fig 4.8

voltage
i0
var_key 2x1 variable_out
speed mux
i1 sel

clk_out20 1 bit
counter var_sel

Figure 4.8: Logic diagram for selection of variable.

4.3.6 Increment and Decrement operation by keypad


After selection of control variable its values have to be adjusted as per require-
ment. For this purpose two keys are needed, one is for increment and another
is for decrement operation. This logic requires mainly one adder for increment,
one subtractor for decrement and one multiplexer. One input of both adder
and subtractor is fixed to decimal value 1 and other input is the current output
from the multiplexer. By this logic if user stop the increment and decrement
operation then current output value will be available at the input of adder
and subtractor so the next time operation will starts from this current value.
According to the selection line of multiplexer increment or decrement value
will selected. All the operations have to be properly synchronized so that each
arithmetic and logical block operates concurrently. Logic diagram is shown in
Fig 4.9.
88 Interface Board for Real-Time Simulator

ADD
2x1 MUX
+
i0[n..0]
constant=1 inc/dce_clk add_sub[n..0]
clk_en
i1[n..0]
_

inc_dce
SUB

inc_key inc

clk_out20 inc
inc_dce
dce
dce_key inc/dce_clk

clk_out20 dce

Figure 4.9: Increment and Decrement logic diagram.


4.4 RS232 Interface 89

Depending on the type of keypad (whether matrix type or not), keyboard


interface can be done in several other ways also. What is described here is just
an example.

4.4 RS232 Interface


RS232 is mainly used for serial communication between computer and periph-
eral(FPGA or DSP). It can operate in either half duplex or full-duplex mode.
The possible baud rates are 1200 bps, 2400 bps, 4800 bps, 9600 bps, 19200
bps, 38400 bps, 57600 bps and 115200 bps.

1. In half duplex mode, communication is possible in only one direction


either FPGA to computer side or computer to FPGA side and for that
only one pin has to be assigned as a input or output, decided by the
direction pin.

2. In full duplex mode, communication is possible in both direction. In full


duplex mode two pins are needed in which one pin will be input and
another one pin will be output decided by the direction pin.

The RS232 interfacing circuit diagram(as shown in 4.10) and I/O pins
assignment is shown Table 4.8

5V 5V
O.1uF
O.1uF
2 V+ VCC
11 T1IN 14 1A 6A
IO40 T1OUT
10 T2IN T2OUT 7 2A 7A
12 R1OUT R1IN 13 3A 8A
IO57 4A
9 R2OUT R2IN 8 9A
1 C1+ 4 5A
C2+
O.1uF 3 C1− C2− 5 O.1uF
6 V−
GND DB9
O.1uF MAX232

Figure 4.10: Circuit diagram of RS232.

Table 4.8: Pin Assignment of RS232


Buffer Direction Bit FPGA Pin I/O Signal
U1:64 = 1 U1:76 IO40 TXD (transmit data)
U1:19 = 0 U1:20 IO57 RXD (Receive data)
90 Interface Board for Real-Time Simulator

4.5 Conclusion
A typical interface card design for the FPGA board has been explained. The
interface card not only brings out the analog and digital I/O channels from
the FPGA main board, but it also provides additional functionality like LCD
and keypad interface. It also houses an RS 232 interface.
Chapter 5

How to use Digital to Analog


converter (AD5447)

5.1 Introduction
AD5447 is CMOS, 12 bit, dual channel, current output digital to analog con-
verter(DAC). This device operates from 2.5V to 5.5V. In this board 5V power
supply is provided for DAC operation. Its conversion time is 0.8us. AD5447
operates in bipolar mode, providing output range from +Vref(10V) to -Vref(-
10). In this chapter, implementation of DAC interface program inside the
FPGA is discussed.

5.2 FPGA implementation of DAC


In the board two DACs(AD5447) are used which provides four analog channel
output simultaneously. Data lines for both DACs are multiplexed which save
the hardware pins of FPGA. By using different control lines for both DACs
(chip select (CS) and Read-Write (R/W)) we can activate only one DAC at a
time. Control lines require active LOW for proper operation.
Data and control lines allocation for both DACs are shown in Table 5.1 and
Table 5.2
92 How to use Digital to Analog converter (AD5447)

Table 5.1: Pin Assignment for first DAC


FPGA Pin Signal value
U1:200 Read Write R/W=0 for write and R/W=1 for read
U1:197 Chip Select CS=0 for chip select
U1:213 Channel select CH=0 for channel A and CH=1 for channel B
U1:194 DB0 dataline
U1:193 DB1 dataline
U1:188 DB2 dataline
U1:187 DB3 dataline
U1:186 DB4 dataline
U1:185 DB5 dataline
U1:201 DB6 dataline
U1:202 DB7 dataline
U1:203 DB8 dataline
U1:206 DB9 dataline
U1:207 DB10 dataline
U1:208 DB11 dataline

Table 5.2: Pin Assignment for second DAC


FPGA Pin Signal value
U1:196 Read Write R/W=0 for write and R/W=1 for read
U1:195 Chip Select CS=0 for chip select
U1:213 Channel select CH=0 for channel A and CH=1 for channel B
U1:194 DB0 dataline
U1:193 DB1 dataline
U1:188 DB2 dataline
U1:187 DB3 dataline
U1:186 DB4 dataline
U1:185 DB5 dataline
U1:201 DB6 dataline
U1:202 DB7 dataline
U1:203 DB8 dataline
U1:206 DB9 dataline
U1:207 DB10 dataline
U1:208 DB11 dataline
5.2 FPGA implementation of DAC 93

5.2.1 Control signals


1. Chip select(CS): CS is a active low input signal. Its used in conjunction
with Read-Write signal to load parallel data to the input latch or to read
data from the DAC register.
2. Read/write(R/W): When low, used in conjunction with CS to load par-
allel data. When high, used in conjunction with CS to read back the
contents of the DAC register.
** When CS and R/W are held low, latches are transparent. Any changes
on the data lines are reflected in the relevant DAC output. Chip select
and Read/Write control signals have to generated as a clock.
3. Channel select(CH): If CH is low channel A output will be selected and
if CH is high then channel B output will be selected.

5.2.2 Logic for DAC operation

CS
Ts

R/W
Ts

A B A
CH_A/B

DATA DATA A DATA B DATA A

Ts Sampling Time

Figure 5.1: Timing diagram of DAC

1. Control signals: For proper functioning of DAC, control signals have to


be genrated very precisely. Chip select and Read/Write decides the con-
vertion of incoming data of DAC. Both signals should be active low and
generated as a clock, not permanently low. During the negative edge of
CS and R/W, digital data will be latched and convertion will be done.
Chip select and Read/Write signals decide the sampling time of incoming
digital data. These signals can be generated as various frequency clocks,
depending on the speed requirement. The minimum time is 10ns and this
94 How to use Digital to Analog converter (AD5447)

is achieved by PLL(Phase Locked Loop). Slower clock generation is done


by counter. Channel select has to be genrate as per requirement. Timing
diagram is shown in Fig 5.1
2. Data selection: Data selection is done by DFF and multiplexer. DFF used
for latching the data and multiplexer used for selecting the two different
input. Logic diagram is shown in Fig 5.2

Clock_out (n) clk


I/P1[11..0] A[11..0] CS
Din Dout
R/W
clk Clock_out (n+1)
Clk CH_A/B
DAC_IP[11..0]
Mux_op[11..0]
A[11..0] Output Section
Mux_op[11..0]
B[11..0] Clock Clock_out[n..0]
Counter
clk

I/P2[11..0] B[11..0]
Din Dout PLL Section High
Low
Frequency CLK CLK_out
clk Frequency
Clk
DAC Input Selection Clock generation

Figure 5.2: Logic diagram of DAC

5.2.3 Operation of both DACs together


As we have seen each DAC is having two output channels. In the FPGA
board analog to digital converter(AD7864) supports four input channels. So,
if we use both DACs together then simultaneously we can get four outputs.
Data lines for both the DACs are multiplexed. At any particular instant, only
one DAC will convert the data and this is achieved by proper selection of the
control lines. By the timing diagram shown in Fig 5.3, we can understand
how to use both the DACs simultaneously.
1. Control signals: In the timing diagram, chip-select signals are different
for two different DACs. CS1 and CS2 have to be complementary to
each other. By this way, we can select only one DAC at a time. R/W1
and R/W2 signals have to be properly synchronized with CS1 and CS2
respectively. Channel-select is same for both the DAC. CS1, CS2, R/W1
and R/W2 are active low signals and their frequency depends on the
5.3 Conclusion 95

CS1
Ts

CS2
Ts

R/W1

R/W2

CH

DAC1 A B A B

C D C D
DAC2
Ts Sampling Time

Figure 5.3: Timing diagram of both DACs operation

speed requirement. Higher frequency and lower frequency signals can be


obtained by built-in PLL and a counter respectively.
2. Data selection: Input section of logic diagram consists of four DFF and
three 2:1 multiplexer. DFF is used for latching of digital data to the DAC
register. For proper synchronization of data lines and control lines, DFF
has to be triggerred by the same clock signal of chip select. Multiplexer
is used for selection of particular input. Logic diagram is shown in Fig
5.4.

5.3 Conclusion
In this chapter, one method to interface the DAC is described. It is important
to see that the two DACs share the same data bus, and hence the method
96 How to use Digital to Analog converter (AD5447)

Clock_out (n) clk


CS1
Clock Clock_out[n..0]
Counter R/W1

CS2
R/W2
PLL Section High Clock_out (n+1) CH_A/B
Low
Frequency CLK_in CLK_out
Frequency
Mux_op[11..0] DAC_IP[11..0]
Clock generation Output Section

I/P1[11..0] A[11..0]
Din Dout
B[11..0]
clk
Clk Mux1[11..0]
A[11..0]
I/P2[11..0] B[11..0]
Din Dout
clk clock_out(n+1)
Clk
Mux2[11..0] Mux_op[11..0]

I/P3[11..0] A[11..0]
Din Dout Mux1[11..0]
D[11..0] clk
clk
Clk Mux2[11..0]
C[11..0]
I/P4[11..0] B[11..0]
Din Dout
clk clock_out(n+1)
Clk
DAC Input Selection

Figure 5.4: Logic diagram of both DACs operation

of DAC interface depends on the hardware design of the board. Hence the
described method will be useful for the user to interface the DAC. A similar
VHDL program may also be written for this task.

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