Digital Electronics

Lecture Material

- Sankara Subramanian
Digital Systems

° Analysis problem:

. Logic .
Inputs Outputs
Circuit
. .

• Determine binary outputs for each combination of inputs

° Design problem: given a task, develop a circuit

that accomplishes the task
• Many possible implementation
• Try to develop “best” circuit based on some criterion
(size, power, performance, etc.)
Toll Booth Controller

° Consider the design of a toll booth controller

° Inputs: quarter, car sensor
° Outputs: gate lift signal, gate close signal

$.25 Logic Raise gate

Car? Circuit Close gate

° If driver pitches in quarter, raise gate.

° When car has cleared gate, close gate.
 Describing Circuit Functionality: Inverter

Truth Table
A Y
A Y 0 1

1 0
Symbol

Input Output
° Basic logic functions have symbols.
° The same functionality can be represented with truth
tables.
• Truth table completely specifies outputs for all input combinations.

° The above circuit is an inverter.

• An input of 0 is inverted to a 1.
• An input of 1 is inverted to a 0.
 The AND Gate

A
Y
B

° This is an AND gate.

° So, if the two inputs signals Truth Table

are asserted (high) the A B Y

output will also be asserted. 0 0 0

Otherwise, the output will 0 1 0

be deasserted (low). 1 0 0

1 1 1
 The OR Gate

A
Y
B

° This is an OR gate. A B Y

° So, if either of the two 0 0 0

input signals are 0 1 1

asserted, or both of 1 0 1

them are, the output 1 1 1

will be asserted.
 Describing Circuit Functionality: Waveforms

AND Gate
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

° Waveforms provide another approach for representing

functionality.
° Values are either high (logic 1) or low (logic 0).
° Can you create a truth table from the waveforms?
Consider three-input gates

3 Input OR Gate
Ordering Boolean Functions

° How to interpret A•B+C?

• Is it A•B ORed with C ?
• Is it A ANDed with B+C ?

° Order of precedence for Boolean algebra: AND

before OR.
° Note that parentheses are needed here :
Boolean Algebra

° A Boolean algebra is defined as a closed algebraic

system containing a set K or two or more elements
and the two operators, . and +.
° Useful for identifying and minimizing circuit
functionality
° Identity elements
• a+0=a
• a.1=a

° 0 is the identity element for the + operation.

° 1 is the identity element for the . operation.
 Commutativity and Associativity of the Operators

° The Commutative Property:

For every a and b in K,
• a+b=b+a
• a.b=b.a

° The Associative Property:

For every a, b, and c in K,
• a + (b + c) = (a + b) + c
• a . (b . c) = (a . b) . c
 Distributivity of the Operators and Complements
° The Distributive Property:
For every a, b, and c in K,
• a+(b.c)=(a+b).(a+c)
• a.(b+c)=(a.b)+(a.c)

° The Existence of the Complement:

For every a in K there exists a unique element
called a’ (complement of a) such that,
• a + a’ = 1
• a . a’ = 0

° To simplify notation, the . operator is frequently

omitted. When two elements are written next to
each other, the AND (.) operator is implied…
• a+b.c=(a+b).(a+c)
• a + bc = ( a + b )( a + c )
Duality

° The principle of duality is an important concept.

This says that if an expression is valid in Boolean
algebra, the dual of that expression is also valid.
° To form the dual of an expression, replace all +
operators with . operators, all . operators with +
operators, all ones with zeros, and all zeros with
ones.
° Form the dual of the expression
a + (bc) = (a + b)(a + c)

° Following the replacement rules…

a(b + c) = ab + ac

° Take care not to alter the location of the

parentheses if they are present.
Involution

° This theorem states:

a’’ = a
° Remember that aa’ = 0 and a+a’=1.
• Therefore, a’ is the complement of a and a is also the
complement of a’.
• As the complement of a’ is unique, it follows that a’’=a.

° Taking the double inverse of a value will give the

initial value.
Absorption

° This theorem states:

a + ab = a a(a+b) = a
° To prove the first half of this theorem:
a + ab = a . 1 + ab
= a (1 + b)
= a (b + 1)
= a (1)
a + ab = a
DeMorgan’s Theorem

° A key theorem in simplifying Boolean algebra

expression is DeMorgan’s Theorem. It states:
(a + b)’ = a’b’ (ab)’ = a’ + b’

° Complement the expression

a(b + z(x + a’)) and simplify.

(a(b+z(x + a’)))’ = a’ + (b + z(x + a’))’

= a’ + b’(z(x + a’))’
= a’ + b’(z’ + (x + a’)’)
= a’ + b’(z’ + x’a’’)
= a’ + b’(z’ + x’a)
Boolean Functions

° Boolean algebra deals with binary variables and

logic operations.
° Function results in binary 0 or 1

x y z F
0 0 0 0
0 0 1 0 x
0 1 0 0 y
0 1 1 0 F = x(y+z’)
z y+z’
1 0 0 1 z’
1 0 1 0
1 1 0 1
1 1 1 1 F = x(y+z’)
Boolean Functions

° Boolean algebra deals with binary variables and

logic operations.
° Function results in binary 0 or 1

x y z xy yz G
0 0 0 0 0 0
0 0 1 0 0 0 x xy
0 1 0 0 0 0 y
0 1 1 0 1 1 G = xy +yz
1 0 0 0 0 0 z
yz
1 0 1 0 0 0
1 1 0 1 0 1 We will learn how to transition between equation,
1 1 1 1 1 1 symbols, and truth table.
Representation Conversion

° Need to transition between boolean expression,

truth table, and circuit (symbols).
° Converting between truth table and expression is
easy.
° Converting between expression and circuit is
easy.
° More difficult to convert to truth table.

Circuit Boolean
Expression

Truth
Table
Truth Table to Expression

° Converting a truth table to an expression

• Each row with output of 1 becomes a product term
• Sum product terms together.

x y z G Any Boolean Expression can be

0 0 0 0 represented in sum of products form!
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
xyz + xyz’ + x’yz
 Equivalent Representations of Circuits
° All three formats are equivalent
° Number of 1’s in truth table output column equals AND
terms for Sum-of-Products (SOP)
x y z G
0 0 0 0
0 0 1 0 x x
x
0 1 0 0 G
x
0 1 1 1 x
x
1 0 0 0 x
1 0 1 0 x
x
1 1 0 1
1 1 1 1

x y z
G = xyz + xyz’ + x’yz
 Reducing Boolean Expressions

° Is this the smallest possible implementation of

this expression? No! G = xyz + xyz’ + x’yz
° Use Boolean Algebra rules to reduce complexity
while preserving functionality.
° Step 1: Use Theorum 1 (a + a = a)
• So xyz + xyz’ + x’yz = xyz + xyz + xyz’ + x’yz

° Step 2: Use distributive rule a(b + c) = ab + ac

• So xyz + xyz + xyz’ + x’yz = xy(z + z’) + yz(x + x’)

° Step 3: Use Postulate 3 (a + a’ = 1)

• So xy(z + z’) + yz(x + x’) = xy.1 + yz.1

° Step 4: Use Postulate 2 (a . 1 = a)

• So xy.1 + yz.1 = xy + yz = xyz + xyz’ + x’yz
Minterms and Maxterms

° Each variable in a Boolean expression is a literal

° Boolean variables can appear in normal (x) or
complement form (x’)
° Each AND combination of terms is a minterm
° Each OR combination of terms is a maxterm
For example: For example:
Minterms Maxterms

x y z Minterm x y z Maxterm
0 0 0 x’y’z’ m0 0 0 0 x+y+z M0
0 0 1 x’y’z m1 0 0 1 x+y+z’ M1
… …
1 0 0 xy’z’ m4 1 0 0 x’+y+z M4
… …
1 1 1 xyz m7 1 1 1 x’+y’+z’ M7
 Representing Functions with Minterms
° Minterm number same as row position in truth table
(starting from top from 0)
° Shorthand way to represent functions

x y z G
0 0 0 0 G = xyz + xyz’ + x’yz
0 0 1 0
0 1 0 0
0 1 1 1
G = m7 + m6 + m3 = Σ(3, 6, 7)
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
 Complementing Functions
° Minterm number same as row position in truth table
(starting from top from 0)
° Shorthand way to represent functions

x y z G G’
0 0 0 0 1 G = xyz + xyz’ + x’yz
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0 G’ = (xyz + xyz’ + x’yz)’ =
1 0 0 0 1
1 0 1 0 1
1 1 0 1 0 Can we find a simpler representation?
1 1 1 1 0
 Complementing Functions

° Step 1: assign temporary names

• b + c -> z G = a + b+ c
• (a + z)’ = G’ G’ = (a + b + c)’
° Step 2: Use DeMorgans’ Law
• (a + z)’ = a’ . z’
° Step 3: Resubstitute (b+c) for z
• a’ . z’ = a’ . (b + c)’
° Step 4: Use DeMorgans’ Law G = a + b+ c
• a’ . (b + c)’ = a’ . (b’. c’) G’ = a’ . b’ . c’ = a’b’c’
° Step 5: Associative rule
• a’ . (b’. c’) = a’ . b’ . c’
Complementation Example

° Find complement of F = x’z + yz

• F’ = (x’z + yz)’

° DeMorgan’s
• F’ = (x’z)’ (yz)’

° DeMorgan’s
• F’ = (x’’+z’)(y’+z’)

° Reduction -> eliminate double negation on x

• F’ = (x+z’)(y’+z’)

This format is called product of sums

 Conversion Between Canonical Forms

° Easy to convert between minterm and maxterm

representations
° For maxterm representation, select rows with 0’s

x y z G
0 0 0 0 G = xyz + xyz’ + x’yz
0 0 1 0
0 1 0 0
0 1 1 1 G = m7 + m6 + m3 = Σ(3, 6, 7)
1 0 0 0
1 0 1 0
1 1 0 1 G = M0M1M2M4M5 = Π(0,1,2,4,5)
1 1 1 1
G = (x+y+z)(x+y+z’)(x+y’+z)(x’+y+z)(x’+y+z’)
 Representation of Circuits
° All logic expressions can be represented in 2-
level format
° Circuits can be reduced to minimal 2-level
representation
° Sum of products representation most common in
industry.
Logic functions of N variables

° Each truth table represents one possible function

(e.g. AND, OR)
N
° If there are N inputs, there are 22
° For example, is N is 2 then there are 16 possible
truth tables.
° So far, we have defined 2 of these functions
• 14 more are possible.

° Why consider new functions?

• Cheaper hardware, more flexibility. x y G
0 0 0
0 1 0
1 0 0
1 1 1
 The NAND Gate

A
Y
B

° This is a NAND gate. It is a combination of an

AND gate followed by an inverter. Its truth table
shows this…
° NAND gates have several interesting properties…
• NAND(a,a)=(aa)’ = a’ = NOT(a)
• NAND’(a,b)=(ab)’’ = ab = AND(a,b)
A B Y
• NAND(a’,b’)=(a’b’)’ = a+b = OR(a,b)
0 0 1

0 1 1

1 0 1

1 1 0
The NAND Gate

° These three properties show that a NAND gate with both

of its inputs driven by the same signal is equivalent to a
NOT gate
° A NAND gate whose output is complemented is
equivalent to an AND gate, and a NAND gate with
complemented inputs acts as an OR gate.
° Therefore, we can use a NAND gate to implement all three
of the elementary operators (AND,OR,NOT).
° Therefore, ANY switching function can be constructed using
only NAND gates. Such a gate is said to be primitive or
functionally complete.
 NAND Gates into Other Gates

(what are these circuits?)

A
Y

NOT Gate A
B Y

A AND Gate

Y
B

OR Gate
 The NOR Gate

A
Y
B

° This is a NOR gate. It is a combination of an OR

gate followed by an inverter. It’s truth table
shows this…
° NOR gates also have several A B Y

interesting properties… 0 0 1
• NOR(a,a)=(a+a)’ = a’ = NOT(a) 0 1 0
• NOR’(a,b)=(a+b)’’ = a+b = OR(a,b)
• NOR(a’,b’)=(a’+b’)’ = ab = AND(a,b) 1 0 0

1 1 0
 Functionally Complete Gates

° Just like the NAND gate, the NOR gate is

functionally complete…any logic function can be
implemented using just NOR gates.
° Both NAND and NOR gates are very valuable as
any design can be realized using either one.
° It is easier to build an IC chip using all NAND or
NOR gates than to combine AND,OR, and NOT
gates.
° NAND/NOR gates are typically faster at switching
and cheaper to produce.
 NOR Gates into Other Gates

(what are these circuits?)

A
Y

NOT Gate A
B Y

A OR Gate

Y
B

AND Gate
 The XOR Gate (Exclusive-OR)

A
Y
B
° This is a XOR gate.
A B Y
° XOR gates assert their output
0 0 0
when exactly one of the inputs
0 1 1
is asserted, hence the name.
1 0 1
° The switching algebra symbol
1 1 0
for this operation is ⊕, i.e.
1 ⊕ 1 = 0 and 1 ⊕ 0 = 1.
 The XNOR Gate

A
Y
B
° This is a XNOR gate.
° This functions as an A B Y

exclusive-NOR gate, or 0 0 1

simply the complement of 0 1 0

the XOR gate. 1 0 0
° The switching algebra symbol 1 1 1
for this operation is ~, i.e.
1 ~ 1 = 1 and 1 ~ 0 = 0.
NOR Gate Equivalence

° NOR Symbol, Equivalent Circuit, Truth Table

DeMorgan’s Theorem

° A key theorem in simplifying Boolean algebra

expression is DeMorgan’s Theorem. It states:
(a + b)’ = a’b’ (ab)’ = a’ + b’

° Complement the expression

a(b + z(x + a’)) and simplify.

(a(b+z(x + a’)))’ = a’ + (b + z(x + a’))’

= a’ + b’(z(x + a’))’
= a’ + b’(z’ + (x + a’)’)
= a’ + b’(z’ + x’a’’)
= a’ + b’(z’ + x’a)
Universality of NAND and NOR gates
 Universality of NOR gate

° Equivalent representations of the AND, OR, and

NOT gates
 Karnaugh maps

° Alternate way of representing Boolean function

• All rows of truth table represented with a square
• Each square represents a minterm

° Easy to convert between truth table, K-map, and

SOP
• Unoptimized form: number of 1’s in K-map equals number of
minterms (products) in SOP
• Optimized form: reduced number of minterms

y F = Σ(m0,m1) = x’y + x’y’

y
x 0 1
x y F
0 x’y’ x’y y
x 0 1 0 0 1
x 1 xy’ xy 0 1 1 0 1 1
1 0 0 1 0 0
1 1 0
 Karnaugh Maps

° A Karnaugh map is a graphical tool for assisting in the

general simplification procedure.
° Two variable maps.
B B
A 0 1 A 0 1
00 1 00 1 F=AB +A′B +AB ′
F=AB ′+A’B
11 0 11 1
A B C F
° Three variable maps. 0 0 0 0
0 0 1 1
BC 0 1 0 1
00 01 11 10 0 1 1 0
A
00 1 0 1 1 0 0 1
1 0 1 1
11 1 1 1 1 1 0 1
+
1 1 1 1

F=AB’C’ +AB ′C +ABC +ABC ′ + A’B’C + A’BC’

Rules for K-Maps
ƒ We can reduce functions by circling 1’s in the K-map
ƒ Each circle represents minterm reduction
ƒ Following circling, we can deduce minimized and-or
form.
Rules to consider
°Every cell containing a 1 must be included at least
once.
±The largest possible “power of 2 rectangle” must be
enclosed.
²The 1’s must be enclosed in the smallest possible
number of rectangles.

Example
 Karnaugh Maps

° A Karnaugh map is a graphical tool for assisting in the

general simplification procedure.
° Two variable maps.
B B
A 0 1 A 0 1
00 1 00 1 F=AB +A′B +AB ′
F=AB ′+A’B
11 0 11 1 F=A+B
° Three variable maps.
BC
00 01 11 10
A
00 1 0 1
1 1 1 1 1 F=A+B ′C +BC ′

F=AB’C’ +AB ′C +ABC +ABC ′ + A’B’C + A’BC’

Karnaugh maps

° Numbering scheme based on Gray–code

• e.g., 00, 01, 11, 10
• Only a single bit changes in code for adjacent map cells
• This is necessary to observe the variable transitions

AB A
C 00 01 11 10
0
A
0 0 1 1 C 1
G(A,B,C) = A
C 0 0 1 1 B
B

A
1 0 0 1
F(A,B,C) = Σm(0,4,5,7) = AC + B’C’
C 0 0 1 1
B
Karnaugh Maps for Four Input Functions

° Represent functions of 4 inputs with 16 minterms

° Use same rules developed for 3-input functions
° Note bracketed sections shown in example.
Karnaugh map: 4-variable example

° F(A,B,C,D) = Σm(0,2,3,5,6,7,8,10,11,14,15)
F=
C + A’BD + B’D’

A 1111
0111
1 0 0 1

0 1 0 0
D
C
1 1 1 1 D
C A
1000
1 1 1 1 0000 B
B
Solution set can be considered as a coordinate
System!
 Design examples

A A A
0 0 0 0 1 0 0 0 0 1 1 1

1 0 0 0 0 1 0 0 0 0 1 1
D D D
1 1 0 1 0 0 1 0 0 0 0 0
C C C
1 1 0 0 0 0 0 1 0 0 1 0
B B B

K-map for LT K-map for EQ K-map for GT

LT = A' B' D + A' C + B' C D

EQ = A'B'C'D' + A'BC'D + ABCD + AB'CD’
GT = B C' D' + A C' + A B D'

Can you draw the truth table for these examples?

Physical Implementation

° Step 1: Truth table

A B C D
° Step 2: K-map
° Step 3: Minimized sum-of-
products
° Step 4: Physical
EQ implementation with gates
A
1 0 0 0

0 1 0 0
D
0 0 1 0
C
0 0 0 1
B

K-map for EQ
 Karnaugh Maps
° Four variable maps.
CD
00 01 11 10
AB F=A′BC ′+A′CD ′+ABC
00 0 0 0 1
+AB ′C′D ′+ABC ′+AB ′C
01 1 1 0 1
11 1 1 1 1 F=BC ′+CD ′+ AC+ AD ′
10 1 0 1 1

° Need to make sure all 1’s are covered

° Try to minimize total product terms.
° Design could be implemented using NANDs and NORs
 Karnaugh maps: Don’t cares

° In some cases, outputs are undefined

° We “don’t care” if the logic produces a 0 or a 1
° This knowledge can be used to simplify functions.

A
AB
CD 00 01 11 10
00 0 0 X 0 - Treat X’s like either 1’s or 0’s
01 - Very useful
1 1 X 1
D - OK to leave some X’s uncovered
11 1 1 0 0
C
10 0 X 0 0

B
 Karnaugh maps: Don’t cares
° f(A,B,C,D) = Σ m(1,3,5,7,9) + d(6,12,13)
• without don't cares
- f=
A B C D f
A’D + C’D 0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
A 0 0 1 1 1
AB 0 1 0 0 0
CD 00 01 11 10 0 1 0 1 1
00 0 0 X 0 0 1 1 0 X
+
0 +
1 1 1 1
01 1 1 X 1 1 0 0 0 0
D 1 0 0 1 1
11 1 1 0 0 1 0 1 0 0
C 1 0 1 1 0
10 0 X 0 0 1 1 0 0 X
1 1 0 1 X
B 1 1 1 0 0
1 1 1 1 0
Don’t Care Conditions

° In some situations, we don’t care about the value of a

function for certain combinations of the variables.
• these combinations may be impossible in certain contexts
• or the value of the function may not matter in when the combinations occur

° In such situations we say the function is incompletely

specified and there are multiple (completely specified) logic
functions that can be used in the design.
• so we can select a function that gives the simplest circuit

° When constructing the terms in the simplification

procedure, we can choose to either cover or not cover the
don’t care conditions.
Map Simplification with Don’t Cares

CD
00 01 11 10
AB
00 0 1 0 0
01 x x x 1 F=A′C′D+B+AC
11 1 1 1 x
10 x 0 1 1
° Alternative covering.
CD
00 01 11 10
AB
00 0 1 0 0
01 x x x 1 F=A′B′C′D+ABC′+BC+AC
11 1 1 1 x
10 x 0 1 1
Karnaugh maps: don’t cares (cont’d)

° f(A,B,C,D) = Σ m(1,3,5,7,9) + d(6,12,13)

• f = A'D + B'C'D without don't cares
• f= with don't cares

A'D + C'D

A
by using don't care as a "1"
0 0 X 0
a 2-cube can be formed
1 1 X 1
rather than a 1-cube to cover
D this node
1 1 0 0
C don't cares can be treated as
0 X 0 0 1s or 0s
B depending on which is more
advantageous
 Definition of terms for two-level simplification
° Implicant
• Single product term of the ON-set (terms that create a logic 1)

° Prime implicant
• Implicant that can't be combined with another to form an implicant with
fewer literals.

° Essential prime implicant

• Prime implicant is essential if it alone covers a minterm in the K-map
• Remember that all squares marked with 1 must be covered

° Objective:
• Grow implicant into prime implicants (minimize literals per term)
• Cover the K-map with as few prime implicants as possible
(minimize number of product terms)
Examples to illustrate terms

A
0 X 1 0 6 prime implicants:
A'B'D, BC', AC, A'C'D, AB, B'CD
1 1 1 0
D
essential
1 0 1 1
C
0 0 1 1 minimum cover: AC + BC' + A'B'D
B

A
5 prime implicants: 0 0 1 0
BD, ABC', ACD, A'BC, A'C'D
1 1 1 0
D
essential 0 1 1 1
C
0 1 0 0
minimum cover: 4 essential implicants
B
Prime Implicants

Any single 1 or group of 1s in the Karnaugh map of a

function F is an implicant of F.
A product term is called a prime implicant of F if it
cannot be combined with another term to eliminate a
variable. If a function F is represented by
A this Karnaugh Map. Which of the
following terms are implicants of
Example: 1 1 1 F, and which ones are prime
1 1 implicants of F?
D (a) AC’D’ Implicants:
1 (b) BD (a),(c),(d),(e)
C
1 1 (c) A’B’C’D’
(d) AC’ Prime Implicants:
(e) B’C’D’ (d),(e)
B
 Essential Prime Implicants

A product term is an essential prime implicant if there is a

minterm that is only covered by that prime implicant.
- The minimal sum-of-products form of F must include
all the essential prime implicants of F.
 The Problem
° How can we convert from a circuit drawing to an
equation or truth table?
° Two approaches
° Create intermediate equations
° Create intermediate truth tables

A
B
C
Out
A
B

C’
Label Gate Outputs

1. Label all gate outputs that are a function of input

variables.
2. Label gates that are a function of input variables
and previously labeled gates.
3. Repeat process until all outputs are labelled.

A R
B
C
Out
S T
A
B

C’
 Approach 1: Create Intermediate Equations
‰ Step 1: Create an equation for each gate output based
on its input.
• R = ABC
• S=A+B
• T = C’S
• Out = R + T

A R
B
C
Out
S T
A
B

C’
 Approach 1: Substitute in subexpressions
‰ Step 2: Form a relationship based on input variables
(A, B, C)
• R = ABC
• S=A+B
• T = C’S = C’(A + B)
• Out = R+T = ABC + C’(A+B)

A R
B
C
Out
S T
A
B

C’
 Approach 1: Substitute in subexpressions
‰ Step 3: Expand equation to SOP final result
• Out = ABC + C’(A+B) = ABC + AC’ + BC’

A
B
C
Out
A
C’

B
C’
 Approach 2: Truth Table
‰ Step 1: Determine outputs for functions of input
variables.
A B C R S
0 0 0 0 0
0 0 1 0 0
0 1 0 0 1
0 1 1 0 1
1 0 0 0 1
1 0 1 0 1
1 1 0 0 1
A R
1 1 1 1 1
B
C
Out
S T
A
B

C’
 Approach 2: Truth Table
‰ Step 2: Determine outputs for functions of
intermediate variables.
A B C C’ R S T
0 0 0 1 0 0 0
T = S * C’ 0 0 1 0 0 0 0
0 1 0 1 0 1 1
0 1 1 0 0 1 0
1 0 0 1 0 1 1
1 0 1 0 0 1 0
1 1 0 1 0 1 1
A R 1 1 1 0 1 1 0
B
C
Out
S T
A
B

C’
 Approach 2: Truth Table
‰ Step 3: Determine outputs for function.
A B C R S T Out
0 0 0 0 0 0 0
0 0 1 0 0 0 0
R + T = Out 0 1 0 0 1 1 1
0 1 1 0 1 0 0
1 0 0 0 1 1 1
1 0 1 0 1 0 0
1 1 0 0 1 1 1
A R 1 1 1 1 1 0 1
B
C
Out
S T
A
B

C’
 Design Procedure (Mano)
Design a circuit from a specification.
1. Determine number of required inputs and
outputs.
2. Derive truth table
3. Obtain simplified Boolean functions
4. Draw logic diagram and verify correctness
A B C RS
0 0 0 0 0
0 0 1 0 1
S=A+B+C 0 1 0 0 1
R = ABC 0 1 1 0 1
1 0 0 0 1
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
 Half Adder

° Add two binary numbers

• A0 , B0 -> single bit inputs
• S0 -> single bit sum
• C1 -> carry out

A0
A0 B0 S0 C 1 S0
B0
0 0 0 0
0 1 1 0
1 0 1 0 C1
1 1 0 1
Dec Binary
1 1
+1 +1
2 10
 Multiple-bit Addition

° Consider single-bit adder for each bit position.

A3 A2 A1 A0 B3 B2 B1 B0
A 0 1 0 1 B 0 1 1 1

Ci+1 Ci
1 1 1
A 0 1 0 1 Ai
B 0 1 1 1 +Bi
1 1 0 0 Si
Each bit position creates a sum and carry
 Full Adder

° Full adder includes carry in Ci

° Notice interesting pattern in Karnaugh map.

Ci Ai Bi Si Ci+1 AiBi
Ci 00 01 11 10
0 0 0 0 0
0 0 1 1 0 0 1 1
0 1 0 1 0
0 1 1 0 1 1 1 1
1 0 0 1 0
1 0 1 0 1 Si
1 1 0 0 1
1 1 1 1 1
 Full Adder

° Full adder includes carry in Ci

° Alternative to XOR implementation

Ci Ai Bi Si Ci+1 Si = !Ci & !Ai & Bi

0 0 0 0 0 # !Ci & Ai & !Bi
0 0 1 1 0 # Ci & !Ai & !Bi
0 1 0 1 0 # Ci & Ai & Bi
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
 Full Adder

° Reduce and/or representations into XORs

Si = !Ci & !Ai & Bi

# !Ci & Ai & !Bi
# Ci & !Ai & !Bi
# Ci & Ai & Bi

Si = !Ci & (!Ai & Bi # Ai & !Bi)

# Ci & (!Ai & !Bi # Ai & Bi)

Si = !Ci & (Ai $ Bi)

# Ci & !(Ai $ Bi)

Si = Ci $ (Ai $ Bi)
 Full Adder

° Now consider implementation of carry out

° Two outputs per full adder bit (Ci+1, Si)

Ci Ai Bi Si Ci+1 AiBi
Ci 00 01 11 10
0 0 0 0 0
0 0 1 1 0 0 1
0 1 0 1 0
0 1 1 0 1 1 1 1 1
1 0 0 1 0
1 0 1 0 1 Ci+1
1 1 0 0 1
1 1 1 1 1 Note: 3 inputs
 Full Adder
° Now consider implementation of carry out
° Minimize circuit for carry out - Ci+1
AiBi
Ci Ai Bi Si Ci+1 Ci 00 01 11 10
0 0 0 0 0 0 1
0 0 1 1 0
0 1 0 1 0 1 1 1 1
0 1 1 0 1
1 0 0 1 0 Ci+1
1 0 1 0 1
1 1 0 0 1 Ci+1 = Ai & Bi
1 1 1 1 1 # Ci & Bi
# Ci & Ai
Full Adder

Ci+1 = Ai & Bi
# Ci !Ai & Bi
# Ci & Ai & !Bi

Ci+1 = Ai & Bi
# Ci & (!Ai & Bi # Ai & !Bi)

Ci+1 = Ai & Bi # Ci & (Ai $ Bi)

Recall:
Si = Ci $ (Ai $ Bi)

Ci+1 = Ai & Bi # Ci & (Ai $ Bi)

 Full Adder
° Full adder made of several half adders

Si = Ci $ (Ai $ Bi)
Ci+1 = Ai & Bi # Ci & (Ai $ Bi)
Ci

Ai Si
Bi

C i+1

Half-adder Half-adder
 Full Adder
° Hardware repetition simplifies hardware design

Ci Si
half-adder
Ai S C
half-adder C i+1
Bi
C

A full adder can be made from

two half adders (plus an OR gate).
 Full Adder
° Putting it all together
• Single-bit full adder
• Common piece of computer hardware
Ai Bi

C i+1 Full Adder Ci

Si

Block Diagram
 4-Bit Adder
° Chain single-bit adders together.
° What does this do to delay?
A3 B3 A2 B2 A1 B1 A0 B0

Full Adder Full Adder Full Adder Full Adder 0

C3 C2 C1

C4 S3 S2 S1 S0

C 1 1 1 0
A 0 1 0 1
B 0 1 1 1
S 1 1 0 0
 Negative Numbers – 2’s Complement.
° Subtracting a number is the same as:
1. Perform 2’s complement
2. Perform addition

° If we can augment adder with 2’s complement

hardware?

110 = 0116 = 00000001

-110 = FF16 = 11111111

12810 = 8016 = 10000000

-12810 = 8016 = 10000000
 4-bit Subtractor: E = 1

A3 B3 A2 B2 A1 B1 A0 B0

Full Adder Full Adder Full Adder Full Adder

C3 C2 C1 +1

C4 SD3 SD2 SD1 SD0

Add A to B’ (one’s complement) plus 1

That is, add A to two’s complement of B
D=A-B
Adder- Subtractor Circuit
Magnitude Comparator

° The comparison of two numbers

• outputs: A>B, A=B, A<B

° Design Approaches
• the truth table
2n
- 2 entries - too cumbersome for large n
• use inherent regularity of the problem
- reduce design efforts
- reduce human errors

A<B
A[3..0] Magnitude
Compare A=B
B[3..0]
A>B
Magnitude Comparator

A0 C0
B0 D01
A1 C1
B1 A_EQ_B
A2 C2
B2
A3 C3 D23
B3

How can we find A > B?

How many rows would a truth table have?

28 = 256
Magnitude Comparator

A0 C0
B0 D01
A1 C1
B1 A_EQ_B Find A > B
A2 C2
B2
A3 C3 D23
B3

Because A3 > B3
If A = 1001 and i.e. A3 . B3’ = 1
B = 0111 Therefore, one term in the
is A > B? logic equation for A > B is
Why? A3 . B3’
Magnitude Comparator

If A = 1010 and A > B = A3 . B3’

B = 1001 + C3 . A2 . B2’
is A > B? + …..
Why? Because A3 = B3 and
A2 = B2 and
A1 > B1
i.e. C3 = 1 and C2 = 1 and
A1 . B1’ = 1
Therefore, the next term in the
logic equation for A > B is
C3 . C2 . A1 . B1’
Magnitude Comparison

° Algorithm -> logic

• A = A3A2A1A0 ; B = B3B2B1B0
• A=B if A3=B3, A2=B2, A1=B1and A1=B1

° Test each bit:

- equality: xi= AiBi+Ai'Bi'
- (A=B) = x3x2x1x0

° More difficult to test less than/greater than

• (A>B) = A3B3'+x3A2B2'+x3x2A1B1'+x3x2x1 A0B0'
• (A<B) = A3'B3+x3A2'B2+x3x2A1'B1+x3x2x1 A0'B0
• Start comparisons from high-order bits

° Implementation
• xi = (AiBi'+Ai'Bi)’
Multiplexers

° Select an input value with one or more select bits

° Use for transmitting data
° Allows for conditional transfer of data
° Sometimes called a mux
4– to– 1- Line Multiplexer
Quadruple 2–to–1-Line Multiplexer

° Notice enable bit

° Notice select bit
° 4 bit inputs
Multiplexer as combinational modules
° Connect input variables to select inputs of
multiplexer (n-1 for n variables)
° Set data inputs to multiplexer equal to values of
function for corresponding assignment of select
variables
° Using a variable at data inputs reduces size of the
multiplexer
Implementing a Four- Input Function with a Multiplexer
Binary Decoder

° Black box with n input lines and 2n output lines

° Only one output is a 1 for any given input

n Binary 2n outputs
inputs Decoder
 2-to-4 Binary Decoder
Truth Table:
X Y F0 F1 F2 F3
0 0 1 0 0 0
0 1 0 1 0 0 F0 = X'Y'
1 0 0 0 1 0
1 1 0 0 0 1
F1 = X'Y

° From truth table, circuit for F2 = XY'

2x4 decoder is:
° Note: Each output is a 2-
variable minterm (X'Y', X'Y, F3 = XY
XY' or XY)

F0
X Y
X 2-to-4 F1
Y Decoder F2
F3
3-to-8 Binary Decoder

Truth Table:
F0 = x'y'z'
x y z F0 F1 F2 F3 F4 F5 F6 F7 F1 = x'y'z
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0 F2 = x'yz'
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0 F3 = x'yz
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0 F4 = xy'z'
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1 F5 = xy'z

F6 = xyz'
F0
F1 F7 = xyz
X
F2
Y
3-to-8
F3
Z
Decoder F4
F5
F6
x y z
F7
Implementing Functions Using Decoders

° Any n-variable logic function can be implemented using

a single n-to-2n decoder to generate the minterms
• OR gate forms the sum.
• The output lines of the decoder corresponding to the minterms
of the function are used as inputs to the or gate.
° Any combinational circuit with n inputs and m outputs
can be implemented with an n-to-2n decoder with m OR
gates.
° Suitable when a circuit has many outputs, and each
output function is expressed with few minterms.
Implementing Functions Using Decoders

° Example: Full adder x y z C S

0 0 0 0 0
S(x, y, z) = Σ (1,2,4,7)
0 0 1 0 1
C(x, y, z) = Σ (3,5,6,7) 0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

3-to-8 0
Decoder 1 S
2
x S2 3
y S1 4
5 C
z S0 6
7
Building a Binary Decoder with NAND Gates

° Start with a 2-bit decoder

• Add an enable signal (E) Note: use of NANDs
only one 0 active!
if E = 0
Use two 3 to 8 decoders to make 4 to 16 decoder
° Enable can also be active high
° In this example, only one decoder can be active
at a time.
° x, y, z effectively select output line for w
 Encoders

° If the a decoder's output code has fewer bits than the

input code, the device is usually called an encoder.
e.g. 2n-to-n

° The simplest encoder is a 2n-to-n binary encoder

• One of 2n inputs = 1
• Output is an n-bit binary number

Binary
2n encoder n
. .
inputs . . outputs
. .
8-to-3 Binary Encoder
At any one time, only Inputs Outputs
one input line has a value of 1.
I0 I1 I2 I3 I4 I5 I6 I7 y2 y1 y0
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
I0
I1 y 2 = I 4 + I5 + I6 + I7
I2
I3 y 1 = I 2 + I3 + I6 + I7
I4
I5
I6
I7 y 0 = I 1 + I3 + I5 + I7
8-to-3 Priority Encoder
• What if more than one input line has a value of 1?
• Ignore “lower priority” inputs.
• Idle indicates that no input is a 1.
• Note that polarity of Idle is opposite from Table 4-8 in Mano

Inputs Outputs
I0 I1 I2 I3 I4 I5 I6 I7 y2 y1 y0 Idle
0 0 0 0 0 0 0 0 x x x 1
1 0 0 0 0 0 0 0 0 0 0 0
X 1 0 0 0 0 0 0 0 0 1 0
X X 1 0 0 0 0 0 0 1 0 0
X X X 1 0 0 0 0 0 1 1 0
X X X X 1 0 0 0 1 0 0 0
X X X X X 1 0 0 1 0 1 0
X X X X X X 1 0 1 1 0 0
X X X X X X X 1 1 1 1 0
 Sequential Circuits

Inputs Combinational Outputs

circuit
Flip
Next Flops
state Present
state

Timing signal
(clock)
Clock
a periodic external event (input)
Clock
synchronizes
synchronizeswhen
whencurrent
currentstate
statechanges
changeshappen
happen
keeps
keepssystem
systemwell-behaved
well-behaved
makes
makesititeasier
easierto
todesign
designand
andbuild
buildlarge
largesystems
systems
Cross-coupled Inverters

° A stable value can be stored at inverter outputs

0 1

1 0

State 1 State 2
 S-R Latch with NORs

R (reset) Q S R Q Q’
1 1 0 0 Undefined
1 0 1 0 Set
Q 0 1 0 1 Reset
S (set) 0 0 0 1 Stable
1 0
° S-R latch made from cross-coupled NORs
° If Q = 1, set state
° If Q = 0, reset state
° Usually S=0 and R=0
° S=1 and R=1 generates unpredictable results
 S-R Latch with NANDs

S S R Q Q’
Q
0 0 1 1 Disallowed
0 1 1 0 Set
1 0 0 1 Reset
Q’
R 1 1 0 1
1 0 Store

° Latch made from cross-coupled NANDs

° Sometimes called S’-R’ latch
° Usually S=1 and R=1
° S=0 and R=0 generates unpredictable results
S-R Latches
 S-R Latch with control input

° Occasionally, desirable to avoid latch changes

° C = 0 disables all latch state changes
° Control signal enables data change when C = 1
° Right side of circuit same as ordinary S-R latch.
 NOR S-R Latch with Control Input

Latch is level -sensitive, in regards to C

level-sensitive,
Only stores data if C’ = 0
R’
Q

C’

Q’
Latch operation
S’
enabled by
C Outputs change
when C is low:
Input sampling RESET and SET
enabled by gates Otherwise: HOLD
 D Latch

° Q0 indicates the previous state (the previously

stored value)
X
D S
Q
C

Q’

Y R
X Y C Q Q’
D C Q Q’
0 0 1 Q0 Q0 ’ Store
0 1 0 1
0 1 1 0 1 Reset
1 1 1 0
1 0 1 1 0 Set
X 0 Q0 Q0 ’
1 1 1 1 1 Disallowed
X X 0 Q0 Q0 ’ Store
D Latch
X
D S
Q
C

Q’

Y R
D C Q Q’
0 1 0 1
1 1 1 0
X 0 Q0 Q0 ’

° Input value D is passed to output Q when C is high

° Input value D is ignored when C is low
D Latch
Latches on following
edge of clock

E
x D
Q x
z
E C
z

° Z only changes when E is high

° If E is high, Z will follow X
D Latch
Latches on following
edge of clock

E
x D
Q x
z
E C
z

° The D latch stores data indefinitely, regardless of

input D values, if C = 0
° Forms basic storage element in computers
Symbols for Latches

° SR latch is based on NOR gates

° S’R’ latch based on NAND gates
° D latch can be based on either.
° D latch sometimes called transparent latch
 D Latch

D
S
S’
Q
C

Q’

R R’
S R C Q Q’
D C Q Q’
0 0 1 Q0 Q0 ’ Store
0 1 0 1
0 1 1 0 1 Reset
1 1 1 0
1 0 1 1 0 Set
X 0 Q0 Q0 ’
1 1 1 1 1 Disallowed
X X 0 Q0 Q0 ’ Store

° When C is high, D passes from input to output (Q)

 Clocking Event

° What if the output only changed on a C transition?

Positive edge triggered

D C Q Q’
D Q
0 0 1
C Q’ 1 1 0
X 0 Q0 Q0 ’

Hi-Lo edge Lo-Hi edge

 Master-Slave D Flip Flop

° Consider two latches combined together

° Only one C value active at a time
° Output changes on falling edge of the clock
 D Flip-Flop
° Stores a value on the positive edge of C
° Input changes at other times have no effect on output

Positive edge triggered

D C Q Q’
D Q
0 0 1
C Q’ 1 1 0
X 0 Q0 Q0 ’

D gets latched to Q on the rising edge of the clock.

Clocked D Flip-Flop

° Stores a value on the positive edge of C

° Input changes at other times have no effect on output
 Positive and Negative Edge D Flip-Flop
° D flops can be triggered on positive or negative edge
° Bubble before Clock (C) input indicates negative edge
trigger

Lo-Hi edge Hi-Lo edge

Positive Edge-Triggered J-K Flip-Flop

°Created from D flop J K CLK Q Q’

°J sets 0 0 ↑ Q0 Q0’
0 1 ↑ 0 1
°K resets 1 0 ↑ 1 0
°J=K=1 -> invert output 1 1 ↑ TOGGLE
Clocked J-K Flip Flop

° Two data inputs, J and K

° J -> set, K -> reset, if J=K=1 then toggle output

Characteristic Table
Positive Edge-Triggered T Flip-Flop

°Created from D flop

T C Q Q’
°T=0 -> keep current
0 ↑ Q0 Q0’
°K resets 1 ↑ TOGGLE
°T=1 -> invert current
 Asynchronous Inputs

• J, K are synchronous inputs

o Effects on the output are synchronized with the CLK input.
• Asynchronous inputs operate independently of the synchronous
inputs and clock
o Set the FF to 1/0 states at any time.
Asynchronous Inputs
Asynchronous Inputs

• Note reset signal (R) for

D flip flop
• If R = 0, the output Q is
cleared
•This event can occur at
any time, regardless of the
value of the CLK
 Parallel Data Transfer

° Flip flops store outputs from combinational logic

° Multiple flops can store a collection of data
Flip Flop State

° Behavior of clocked sequential circuit can be

determined from inputs, outputs and FF state
x D0
Q1 Q0
Q
D
Q’
y
Q
D Q1
Q0 D1 Q’

Clk

y(t) = x(t)Q1(t)Q0(t)
Q0(t+1) = D0(t) = x(t)Q1(t)
Q1(t+1) = D1(t) = x(t) + Q0(t)
 Output and State Equations

° Next state dependent on previous state.

x D0
Q1 Q0
Q
D
Q’
y
Q
D Q1
Q0 D1 Q’

Clk
Output equation
y(t) = x(t)Q1(t)Q0(t)
Q0(t+1) = D0(t) = x(t)Q1(t)
State equations
Q1(t+1) = D1(t) = x(t) + Q0(t)
State Table
° Sequence of outputs, inputs, and flip flop states
enumerated in state table
° Present state indicates current value of flip flops
° Next state indicates state after next rising clock
edge
° Output is output value on current clock edge

Present Next State Output

State x=0 x=1 x=0 x=1
00 00 10 0 0
State Table 01 10 10 0 0
10 00 11 0 0
11 10 11 0 1

Q1(t) Q0(t) Q1(t+1) Q0(t+1)

State Table
° All possible input combinations enumerated
° All possible state combinations enumerated
° Separate columns for each output value.
° Sometimes easier to designate a symbol for each
state.

Present Next State Output

State x=0 x=1 x=0 x=1
Let:
s0 = 00 s0 s0 s2 0 0
s1 = 01 s1 s2 s2 0 0
s2 = 10 s2 s0 s3 0 0
s3 = 11 s3 s2 s3 0 1
 State Diagram
° Circles indicate current state
° Arrows point to next state
° For x/y, x is input and y is output
Present Next State Output
State x=0 x=1 x=0 x=1
00 00 10 0 0
01 10 10 0 0
10 00 11 0 0
11 10 11 0 1
1/1
0/0 0/0
0/0 1/0
00 01 10 11
1/0
1/0 0/0
State Diagram

° Each state has two arrows leaving

° One for x = 0 and one for x = 1
° Unlimited arrows can enter a state
° Note use of state names in this example
° Easier to identify

1/1
0/0 0/0
0/0 1/0
s0 s1 s2 s3
1/0
1/0 0/0
 Flip Flop Input Equations

° Boolean expressions which indicate the input to

the flip flops.

x D0
Q1 Q0
Q
D
Q’
y
Q
D Q1
Q0 D1 Q’

Clk
DQ0 = xQ1
DQ1 = x + Q0 Format implies type of flop used
Analysis with D Flip-Flops

° Identify flip flop input equations

° Identify output equation

Note: this example

has no output
Mealy Machine
• Output based on state and present input

Q(t+1) Flip
Comb.
next Flops
Logic Q(t)
state present Y(t)
X(t) Comb.
state
present Logic
input
clk
 Moore Machine

• Output based on state only

Q(t+1) Y(t)
Comb. Flip Comb.
Logic next Flops Q(t) Logic
state present
X(t)
state
present
input
clk
State Diagram with One Input & One Mealy Output

° Mano text focuses on Mealy machines

° State transitions are shown as a function of
inputs and current outputs.

e.g. 1 0/0 Input(s)/Output(s) shown

in transition
1/1 S1 1/0

S4 S2
0/0
0/0
0/0
1/0 S3 1/0
State Diagram with One Input & a Moore Output

° Moore machine: outputs only depend on the

current state
° Outputs cannot change during a clock pulse if the
input variables change
° Moore Machines usually have more states.
° No direct path from inputs to outputs
° Can be more reliable
Designing Finite State Machines

° Specify the problem with words

° (e.g. Design a circuit that detects three
consecutive 1 inputs)
° Assign binary values to states
° Develop a state table
° Use K-maps to simplify expressions
° Flip flop input equations and output equations
° Create appropriate logic diagram
° Should include combinational logic and flip
flops
Example: Detect 3 Consecutive 1 inputs

0
° State S0 : zero 1s detected
° State S1 : one 1 detected
° State S2 : two 1s detected
° State S3 : three 1s detected

° Note that each state has 2 output arrows

° Two bits needed to encode state
 State Table for Sequence Detector

Present Next ° Sequence of outputs, inputs,

State Input State Output and flip flop states enumerated
A B x A B y in state table
0 0 0 0 0 0 ° Present state indicates current
0 0 1 0 1 0 value of flip flops
0 1 0 0 0 0
0 1 1 1 0 0
° Next state indicates state after
next rising clock edge
1 0 0 0 0 0
1 0 1 1 1 0 ° Output is output value on
1 1 0 0 0 1 current clock edge
1 1 1 1 1 1

° S0 = 00 ° S2 = 10
° S1 = 01 ° S3 = 11
Finding Expressions for Next State and Output Value

° Create K-map directly from state table (3 columns = 3 K-maps)

° Minimize K-maps to find SOP representations
° Separate circuit for each next state and output value
 Circuit for Consecutive 1s Detector

° Note location of state

flip flops
° Output value (y) is
function of state
° This is a Moore
machine.
Register with Parallel Load

° Register: Group of Flip-Flops

° Ex: D Flip-Flops
° Holds a Word (Nibble) of Data
° Loads in Parallel on Clock
Transition
° Asynchronous Clear (Reset)
Register with Load Control

° Load Control = 1
• New data loaded
on next positive
clock edge

° Load Control = 0
• Old data reloaded
on next positive
clock edge
Shift Registers

° Cascade chain of Flip-Flops

° Bits travel on Clock edges
° Serial in – Serial out, can also have parallel load /
read
Parallel Data Transfer
° All data transfers on rising clock edge
° Data clocked into register Y
 Parallel versus Serial

° Serial communications is defined as

• Provides a binary number as a sequence of binary digits, one
after another, through one data line.

° Parallel communications
• Provides a binary number through multiple data lines at the
same time.
 Serial Transfer
° Data transfer one bit at a time
° Data loopback for register A

Time Reg A Reg B

T0 1011 0011
T1 1101 1001
T2 1110 1100
T3 0111 0110
T4 1011 1011
Serial Transfer of Data

° Transfer from register X to register Y (negative

clock edges for this example)
Serial Addition (D Flip-Flop)

° Slower than
parallel
° Low cost
° Share fast
hardware on
slow data
° Good for
multiplexed
data
 Serial Addition (D Flip-Flop)

° Only one full

adder
° Reused for
each bit
° Start with low-
order bit
addition
° Note that carry
(Q) is saved
° Add multiple
values.
• New values
placed in shift
register B
 Serial Addition (D Flip-Flop)

° Shift control
used to stop
addition
° Generally not a
good idea to
gate the clock
° Shift register
can be
arbitrary length
° FA can be built
from combin.
logic
 Universal Shift Register

° Clear
° Clock
° Shift
• Right
• Left
° Load
° Read
° Control
Counters

° Counter: A register that goes through a prescribed

series of states
° Binary counter
• Counter that follows a binary sequence
• N bit binary counter counts in binary from n to 2n-1

° Ripple counters triggered by initial Count signal

° Applications:
• Watches
• Clocks
• Alarms
• Web browser refresh
 Binary Ripple Counter

° Reset signal sets all outputs

to 0
° Count signal toggles output
of low-order flip flop
° Low-order flip flop provides
trigger for adjacent flip flop
° Not all flops change value
simultaneously
• Lower-order flops change first

° Focus on D flip flop

implementation
Another Asynchronous Ripple Counter

° Similar to T flop example on previous slide

Asynchronous Counters

° Each FF output drives the CLK input of the next

FF.
° FFs do not change states in exact synchronism
with the applied clock pulses.
° There is delay between the responses of
successive FFs.
° Ripple counter due to the way the FFs respond
one after another in a kind of rippling effect.
A3 A2 A1 A0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
1 0 0 0
1 0 0 1
 Synchronous counters

° Synchronous(parallel)
counters
• All of the FFs are triggered
simultaneously by the clock
input pulses.
• All FFs change at same time

° Remember
• If J=K=0, flop maintains value
• If J=K=1, flop toggles

° Most counters are

synchronous in computer
systems.
° Can also be made from D
flops
° Value increments on
positive edge
Synchronous counters

° Synchronous counters
• Same counter as previous slide except Count enable replaced
by J=K=1
• Note that clock signal is a square wave
• Clock fans out to all clock inputs
 Circuit operation

° Count value increments on each negative edge

° Note that low-order bit (A) toggles on each clock
cycle
 Synchronous UP/Down counters

° Up/Down Counter can either

count up or down on each
clock cycle
° Up counter counts from 0000
to 1111 and then changes
back to 0000
° Down counter counts from
1111 to 0000 and then back
to 1111
° Counter counts up or down
each clock cycle
° Output changes occur on
clock rising edge
 Counters with Parallel Load

° Counters with parallel load

can have a preset value
° Load signal indicates that
data (I3…I0) should be
loaded into the counter
° Clear resets counter to all
zeros
° Carry output could be used
for higher-order bits
 Counters with Parallel Load

Clear Clk Load Count Function

0 X X X Clear to 0
1 ↑ 1 X Load inputs
1 ↑ 0 1 Count
1 ↑ 0 0 No Change

Function Table
° If Clear is asserted (0), the
counter is cleared
° If Load is asserted data
inputs are loaded
° If Count asserted counter
value is incremented
 Binary Counter with Parallel Load and Preset
• Presettable parallel counter with
asynchronous preset.

If PL’ = 0, load P into flops