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ECE 6130/4130: Advance VLSI Systems

Combinational Logic Styles: Part-II
Dynamic Logic
Other Styles
Prof. Saibal Mukhopadhyay
School of Electrical & Computer Engineering
Georgia Institute of Technology
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Reading Materials
Chapter 9 : Introduction to VLSI
Circuits and Systems, Uyemura,
Chapter 6: Digital Integrated Circuits:
A Design Perspectives, J. M. Rabaey,
A. Chandrakasan, B. Nikolic
Lecture notes (posted in T-square,
under Resources/Lecture Slides)
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Dynamic CMOS
In static circuits at every point in time (except
when switching) the output is connected to
either GND or V
DD
via a low resistance path.
fan-in of n requires 2n (n N-type + n P-type)
devices
Dynamic circuits rely on the temporary
storage of signal values on the capacitance of
high impedance nodes.
requires on n + 2 (n+1 N-type + 1 P-type)
transistors
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Dynamic Gate
In
1
In
2
PDN
In
3
M
e
M
p
Clk
Clk
Out
C
L
Out
Clk
Clk
A
B
C
M
p
M
e
Two phase operation
Precharge (Clk = 0)
Evaluate (Clk = 1)
on
off
1
off
on
((AB)+C)
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Conditions on Output
Once the output of a dynamic gate is
discharged, it cannot be charged again until
the next precharge operation.
Inputs to the gate can make at most one
transition during evaluation.
Output can be in the high impedance state
during and after evaluation (PDN off), state is
stored on C
L
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Properties of Dynamic Gates
Logic function is implemented by the PDN only
number of transistors is N + 2 (versus 2N for static complementary
CMOS)
Full swing outputs (V
OL
= GND and V
OH
= V
DD
)
Non-ratioed - sizing of the devices does not affect
the logic levels
Faster switching speeds
reduced load capacitance due to lower input capacitance (C
in
)
reduced load capacitance due to smaller output loading (Cout)
no I
sc
, so all the current provided by PDN goes into discharging C
L
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Properties of Dynamic Gates
Overall power dissipation usually higher than static
CMOS
no static current path ever exists between V
DD
and GND
(including P
sc
)
no glitching
higher transition probabilities
extra load on Clk
PDN starts to work as soon as the input signals
exceed V
Tn
, so V
M
, V
IH
and V
IL
equal to V
Tn
low noise margin (NM
L
)
Needs a precharge/evaluate clock
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Issues in Dynamic Design 1:
Charge Leakage
C
L
Clk
Clk
Out
A
M
p
M
e
Leakage sources
CLK
V
Out
Precharge
Evaluate
Dominant component is subthreshold current
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Solution to Charge Leakage
Precharge: Out is V
DD
and inverter out is GND, so keeper is on
Evaluation:
PDN is off => keeper compensates for leakage
PDN is on => keeper fights with PDN
Higher delay, higher short-circuit power
Proper keeper sizing is necessary to improve robustness while
ensuring a reasonable delay
C
L
Clk
Clk
M
e
M
p
A
B
Out
M
kp
Keeper
C
L
Clk
Clk
M
e
M
p
A
B
Out
M
kp
Keeper
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Issue 2: Charge Sharing
C
L
Clk
Clk
C
A
C
B
B=0
A
Out
M
p
M
e
Charge stored originally on
C
L
is redistributed (shared)
over C
L
and C
A
leading to
reduced robustness
Assume, C
A
initially
discharged and C
L
fully
charged.
A makes a 0 -> 1 transition
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Charge Sharing
C
L
V
DD
C
L
V
out
t
( )
C
a
V
DD
V
Tn
V
X
( )

( )
+ =
or
AV
out
V
out
t
( )
V
DD

C
a
C
L
-------- V
DD
V
Tn
V
X
( )

( )
= =
AV
out
V
DD
C
a
C
a
C
L
+
----------------------
\ .
|
| |
=
case 1) if AV
out
< V
Tn
case 2) if AV
out
> V
Tn
B
=
0
Clk
X
C
L
C
a
C
b
A
Out
M
p
M
a
V
DD
M
b
Clk
M
e
:
1; 2
a Tn
L DD Tn
a Tn a Tn
L DD Tn L DD Tn
C V
Boundary
C V V
C V C V
case and case
C V V C V V
=

< => > =>

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Charge Sharing Example
C
L
=50fF
Clk
Clk
A A
B
B
B
C C
Out
C
a
=15fF
C
c
=15fF
C
b
=15fF
C
d
=10fF
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2.5 0.94
80
L DD L out a out c out
a c
out DD
L a c
C V C V C V C V
C C
V V V V
C C C
= + +
+
| |
A = = =
|
+ +
\ .
B
V
DD
=2.5V, V
Tn
=0.5V
( )
0.6 0.25
2
a c L
C C C
Case
+ = >
=>
( )
0.25
Tn DD Tn
V V V =
Worst cases:
ABC or ABC
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Solution to Charge Redistribution
Clk
Clk
M
e
M
p
A
B
Out
M
kp
Clk
Precharge internal nodes using a clock-driven transistor
(at the cost of increased area and power)
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Cascading Dynamic Gates
Clk
Clk
Out1
In
M
p
M
e
M
p
M
e
Clk
Clk
Out2
V
t
Clk
In
Out1
Out2
AV
V
Tn
Only 0 1 transitions allowed at inputs!
Out2 should remain at VDD since Out1 transitions to 0
during evaluation.
A finite propagation delay for the input to discharge Out1 to
GND => the second output also starts to discharge.
The second dynamic inverter turns off (PDN) when Out1
reaches VTn.
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Domino Logic
In
1
In
2
PDN
In
3
M
e
M
p
Clk
Clk
Out1
In
4
PDN
In
5
M
e
M
p
Clk
Clk
Out2
M
kp
1 1
1 0
0 0
0 1
Ensures all inputs to the Domino gate are set to 0
at the end of the precharge period. Hence, the
only possible transition during evaluation is 0 -> 1
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Properties of Domino Logic
Only non-inverting logic can be implemented
Very high speed
static inverter can be skewed, only L-H transition
Input capacitance reduced smaller logical effort
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Designing with Domino Logic
M
p
M
e
V
DD
PDN
Clk
In
1
In
2
In
3
Out1
Clk
M
p
M
e
V
DD
PDN
Clk
In
4
Clk
Out2
M
r
V
DD
Inputs = 0
during precharge
Can be eliminated!
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Footless Domino
The first gate in the chain needs a foot switch
Precharge is rippling short-circuit current
A solution is to delay the clock for each stage
V
DD
Clk M
p
Out
1
In
1
1 0
V
DD
Clk M
p
Out
2
In
2
V
DD
Clk M
p
Out
n
In
n
In
3
1 0
0 1 0 1 0 1
1 0 1 0
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np-CMOS
In
1
In
2
PDN
In
3
M
e
M
p
Clk
Clk
Out1
In
4
PUN
In
5
M
e
M
p
Clk
Clk
Out2
(to PDN)
1 1
1 0
0 0
0 1
Only 0 1 transitions allowed at inputs of PDN
Only 1 0 transitions allowed at inputs of PUN
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How to Choose a Logic Style?
Static CMOS:
robust, ease of implementation and design automation.
Complex gates requires larger area and has lower speed
Pseudo-NMOS:
Simple and fast
Reduced robustness and static power
Pass transistor/Transmission gate:
Attractive for implementation of specific circuits: XOR,
Adders, Multiplexers
Dynamic CMOS:
High-performance and area efficient for complex gates
Reduced robustness, complex design process, and higher
power dissipation
Current Trend: Increased use of Static CMOS
Use of EDA tools for logic optimization
More suitable for voltage scaling as CMOS is more robust to
noise and noise does not scale with voltage
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Few Other Logic Styles
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Mirror Circuit
Example: XOR function table.
Equal number of input combinations that produces 0
and 1 in output
Same transistor topology for PUP and PDN paths
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XOR and XNOR mirror circuit
XOR XNOR
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Tri-state inverter
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Clocked CMOS: C
2
MOS gate.
Clock signals
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Example of clocked-CMOS logic gates.