Astable Circuits.

Astable Multivibrators are a type of free running oscillator that have no permanent "meta" or "steady" state but are continually changing there output from one state ("LOW") to the other state ("HIGH") and then back again. This continual switching action from "HIGH" to "LOW" and "LOW" to "HIGH" produces a continuous and stable square wave output that switches abruptly between the two logic levels making it ideal for timing and clock pulse applications. As with the monostable multivibrator circuit above, the timing cycle is determined by the time constant of the resistor-capacitor, RC Network. Then the output frequency can be varied by changing the value(s) of the resistors and capacitor in the circuit.

NAND Gate Astable Multivibrators

The astable multivibrator circuit uses two CMOS NOT gates such as the CD4069 or the 74HC04 hex inverter ICs, or as in our simple circuit below a pair of CMOS NAND such as the CD4011 or the 74LS132 and an RC timing network. The two NAND gates are connected as inverting NOT gates. Suppose that initially the output from the NAND gate U2 is HIGH at logic level "1", then the input must therefore be LOW at logic level "0" (NAND gate principles) as will be the output from the first NAND gateU1. Capacitor, C is connected between the output of the second NAND gate U2 and its input via the timing resistor, of R2 and C. As the capacitor, C charges up, the junction between the resistor R2 and the capacitor, C, which is also connected to the input of the NAND gate U1 via the stabilizing resistor, R2 decreases until the lower threshold value of "0" to logic "1" resulting in the output of NAND gate U2 becoming LOW, logic level "0". Capacitor C is now reverse biased and discharges itself through the input of

R2. The capacitor now charges up at a rate determined by the time constant

U1 is reached at which point U1 changes

state and the output of U1 now becomes HIGH. This causes NAND gate U2 to also change state as its input has now changed from logic

NAND gate U1. Capacitor,C charges up again in the

opposite direction determined by the time constant of both R2 and C as before until it reaches the upper threshold value of NAND gate U1. This causes U1 to change state and the cycle repeats itself over again. Then, the time constant for a NAND gate Astable Multivibrator is given as T as f

= 2.2RC in seconds with the output frequency given

= 1/T. = 10k and the capacitor C = 45nF, then the oscillation frequency will be given as:

For example: if resistor R2

then the output frequency is calculated as being

1kHz, which equates to a time constant of 1mS so the output waveform would look like:

Kuwait University Electrical Engineering Department

CMOS Timing, Logic, and Memory Circuits

Objective: The objectives of this experiment are to observe the operating characteristics of
some CMOS time base and memory circuits.

Theory: Figure 1 shows a simple and popular circuit for monostable multivibrator. The input
source supplies the triggering pulses.

Fig.1: Monostable multivibrator Fig.2: a) Diodes at each input of a two-input CMOS gate. (b) Equivalent diode circuit when the two inputs of the gate are joined together

If the input signal vI is a pulse of a time (). This must be greater than the sum of the propagation delays of gates G1 and G2. When the input pulse start to be high a sudden change of V1 occurs at vO1 and vI2

Then vO1 starts to decrease exponentially with a time constant = C*(R+Ron) and v I2 starts to increase exponentially with the same time constant where Ron is the finite output resistance of the NOR gate. So vO1 will go to ground and stay even if the triggered pulse has disappeared and goes to zero. VI2 Will continue rising to VDD but before that it will reach the threshold voltage Vth of the inverter G2. At this time vo2 will switch from VDD to ground which will cause G1 to

switch and its output will start go to VDD. First an instantaneous rise will be limited to V2 and so the input of gate G2 will rise the same amount ofV2 and because of the diode at the input of G2 it will limit V2 Look to waveforms in Figure 2.

Fig. 2: Timing diagram for the monostable circuit in Fig. 1.

As seen the monostable circuit has one stable state when the output is zero and has one quasistable state when to output is high during the time T. So it is called a pulse stretcher and also referred as one-shot circuit (fig. 3).

Fig. 3: The Monostable multivibrator (one-shot) as a functional block, shown to be triggered by a positive pulse. In addition, there are one shots that are triggered by a negative pulse.

The astable multivibrator (fig.4) has no stable state. Rather, it has two quasi-stable states and it remains in each for predetermined intervals T1 and T2. Thus the circuit oscillate with a period T=T1+T2, or a frequency f=1/T and it can be use to generate periodic pulses such as those required for clocking (fig. 5).

Fig.4: A simple Astable multivibrator circuit using CMOS gates.

Fig. 5: Waveforms for the astable circuit in . The diodes at the gate input are assumed to be ideal and thus to limit the voltage vI1 to 0 and VDD.

The ring oscillator (fig. 6) is very popular oscillator circuit. A ring oscillator is a circuit which is used for testing the speed of logic gates. An odd number of inverters is connected into a single loop, so that a change in logic state continues to propagate around the loop. The period of the

resulting oscillation is equal to the propagation delay of a single inverter times the number of inverters in the loop times two (since the change in state must make two complete round trips to restore the system to its starting state). The propagation delay of each inverter is determined by its current drive ability and the output node capacitance that it must charge and discharge. Ring oscillator tests, while commonly used to compare logic families, should normally be treated with a good deal of suspicion, because they rarely reflect the conditions that the logic gates will be operating under when in a real circuit application. The ring oscillator test will always produce an optimistic speed for the logic family, because the fan-out of each gate is only one, i.e. the output of a gate drives only one input to another gate. In a more realistic situation, the fan-out will be a good deal greater than this, since one output will typically drive 2-5 inputs. The increased fan-out will increase the output node capacitance, which will in turn increase the propagation delay time for each gate.

fig.6: (a) A ring oscillator formed by connecting three inverters in cascade. (Normally at least five inverters are used.) (b) The resulting waveform. Observe that the circuit oscillates with frequency 1/6tP.

Procedure: Precautions: This experiment will use standard 4000-series. These IC's have internal diodes to
protect the MOSFET gates; but even so, they can still be destroyed by careless handling which may produce stray electrostatic discharge (ESD). The arrangement of the gates within the package, i.e. the pin-out of the package for the HEFCD4001B IC is shown in Fig. 7. The HEF4001B provides the positive quadruple 2-input

NOR function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance.

Fig. 7: HEF4001B pin diagram

Part A) Latching Monostable Circuit

1- Connect the circuit shown in fig. 1 with: C = 0.1 F R = 1 k U = HEF4001B 2- Configure a function generator to output a square wave of 10 kHz frequency which makes transitions from a maximum voltage of +5.0 V to a minimum of 0.0 V. You will normally have to piddle with the amplitude and DC offset controls to produce this type of waveform. Make the symmetry of the signal to be 5%. 3- Connect t the oscilloscope Ch-1 to the input, and the oscilloscope Ch-2 to the output. 4- The oscilloscope should again show a positive output pulse which is now initiated by the rising edge of the input square wave. Measure the width of the output pulse. You may have to adjust the oscilloscope time base in order to get an accurate measurement. 5- Measure the width of the output pulse when C is replaced by 1 F.

Questions
(a) Derive an expression for the generated pulse period.

(b) In your notebook, draw the schematic for a latching monostable circuit which produces a negative output pulse which is initiated by the falling edge of an input trigger pulse. Label all ICs and give pin numbers to each gate input and output.

Part B) Astable circuits and Square Wave Oscillator

1- Connect the circuit shown in fig. 4 with: R1 = 50 k R2 = 100 k C1 = 0.01 F U1 = HEF4001B Implement the two inverters of Fig. 5 using gates A and B of either the CD4001B quad NOR IC or the CD4011B quad NAND IC. Use the pin-out diagram of Fig. 1 to determine the correct pin numbers to use. 2- Connect Ch-1 of the oscilloscope to the output. (This circuit is an oscillator and does not require any input signal.) 3- Adjust the time base of the oscilloscope to display the output of the oscillator circuit. 4- Measure the period of the waveform, make a sketch of the waveform in your notebook, and measure the symmetry of the waveform, i.e. the ratio of the HIGH time to the LOW time 5- Replace resistor R1 with a value of 10 k . Re-examine the output waveform and note any differences from the previous case.

Questions:
(a) Find expression for the generated period T. (b) Comment whether R1 has any effect on the frequency of the output waveform. Does R have any effect on the output waveshape or period? Why?

Part C) CMOS Ring Oscillator

1- Connect the circuit shown in fig. 8 with: C2, C3, C4 = 33 pF, 100 pF, or 1000 pF U = HEF4001B ***initially install a 33 pF capacitor for each of C2, C3, and C4.

Fig. 8 2- Connect the output of the ring oscillator to Ch-1 of an oscilloscope. Configure the oscilloscope to display only Ch-1 at 2 V/div. You will have to experiment with the timebase to fit 2 or 3 complete cycles into the display 3- Apply +5.0 Volt DC power to the breadboard and you should observe a waveform on the oscilloscope whose frequency is roughly around 1 MHz. The waveform will not look like a pretty square wave, but will have a good deal of rounding on its corners. Nevertheless, we shall still refer to this as a square wave, its shape notwithstanding. 4- Use the oscilloscope to measure the frequency of the waveform to at least two significant figures. 5- Remove all of the 33 pF capacitors and remeasure the frequency of the waveform, again to two significant figures, if possible. 6- Install 100 pF capacitors to each of the inverter output nodes and remeasure the oscillator frequency. 7- Finally, change the capacitors to 1000 pF and remeasure the oscillator frequency. 8- Now, change the capacitors back to 33 pF, and increase the DC power supply output voltage to +10.0 Volts. Remeasure the output waveform frequency. 9- Finally, increase the DC power supply output voltage to +15.0 Volts and remeasure the output waveform frequency. Be very careful to not exceed +15.0 Volts on the DC power supply, since much higher than this will destroy the CMOS integrated circuits, which are only rated at +18.0 Volts, absolute maximum.

Question:
(a) From your measured values of oscillation frequency, calculate the propagation delay of a single inverter for each of the circumstances measured above.

(b) Make a plot of propagation delay versus output node capacitance, noting that an unknown built-in capacitance is present at each node in addition to the capacitors which were intentionally added. (c) Make a plot of propagation delay versus power supply voltage. Is this plot more closely linear or quadratic in shape? (d) Explain why increasing the power supply voltage decreases the propagation delay time.