AVR Based Motor Control

Revision: June 8, 2007 .

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Overview
This document describes the process of writing software for controlling a Digilent geared motor with a Digilent PmodHB5 and an AVR based controller. Additionally it will point out the aspects of precision motor control along with the features of the AVR that can maintain such control. Design considerations are also highlighted to help decide what level of control may be needed for the project. Digilent products used for this tutorial are: motor-gearbox PmodHB5 Cerebot Robotic starter kit.

The ideas presented in this document can be applied to any of Digilent's embedded control boards, not just the Cerebot. Refer to the Atmel data sheet that applies to the board to see how the register names listed there may be different for your board. This tutorial will walk through the process of interfacing one motor with the Cerebot. By repeating this design process additional motors can be added.

Functional Description
All products listed above are designed to seamlessly integrate with one another. The motor-gearbox has a connector that directly mates with the PmodHB5 which plugs into one of the Cerebot's Pmod ports. A Pmod extension will be helpful to have to freely position the motor. Before beginning this tutorial: have familiarity with programming the Cerebot read the PmodHB5 reference manual read the Cerebot reference manual. After completing this tutorial: know how to choose what level of control is needed for projects know the principles behind precision motor control using the products listed. Different kinds of control First, decide what level of control the project requires. Listed below are a few levels of control along with their respective benefits and limitations:

Simple on/off
extremely easy to implement offers no control.

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PWM based without feedback

easy to implement while offering limited control of speed lacks complete control of speed not suited for projects requiring positioning.

PWM based with feedback

offers complete control of speed exact positioning is possible harder to implement.

Simple on/off Set up the data direction register (DDRx) bits that correspond to the Enable and Direction signals of the h-bridge for output. Then control the motor by first setting the Direction bit as desired and toggle on or off the Enable bit in the appropriate port (PORTx). It is important to know that the h-bridge was not designed for 100% duty cycle. If 100% duty cycle is expected, some kind of heat dissipation device should be implemented. Never change the Direction signal of the h-bridge when the Enable signal is high. This may short circuit the internals of the h-bridge itself. To change the direction of the motor, ensure that the Enable signal is low first, then change the Direction signal. PWM based without feedback Pulse-width modulation without feedback does not utilize the AVR's input capture capabilities, which may not be necessary for the project. Once the internal PWM hardware is set up, it does not require any further interaction with the AVR's CPU. The only time that PWM requires any CPU processing is when the duty cycle of the motor is modified. The AVR is capable of 15 different implementations of pulse-width modulation. Each of these methods accomplishes the task of controlling the duty cycle of the motor, but each method has its own challenges and drawbacks. Some offer incredible precision in controlling the length of the pulse; up to 16-bit precision, 65536 steps between on and off. However, in most cases this level of precision is not needed. To determine which method is best for an application see the Atmel data sheet that applies to the AVR on the board used. This tutorial will focus on what the data sheet identifies as Mode 5. This method offers 8-bit precision, and has 256 steps between on and off, an amount sufficient for most tasks.

Mode 5 and PWM

The methods listed on the Atmel data sheet apply to the AVR's 16-bit timers. The ATMega64L, which is located on the Cerebot, has two 16-bit timers, Timer/Counter1 and Timer/Counter3. The Cerebot was designed in such a way that both of these timers' output compare pins are handily located on Pmod port JB and JC respectively. In fact, those pins are located where the Enable signals would be if they were smartly plugged in at those locations.
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Many specific registers are referred to in this document. In these references an 'x' refers to a letter designation and an 'n' refers to a number. For example, Pin 2 on port JB of the Cerebot is connected to OCnx, where n = 1 and x = A. Mode 5 implements pulse-width modulation by pairing the timer and counter with the output compare register. The timer/counter will increment from BOTTOM, which is zero, to TOP, which in the case of Mode 5, is 255. Depending on how the timer's registers are set up, the Output Compare pin will start out high/low at BOTTOM and switch when the timer's Output Compare Register value matches that of the timer/counter. Each time the timer/counter overflows and returns to BOTTOM, the state of the OCnx pin is reset. For both timer/counter1 and timer/counter3, each has three output compare registers, potentially allowing three separate pulse-modulated pins per timer/counter. In the case of the Cerebot only OCR1A and OCR3B are of interest as these control the Enable signals on port JB and JC respectively. Certain bits are set in the timer's registers for the PWM hardware. Each bit controls a specific property of the resulting PWM signal. To completely set up one channel of PWM requires only two lines of code. As such, this document does not include any sample code. The primary registers are TCCRnA and TCCRnB. These two registers set up the PWM hardware. The secondary register is OCRnx, which defines the particular duty cycle of the motor. It is important to note that OCRnx is a 16-bit register and is made up of two 8-bit registers, OCRnxL and OCRnxH. Using Mode 5, which is limited to 8-bit resolution, the upper register, OCRnxH should be permanently written to 0, as it will never be used. Writing to OCRnxL with a value from 0 to 255 will define the duty cycle of the motor. Each bit in TCCRnA and TCCRnB has a specific purpose. The Atmel data sheet shows what each bit is and its affect on the hardware. It is essential to refer to this information.

TCCRnA is constructed as follows:

Bit name 7 6 5 4 3 2 1 0 WGMn0

COMnA1 COMnA0 COMnB1 COMnB0 COMnC1 COMnC0 WGMn1

TCCRnB is constructed as follows:

Bit name 7 ICNCn 6 ICESn 5 4 3 WGMn2 2 CSn2 1 CSn1 0 CSn0

reserved WGMn3

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Properties
The COMnx1 and COMnx0 pair is used to define the compare output mode. Here you can define what the PWM hardware will do when the compare register value matches the counter value. The WGMn0, WGMn1, WGMn2 and WGMn3 set of bits defines what mode the PWM hardware will take. For Mode 5: WGMn2 = 1, WGMn0 = 1, while the others equal zero. ICNCn enables the digital input capture filter. Enabling this feature filters out noise that may otherwise be captured by the hardware, but delays capture by four system clock cycles. This is not needed for this setup. ICESn determines if a rising edge or a falling edge triggers the input capture interrupt (not needed here). The CSn2, CSn1 and CSn0 set of bits enables the timer/clock and also defines a clock divider. This is a desirable feature because the system clock runs far faster than is needed for the PWM hardware. When calculating the clock divider for your project, remember that the motor performs more smoothly when it is pulsed at a rate faster than humans can notice.

PWM based with feedback To set up this form of motor control, set up the PWM facilities the same way as mentioned above. In addition to this, the ICNCn and ICESn bits in TCCRnB now become relevant along with another register called the Timer/Counter Interrupt Mask Register (TIMSK). While the hardware PWM may run with little to no input from the CPU, the input capture abilities of the AVR may become resource intensive. The h-bridge allows feedback from the motors to be routed to the AVR through the use of the hall-effect sensors on the back of the motors. Each revolution of the motor triggers a signal on Sensor A and Sensor B, which are separated by 90. Since the direction of the motor is controlled through the use of the h-bridge, the focus will be on the signal coming in from Sensor A. This signal gets routed to pin three on JB or JC depending on which port has been selected for use. This pin is labeled ICPn, which is the input capture pin for Timer/Counter n. The idea behind motor feedback, using the hardware timer/counter, is to measure the amount of time it takes for the motor to complete one revolution. By interpreting this measurement, software can be used to manipulate the value stored in OCRnx, which governs the duty cycle of the motor. If the motor is spinning slower than desired, increase the duty cycle of the motor. Conversely, if the motor is spinning too fast, reduce the duty cycle of the motor. Alternatively, a counter variable that gets incremented/decremented during each revolution of the motor can be implemented depending on the direction and use that counter value to determine the position of the motor. This is how industrial servo motors operate, that control the position of some resource like a robotic arm or tool in a CNC machine. Pair this with the ability to control the velocity of the motor and you have an advanced servo motor that can be implemented in a vast range of devises.

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AVR Based Motor Control

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The additional registers involved in this added layer of control are:

TIMSK
Bit name 7 OCIE2 6 TOIE2 5 TICIE1 4 OCIE1A 3 OCIE1B 2 TOIE1 1 OCIE0 0 TOIE0

Properties
OCIE2, TOIE2, OCIE0 and TOIE0 refer to other timers that we are not using TICIE1 enables an interrupt upon an input capture event OCIE1A enables a compare match interrupt and can be ignored OCIE1B enables a compare match interrupt and can be ignored TOIE1 enables an interrupt when timer/counter1 overflows. This can be a useful feature if the input capture event occurs less often than the PWM refresh rate.

ETIMSK
Bit name 7 reserved 6 5 4 OCIE3A 3 OCIE3B 2 TOIE3 1 OCIE3C 0 OCIE1C

reserved TICIE3

refers to the timer/counter3 interrupt properties TICIEn and TOIEn operate in the same way as found in TIMSK.

When using interrupts, make sure that global interrupts are enabled. Also, make sure you pay attention to the amount of CPU time, and frequency of each interrupt.

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