Modeling Finite-State Machines and ASM Charts

Finite state machines are widely used for modeling memory components, such as ip-ops, as well as controllers for synchronous datapath and register operations of a computer. Hence they have both theoretical and practical importance. Finite state machines also have applications in several areas of computing, including cellular automata, natural computing, natural language processing and recognition, compiler theory, and text processing to name just a few. Finite state machines solve problems that require only a nite amount of memory, irregardless of the problem size. A nite state machine (FSM) consists of a 6-tuple (Q, , , , , q0 ), where 1. Q is a nite set of states. 2. is a nite set, called the input alphabet. 3. is a nite set, called the output alphabet. 4. is a transition function that determines the next state of the automaton given the current state and the current input. In other words, : Q Q, 5. is an output function that determines the output of the FSM given the current state and the current input. In other words, : Q , is a mapping from (current) state-input ordered pairs to an output symbol. 6. q0 Q is the initial state.

A graphical way of representing an FSM is to represent the states with graph nodes, with an arrow pointing at the initial state. Furthermore, a directed edge labeled with s/t starts at node qi and terminates at node qj i (qi , s) = qj and (qi , s) = t. Example 1. Provide a state diagram for an FSM whose current output is the mod 2 sum of all input bits that have thus far been witnessed. For example, if M if fed an input sequence of 10001110, then its output sequence is 11110100.

FSM computation. Let M = (Q, , , , , q0 ) be an FSM, and w = w1 w2 wn be a word in . Then the computation of M on input w is a sequence (q0 , t0 ), (q1 , t1 ), . . . , (qn1 , tn1 ), (qn , tn ) of state-output pairs dened recursively by 1. q0 is the initial state of M and t0 = (q0 , w1 ). 2. qi = (qi1 , wi ), for every 1 i n, and ti = (qi , wi+1 ), for every 1 i n 1, while tn = tn+1 . In words, the computation of M on input w is the sequence of state-outputs (q0 , t0 ), (q1 , t1 ), . . . , (qn1 , tn1 ), (qn , tn ) that M transitions through when successively reading input symbols w1 , w2 , . . . , wn . The word t0 t1 tn1 is called the output of M on input word w. Example 2. Provide an FSM that, on input w {0, 1} outputs the quotient of w/3.

Mealy vs. Moore Machines. Another name for an FSM as we dened it above is Mealy machine, since depends on both the current state and the current input. If depends on the current state only, then M is called a Moore machine. Example 3. Provide the state diagram for an FSM modulo 4 counter with input alphabet = {00, 01, 10, 11}, where the rst bit represents the value of signal e which enables the counter, and the second bit is a reset signal which resets the counter to zero when it is set to 1. The output of the FSM is the current value of the counter.

Comments on the implementation of nite state machines in hardware. Given a nite-state machine M . the states of M are encoded using one or more synchronous ip-ops state transitions occur during a clock edge transition (e.g. from low to high) the next state and output (in case of Mealy) are determined by the current state and current input, but the actual transition to the next state occurs at the next clock-edge transition (e.g. from low to high). Once the clock returns to low, the current state (and output in the case of Moore) will be stabilized until the next rising edge.

Mealy-Machine Architecture:

Moore-Machine Architecture:

Specifying an FSM in Verilog Example 4. This examples gives an explicit specication of the Mealy machine from Example 1 with a reset input added. module parity_check(parity, s, clk, reset); input s, clk, reset; output parity; reg parity; parameter S0= 1b0, S1= 1b1; reg state, next_state; always @(posedge clk or posedge reset) begin if(reset == 1b1) state <= S0; else @(negedge clk) state = next_state; end; always @(state or s) begin case (state) S0: if(s == 1b0) begin parity = 1b0; next_state = S0; end else if(s == 1b1) begin parity = 1b1; next_state = S1; end S1: if(s == 1b0) begin parity = 1b1; next_state = S1; end else if(u == 1b1) begin parity = 1b0; next_state = S0; end endcase end endmodule

Algorithmic State Machines Algorithmic state machines are similar to nite state machines, yet are more expressive in that, during each state (i.e. clock cycle), register operations may be specied and performed during the transition (i.e. next positive clock transition) from the current state to the next state. An algorithmic-state-machine (ASM) chart consists of a set of n 1 blocks B1 , . . . , Bn . Each block B may be viewed as a directed simple graph that has three kinds of nodes: state node (box). B has one state node which is symbolically represented as a rectangular box. The state node represents which state the system is in when block B is being executed. Within the box one may list one or more register operations that take place during the next rising clock edge when control passes from B to the next block/state. The state box has outdegree 1, and the edge leaving the state box may 1. loop back to itself, 2. be directed towards the state box of a dierent block, or 3. be directed to a decision box within B. binary decision node. A decision node is symbolically shaped like a diamond. Within the node is a binary predicate P which is a function of one or more net or register values. A binary decision node has two edges leaving it: one for each possible value of P . Edges leaving the decision node may 1. be directed towards the state box of any block, 2. another decision node within B, or 3. a conditional node. conditional node (box). A conditional node is symbolically shaped like a rectangular box with rounded sides. Within the box are one or more register operations that take place during the next rising clock edge, on condition that execution passes through the box. Edges leaving the condtional box may 1. be directed towards the state box of any block, or 2. another decision node within B. Suppose that block B is being executed, and let n be a node of B. We say that execution passes through n i one of the following is true. 1. n is the state box for B 2. execution passes through a parent p of n, and p is not a decision node 3. execution passes through a decsision-node parent p of n, and the edge from p to n is consistent with the evaluation of predicate P , where P is the predicate associated with p 8

Example 5. Use an ASM chart to design an unsigned 8-bit counter which has the ability to reset, and count up by either one, two, or three. The synchronous inputs to the counter are a reset signal R, and a two-bit signal X which denotes the amount that the counter should increment by. The output is the value of the counter expressed as an 8-bit vector.

Example 6. Use the ASM chart to give an architectural view of the counter specied in the previous example.

10

Example 7. Use an ASM chart to design an 8 8 multiplier using one or more shift registers.

11