CSE 151-- Intro to VLSI Design

Fadi J. Kurdahi

EECS Dept., UC Irvine
Fall 2011

Lecture 3: Semiconductors
Lecture 4: MOS Transistors intro

Adapted from Digital Integrated Circuits: A Design Perspective, 2
nd
Ed. PH
2003. J. Rabaey, A. Chandrakasan, B. Nikolic
Credits
Slides used in this course have been adapted
from the following two sources:
Course slides by the textbook author:
http://bwrc.eecs.berkeley.edu/Icbook/slides.htm
Course slides adapted from above by:
http://bwrc.eecs.berkeley.edu/IcBook/slides_PennState.htm
Many applets, animations, videos from the internet. See
sources next to each item in the slides.

All materials on this page and its sub-pages and all linked files are copyright 2003 by Prentice-Hall/Pearson Education, and
may be downloaded and printed for instructional purposes by instructors using the book. Permission is given to incorporate
excerpts of these materials in instructors' classroom presentations and handouts. The following credit line should be included:
"Adapted from (complete bibliographic citation). Copyright 2003 Prentice Hall/Pearson."
Permission expressly is not given to publish these materials, in either original or modified form, in printed, electronic, or any
other format.

2
3
Overview of Last Lecture
Digital integrated circuits experience exponential
growth in complexity (Moores law) and performance
Design in the deep submicron (DSM) era creates new
challenges
Devices become somewhat different
Global clocking becomes more challenging
Interconnect effects play a more significant role
Power dissipation may be the limiting factor
Our goal in this class will be to understand and design
digital integrated circuits in the deep submicron era
4
Goal of this chapter
Present intuitive understanding of device
operation
Introduction of basic device equations
Introduction of models for manual
analysis
Introduction of models for SPICE
simulation
Analysis of secondary and deep-sub-
micron effects
Future trends


Very quick review of basic circuits
Field
Current
Resistance
Capacitance
Ohms law
Electric Field
E=F/q (F = electric force, q= charge)
+
+
+
+
+
+
+
+
-
-
-
-
-
-
-
-
E
http://www.absorblearning.com/media/item.action?quick=6l#
Current Flow
The flow of charges through a conductor gives rise to a current
Resistance
Electrons are
scattered as they
move.
Impedes the flow of
current through
material
Resistance affected
by: material, length,
cross section
Dissipates power as
heat
Factors affecting Resistance
http://phet.colorado.edu/sims/resistance-in-a-wire/resistance-in-a-wire_en.html
Capacitors
http://micro.magnet.fsu.edu/electromag/java/lig
htning/index.html
http://micro.magnet.fsu.edu/electromag/java/capacitance/index.html
Factors affecting capacitance
Plate area
Spacing between plates
Type of dielectric
C = e*A/d
e = dielectric
A= area
d = thickness
Ohms Law
http://phet.colorado.edu/sims/ohms-law/ohms-law_en.html
Kirchhoffs Laws
http://en.wikipedia.org/wiki/Kirchhoff%27s_circuit_laws
14
A First-Order RC Network
v
out
v
in C
R
t
p
= ln (2) t = 0.69 RC
Important model matches delay of inverter
RC Network Simulation
http://www.youtube.com/watch?v=8Pnsbh0DrE4
Conductors, insulators and Semiconductors
17
Semiconductors
Pure semiconductors have low and equal
concentrations of electrons and holes low
electrical conductivity
Si has 4 valence electrons
Phosphorous, arsenic, etc.. Have 5 electrons
provide one free electron
Silicon doped w/these material becomes n-type
Dual argument applies for trivalent material (e.g.
Boron, gallium) p-type
18
Venturecaplaw

|

FEBRUARY 10, 2010
Semiconductor Devices Module 1 Theory Lesson 1 Segment 4 set1s4,
19
Intrinsic and Extrinsic Semiconductors
http://www.youtube.com/watch?v=o-PPbmMm0eA&feature=related
20
Semiconductors
Source: http://php.scripts.psu.edu/users/i/r/irh1/SWF/Semiconductors.swf
21
The Diode
n
p
p
n
B A
SiO
2
Al
A
B
Al
A
B
Cross-section of pn -junction in an IC process
One-dimensional
representation diode symbol
Mostly occurring as parasitic element in Digital ICs
Doped
w/acceptor
impurities
(e.g. Boron).
Mostly Holes
Doped
w/donor
impurities
(e.g.
Phosphorus).
Mostly
Electrons
Diodes
22 http://www.youtube.com/watch?v=W6QUEq0nUH8&feature=related
Diode Properties
23 http://www-g.eng.cam.ac.uk/mmg/teaching/linearcircuits/diode.html
24
Review: Diode
The ideal diode equation (for both forward and reverse-
bias conditions) is
I
D
= I
S
(e
V
D
/ |
T 1)


where V
D
is the voltage applied to the junction
a forward-bias lowers the
potential barrier allowing
carriers to flow across the
diode junction
a reverse-bias raises the
potential barrier and the
diode becomes nonconducting
|
T
= kT/q = 26mV at 300K
I
S
is the saturation current of the diode
+
-
V
D
-0.5
0.5
1.5
2.5
-1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1
V
D
(V)
Diode Animation
25
The MOS Transistor
Polysilicon
Aluminum
26
The NMOS Transistor Cross Section
n areas have been doped with donor ions
(arsenic) of concentration N
D
- electrons
are the majority carriers
p areas have been doped with acceptor
ions (boron) of concentration N
A
- holes
are the majority carriers
Gate oxide (SiO
2
)
n+
Source Drain
p substrate
Bulk (Body)
p+ stopper
Field-Oxide
(SiO
2
) n+
Polysilicon
Gate
L
W
27
MOSFET Operation
http://www-g.eng.cam.ac.uk/mmg/teaching/linearcircuits/mosfet.html
http://www-g.eng.cam.ac.uk/mentor/IIA/VLSI/CMOS1/CMOS1.html
The MOS Capacitor (Reference)
MOS Transistors as Switches
29
http://tams-www.informatik.uni-hamburg.de/applets/cmos/cmosdemo.html
30
Switch Model of NMOS Transistor
Gate
Source
(of carriers)
Drain
(of carriers)
| V
GS
|
| V
GS
| < | V
T
|
| V
GS
| > | V
T
|
Open (off) (Gate = 0)
Closed (on) (Gate = 1)
R
on
31
Switch Model of PMOS Transistor
Gate
Source
(of carriers)
Drain
(of carriers)
| V
GS
|
| V
GS
| > | V
DD
| V
T
| | | V
GS
| < | V
DD
|V
T
| |
Open (off) (Gate = 1)
Closed (on) (Gate = 0)
R
on
In reality
Gate
Source
(of carriers)
Drain
(of carriers)
| V
GS
|
| V
GS
| < | V
T
|
| V
GS
| > | V
T
|
Open (off) (Gate = 0)
Closed (on) (Gate = 1)
(Small) R
on
(Large) R
off
Same for PMOS
33
Threshold Voltage Concept
S
D
p substrate
B
G
V
GS

+


-


n+ n+
depletion
region
n
channel
The value of V
GS
where strong inversion occurs
is called the threshold voltage, V
T
34
The Threshold Voltage
V
T
= V
T0
+ (\|-2|
F
+ V
SB
| - \|-2|
F
|)
Where
V
T0
is the threshold voltage at V
SB
= 0 and is mostly a
function of the manufacturing process
V
SB
is the source-bulk voltage
|
F
= -|
T
ln(N
A
/n
i
) is the Fermi potential (|
T
= kT/q = 26mV at
300K is the thermal voltage; N
A
is the acceptor ion concentration; n
i
~
1.5x10
10
cm
-3
at 300K is the intrinsic carrier concentration in pure silicon)
= \(2qc
si
N
A
)/C
ox
is the body-effect coefficient (impact
of changes in V
SB
) (c
si
=1.053x10
-10
F/m is the permittivity of silicon;
C
ox
= c
ox
/t
ox
is the gate oxide capacitance with c
ox
=3.5x10
-11
F/m)
35
The Body Effect
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
-2.5 -2 -1.5 -1 -0.5 0
V
BS
(V)
V
SB
is the substrate bias
voltage (normally positive for n-
channel devices with the body
tied to ground)

A negative bias causes V
T
to
increase from 0.45V to 0.85V

Can use this trick to help with
power consumption reduces
leakage currents (but slows down
the gate)

VSB always has to be larger
than 0.6V in an NMOS device;
otherwise the source-body diode
becomes forward biased


36
Transistor in Linear Mode
S
D
B
G
n+ n+
Assuming V
GS
> V
T
V
GS
V
DS
I
D
x
V(x)

-

+

The current is a linear function of both V
GS
and V
DS.
I
D
= F(V
GS
and V
DS
)
37
Voltage-Current Relation: Linear Mode
For long-channel devices (L > 0.25 micron)
When V
DS
s V
GS
V
T

I
D
= k
n
W/L [(V
GS
V
T
)V
DS
V
DS
2
/2]
where
k
n
=
n
C
ox
=
n
c
ox
/t
ox
= is the process
transconductance parameter (
n
is the carrier mobility
(m
2
/Vsec))
k
n
= k
n
W/L is the gain factor of the device
For small V
DS
, there is a linear dependence between V
DS

and I
D
, hence the name resistive or linear region
38
Transistor in Saturation Mode
S
D
B
G
V
GS
V
DS
> V
GS
- V
T
I
D
V
GS
- V
T
-

+

n+ n+
Pinch-
off
Assuming V
GS
> V
T
V
DS
The current remains constant (saturates).

39
Voltage-Current Relation: Saturation Mode
For long channel devices
When V
DS
> V
GS
V
T

I
D
= k
n
/2 W/L [(V
GS
V
T
)
2
]
since the voltage difference over the induced
channel (from the pinch-off point to the source)
remains fixed at V
GS
V
T
Some caveats (see the textbook) so I
D
is not
100% constant.
40
Current Determinates
For a fixed V
DS
and V
GS
(> V
T
), I
DS
is a function
of
the distance between the source and drain L
the channel width W
the threshold voltage V
T
the thickness of the SiO
2
t
ox
the dielectric of the gate insulator (SiO
2
) c
ox

the carrier mobility
for nfets:
n
= 500 cm
2
/V-sec
for pfets:
p
= 180 cm
2
/V-sec
41
Long Channel I-V Plot (NMOS)
0
1
2
3
4
5
6
0 0.5 1 1.5 2 2.5
V
DS
(V)
X 10
-4
V
GS
= 1.0V
V
GS
= 1.5V
V
GS
= 2.0V
V
GS
= 2.5V
Linear Saturation
V
DS
= V
GS
- V
T
NMOS transistor, 0.25um, L
d
= 10um, W/L = 1.5, V
DD
= 2.5V, V
T
= 0.4V
cut-off
42
Current-Voltage Relations
Long-Channel Device
43
Short Channel Effects
0
10
0 1.5 3
(V/m)
For an NMOS device with L of .25m, only a couple of volts
difference between D and S are needed to reach velocity
saturation

c
=
Behavior of short channel device mainly due to

Velocity saturation the
velocity of the carriers
saturates due to scattering
(collisions suffered by the
carriers)

5

44
Voltage-Current Relation:
Velocity Saturation
For short channel devices
Linear: When V
DS
s V
GS
V
T

I
D
= k(V
DS
) k
n
W/L [(V
GS
V
T
)V
DS
V
DS
2
/2]
where
k(V) = 1/(1 + (V/
c
L)) is a measure of the degree
of velocity saturation

Saturation: When V
DS
= V
DSAT
> V
GS
V
T

I
DSat
= k(V
DSAT
) k
n
W/L [(V
GS
V
T
)V
DSAT
V
DSAT
2
/2]

45
Velocity Saturation Effects
V
DSAT
< V
GS
V
T
so
the device enters
saturation before V
DS

reaches V
GS
V
T
and
operates more often in
saturation

For short channel devices
and large enough V
GS
V
T
I
DSAT
has a linear dependence wrt V
GS
so a reduced
amount of current is delivered for a given control
voltage
0
10
46
Short Channel I-V Plot (NMOS)
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5
V
DS
(V)
X 10
-4
V
GS
= 1.0V
V
GS
= 1.5V
V
GS
= 2.0V
V
GS
= 2.5V
NMOS transistor, 0.25um, L
d
= 0.25um, W/L = 1.5, V
DD
= 2.5V, V
Early Velocity
Saturation
Linear Saturation
47
MOS I
D
-V
GS
Characteristics
Linear (short-channel)
versus quadratic (long-
channel) dependence of
I
D
on V
GS
in saturation

Velocity-saturation
causes the short-
channel device to
saturate at substantially
smaller values of V
DS

resulting in a substantial
drop in current drive

(for V
DS
= 2.5V, W/L = 1.5)
0
1
2
3
4
5
6
0 0.5 1 1.5 2 2.5
V
GS
(V)
X 10
-4
48
Short Channel I-V Plot (PMOS)
-1
-0.8
-0.6
-0.4
-0.2
0
0 -1 -2
V
DS
(V)
X 10
-4
V
GS
= -1.0V
V
GS
= -1.5V
V
GS
= -2.0V
V
GS
= -2.5V
PMOS transistor, 0.25um, L
d
= 0.25um, W/L = 1.5, V
DD
= 2.5V, V
T
= -0.4V
All polarities of all voltages and currents are reversed

49
The MOS Current-Source Model
V
T0
(V) (V
0.5
) V
DSAT
(V) k(A/V
2
) (V
-1
)
NMOS 0.43 0.4 0.63 115 x 10
-6
0.06
PMOS -0.4 -0.4 -1 -30 x 10
-6
-0.1
S D
G
B
I
D
I
D
= 0 for V
GS
V
T
s 0

I
D
= k W/L [(V
GS
V
T
)V
min
V
min
2
/2](1+V
DS
)
for V
GS
V
T
> 0

with V
min
= min(V
GS
V
T
, V
DS
, V
DSAT
)
and V
GT
= V
GS
- V
T
Determined by the voltages at the four terminals and a set of five
device parameters

PSPICE
Simulating Circuits
PSPICE
51
The Transistor Modeled as a Switch
0
1
2
3
4
5
6
7
0.5 1 1.5 2 2.5
V
DD
(V)
x10
5
S
D
R
o
n
V
GS
> V
T
V
DD
(V) 1 1.5 2 2.5
NMOS(kO) 35 19 15 13

PMOS (kO) 115 55 38 31

(for V
GS
= V
DD
,
V
DS
= V
DD
V
DD
/2)
Modeled as a switch with infinite
off resistance and a finite on
resistance, R
on

Resistance inversely
proportional to W/L (doubling
W halves R
on
)

For V
DD
>>V
T
+V
DSAT
/2, R
on

independent of V
DD

Once V
DD
approaches V
T
,
R
on
increases dramatically
R
on
(for W/L = 1)
For larger devices divide
R
eq
by W/L
52
Circuit: The CMOS Inverter
V
DD

V
out

C
L

V
in