ECE531 Cadence Simulation Tutorial

Haibo Wang Southern Illinois University Carbondale 1. Cadence Setup

1. Add Cadence executable into your computer search path by: (a) Copy path le .cadence.ece531 from directory /staff2/magic/ece531 to your home directory (e.g. at your home directory type cp /staff2/magic/ece531/.cadence.ece531 .) (b) Insert command line source .cadence.ece531 into your .cshrc le (if you already have a similar command line, just modify it.) 2. Create a directory that will contain all your design. (e.g. mkdir ece531). We will refer this directory as your project directory in later discussion. 3. Copy library setup le cds.lib from directory /staff2/magic/ece531 to your project directory. 4. Copy device model le models.m from directory /staff2/magic/ece531 to your project directory. 5. Verify your Cadence setup (a) Invoke Cadence tool: Open a new command terminal, go to your project directory, type icms &. The Cadence command interface window (CIW) as shown in Figure 1 should pop up.

Figure 1. Cadence CIW with Tools menu opened.

(b) Open Library Manager window: From the CIW pull down Tools menu (the second menu from the left) and select Library Manager (LM) as shown in Figure 1. The Library Manager window pops up as shown in Figure 2. (c) Open Design: From LM library column (the rst column) select (by left clicking it) library a2dlib. Then the cell column (the second column) lists all the cells contained in the selected library. Select cell test veri spec. Thereafter, the view column (the third column) lists all the views of the selected cell. Move curse to view con guration and right click mouse to bring up an action window as shown in Figure 2. Select Open (ReadOnly) from the action window (when you open your own design, select Open). It results in a new window as show in Figure 3. Select both Yes radio buttons. Then, click OK to close it. This results in both conguration (hierarchy) and schematic views of cell test veri spec being opened as shown in Figure 4 and 5. (d) Open Analog Environment: From the schematic window (shown in Figure 5), pull down Tools menu (the rst menu from the left) and select Analog Environment. The Analog Design Environment (ADE) window as shown in Figure 6 will pop up. 1

Figure 2. Cadence Library Manager with an opened action window.

Figure 3. Open conguration window.

Figure 4. Conguration view.

(e) Select simulation tool and specify simulation directory: From the ADE window, pull down Setup menu (the second menu from the left) and select simulator/Directory/Host. A new window as shown in Figure 7 pops up. Select simulation tool as SpectreVerilog; specify simulation directory as /simulation; set host as local. Click OK to close it. (f) Specify device model: From the ADE window, pull down Setup menu and select model libraries. A new window as shown in Figure 8 pops up. Type the model le name models.m with its full directory path. Click Add button to add it the simulation environment. Click OK button to close the window. (g) Congure simulation type: From the ADE window, pull down Analyses menu (the third menu from the left) and select choose. A new window as shown in Figure 9 pops up. Select tran button. Type 2u at the stop time lling-up blank. Close OK button to close it. (h) Select signals to be plotted: From the ADE window, pull down Outputs menu (the fth menu from the left) and select To Be Plotted to bring up another menu. Select Select On Schematic from the new menu. This will bring the schematic window to the front. Click nets labeled as vin, inv out, and out in the schematic window. This adds these three signals to the output panel in the ADE window. The selected signals will be plotted after simulation. (i) Run simulation: In the ADE window, click the Netlist and simulate icon (the green light icon, it is the sixth 2

Figure 5. Schematic view.

Figure 6. Analog Environment window.

Figure 7. Simulation conguration window.

Figure 8. Specifying device model.

icon from the top at the right side of the ADE window) to start the simulation. After simulation, the selected signals are plotted in a waveform window as shown in Figure 10. The top panel shows digital signal out, which is either logic 1 or 0. The bottom panel shows analog signals vin and inv out.

Figure 9. Conguring simulation type.

Figure 10. Simulation results.

2. Working on your own design

2.1 Creating your library
The rst step to working on your own design is to create your own library. In the LM window, open File menu (the rst from the left) and select New menu item to bring a sub menu. Select Library from the sub menu. This brings up a new window as shown in Figure 11 to let you type your library name (in the following discussion we assume that the name of the created library is ece531). After that, the third window as shown in Figure 12 is popped up. If you do not want to use a specic technology, just click Dont need a techle as shown in Figure 12. This completes the creation of your library. You should see it in the Library Manager window.

Figure 11. Specifying library name.

Figure 12. Specifying technology.

If you want to create a library that uses IBM7wl technology, rst add the following line into the cds.lib le before creating the new library. DEFINE bicmos7wl /cadence/IBM PDK/bicmos7wl/V1.1.0.6DM/cdslib/bicmos7wl Then, in the technology conguration window (shown in Figure 12) click Attach to an existing techle. After you click OK, a new window as shown in Figure 13 pops up. Select bicmos7wl and click OK to close the window. After that, copy the necessary les to your project directory by the following commands (assume that you type these commands in your project directory): cp /cadence/IBM cp /cadence/IBM cp /cadence/IBM cp /cadence/IBM PDK/bicmos7wl/V1.1.0.6DM/cdslib/examples/.* . PDK/bicmos7wl/V1.1.0.6DM/cdslib/examples/add text.le . PDK/bicmos7wl/V1.1.0.6DM/cdslib/examples/local.rsf . PDK/bicmos7wl/V1.1.0.6DM/cdslib/bicmos7wl/display.drf .

Figure 13. Specifying bicmos7wl technology.

Note: Unless you really think you will use ibm7wl technology, DO NOT attach ibm7wl techle when creating your library.

2.2 Creating your design: a simple common-source amplier

In the LM window, select library ece531. Then, open File menu (the rst from the left) and select new menu item to bring up a sub menu. Select Cell View from the sub menu. This results in a new window as shown in Figure 14. Type the cell name as amp. Select Tool as Composer-Schematic. The view name will become schematic automatically. Click OK to close this window. It brings a schematic window as shown in Figure 15 (the initial schematic window will not have these circuit components). In the schematic window, click the instance icon (the 10th icon from the top at the left side of the schematic window) to bring component window as shown in Figure 16. Note that you can also get the component window by pulling down Add menu and select instance. In the component window, you can specify from which library you want to get component as well as the component name, view, and parameters. Congure the component window as shown in Figure 16 (except device size) and click OK. It brings a NMOS device symbol. Left click mouse to place the NMOS device. Similarly, place a resistor (res), DC voltage source (vdc), sine-wave voltage source (vsin), and ground (gnd) into the schematic as shown in Figure 15. All the components used in this circuit are from library analogLib. Their parameters are summarized in Table 1. Note that you can specify these parameters in component windows when you instantiate these components. If you want to change any component parameter later, you can select the corresponding component by left clicking it and then click the property icon (the 9th icon from the top). It will bring up the component window to allow you modify component parameters. 5

Figure 14. Conguring new cell.

Figure 15. Schematic view of a simple common-source amplier.

Figure 16. Component window.

Add output pin V1 by clicking the pin icon (the 14th icon from the top). The pin conguration window as shown in Figure 17 will appear. Type the pin name and congure the pin type as output. Click OK to close the window and place the pin to its proper position. Click the wire icon (the 11th icon from the top), wire all the components as shown in Figure 15. Click the wire Name icon (the 13th icon from the top) to bring up the wire name window as shown in Figure 18. Type vin in the wire name lling-up blank. Click hide button to close the window. Move mouse on the schematic window to attach the wire name to its corresponding wire. Finally, click the Check and Save icon (the rst icon from the top). It performs 6

Table 1. Component parameters.

Component NMOS device Resistor DC voltage source Sine-wave voltage source

Component (cell) name nmos4 res vdc vsin

Parameters l=1, w = 5, model name = nmos r = 22.5K DC voltage = 5V offset voltage=1.5V, amplitude=0.1V, freq=1M

electrical rule check and saves your design if there are no errors and warnings in the schematic.

Figure 17. Pin conguration window.

Figure 18. Adding wire name window.

2.3 Performing analog (spectre) simulation

In the schematic window (shown in Figure 15), pull down Tools menu and select Analog Environment to bring up the ADE window. Following the steps discussed in Section 1 5(e)5(i) to set simulation tool as Spectre (note it is not SpectreVerilog this time), specify device model models.m (with its full path), select transient simulation (tran) for 10u, select signals vin and V1 to be plotted, and run simulation. The simulated waveform is shown in Figure 19. The bottom waveform is the amplier input and the top waveform is the amplied signal.

Figure 19. Spectre simulation output.

2.4 Modeling digital components in analog domain

In mixed-signal design, digital components are frequently used. During early simulation, designers may prefer to use behavioral models, instead of detail circuit implementations, to save time. One option in modeling digital components is to use Verilog-A hardware description language (HDL). The advantages of this approach include: (1) it requires only analog simulation tools during simulation; (2) it can model analog behaviors of digital circuits. However, its major drawback comes from the difculty to model complex digital systems. In the following example, we will use Verilog-A HDL to model a digital inverter. Also, we will instantiate the inverter into the amplier circuit we just created. 2.4.1 Creating Verilog-A view of inverter Following the steps in Section 2.2 to open a cell creation window. Congure the window as shown in Figure 20 and close it. A new window named as Invoke Modelwriter will pop up. Click Cancel button to skip the use of Modelwriter (you can explore how to use Modelwriter by yourself). After that, a text editor window will pop up. Modify the Verilog-A code in the text editor window as shown in Figure 21. If the text window does not pop up and an error message cannot ne texteditor or something similar appears in the CIW, you need exit icms tool and add the following command line setenv EDITOR /opt/SUNWspro/bin/nedit in your .cshrc le. After that, open a new terminal and invoke icms tool. There are numerous Verilog-A tutorial available on Internet. You can understand the given code by reading any of these tutorials. Also, Library ahdlLib contains many components implemented using Verilog-A code. You can use them as examples or templates in your design.

Figure 20. Cell conguration window.

After you save and exit the text editor window, if there are syntax errors in your code, an error message window will appear. You can correct these errors accordingly. If there are no errors in your code and there is no existing symbol for this cell, a window as shown in Figure 22 will appear to ask if you want to create a symbol for this cell. Clicking Yes button brings up another window as shown in Figure 23 to allow you specify pin locations. Click OK to close it and the symbol edit window will pop up as shown in Figure 24. In this window, you can modify the symbol into a new shape as shown in Figure 25. Click save icon and close this window. 2.4.2 Instantiating the created inverter Open the schematic view of cell amp from the LM window. Add the inverter to the circuit as shown in Figure 26. Following the steps described in Section 2.3, perform analog simulation for the modied circuit and plot signals vin, V1, and Vout. The simulated waveforms are shown in Figure 27.

2.5 Modeling digital components in digital domain

To model complex digital components (such as arithmetic circuits, nite state machines, etc), it is convenient to use Verilog HDL. In the following, we discuss how to simulate circuits consisting of both analog and digital components in Cadence design environment. 2.5.1 Creating Verilog view of inverter Following the steps in Section 2.2 to open a cell creation window. Congure the window as shown in Figure 28 and close it. A text editor window will pop up for editing Verilog code. Modify the Verilog code as shown in Figure 29. There are various Verilog Tutorial available on Internet. You can nd one from ECE428 class website (www.engr.siu.edu/haibo/ece428/notes).

Figure 21. Inverter Verilog-A code.

Figure 22. Symbol creation prompt window.

Figure 23. Conguring symbol pin locations.

2.5.2 Creating conguration view So far, cell inverter has three views: symbol, veriloga, and verilog. In particular, symbol is used for component instantiation. Both veriloga and verilog can be used in simulation. This leads to the question how to chose a view in simulation. This is addressed by using cell conguration view. How to create a conguration view is the focus of this sub section. Following the steps in Section 2.2 to open a cell creation window, congure the window as shown in Figure 30 and close it. Two new windows as shown in Figure 31 and 33 will pop up. In the front window (Figure 31), type schematic at the blank following view item. Then click Use Templates button to pop up another window. In the new window, select spectreVerilog as shown in Figure 32. Click OK buttons to close both windows. After these steps, the back window will look like what is shown in Figure 33. Click Save icon (the third icon at the top from the left) and close this window. This completes the creation of conguration view of cell amp. You should see it in the LM window view column.

Figure 24. Automated generated inverter symbol.

Figure 25. Modied inverter symbol.

2.5.3 Performing mixed-signal simulation Following the steps described in Section 1 5(c)5(i), open both conguration and schematic views of cell amp, open the ADE window, set simulation tool (spectreVerilog), specify model le, select analysis type (transient simulation for 10u), and select signals to be plotted (vin, V1 and vout). In the conguration window (Figure 33), the view found column for cell inv should be verilog. If it is not verilog, move mouse to view to use column at cell inv row, right click mouse to pop a menu, click Set View, and select verilog as shown in Figure 34. Click the Update icon (the 8th from the left) to update the change. With the above conguration, there are two types of components in the circuit. The simple amplier is an analog circuit. Its input and output are represented by continuous values. The inverter is a digital component, its input and output are discrete values, particularly 1 or 0. Although, a single wire is used to connect the output of the amplier to the inverter input in the schematic, simulator will insert an analog to digital (a2d) converter between the amplier output and inverter input during simulation. Parameters of the inserted a2d converter are specied as follows. After the ADE window is opened, a new menu mixed-signal is added to the schematic window. Pull down the mixed-signal menu and select Interface Elements. From the Interface Elements sub menu select Library as shown in Figure 35. This brings up the interface conguration window. Congure the interface window as shown in Figure 36. In this window, we specify the delay of analog to digital conversion, the threshold voltage for logic 1 and 0. Note that there are no wires connecting digital outputs to analog inputs in this circuit. Hence, we do not specify digital to analog (d2a) converter parameters in

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Figure 26. Modied amplier circuit.

Figure 27. Simulated output of the modied amplier circuit.

Figure 28. Creating inverter Verilog view.

the example. Click Netlist and run icon on the ADE window to start the simulation. The simulated waveforms are shown in Figure 37. Compare the difference between the spectre and spectreVerilog simulation outputs.

2.6 Taking advantage of conguration mechanism

Following the steps described in Section 2.2, create a schematic view for cell inv as shown in Figure 38. Transistor sizes used in the schematic view are: NMOS w=2.5, l=0.5; PMOS w=5, l=0.5. Vdc voltage is 5V. Now, we have three

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Figure 29. Inverter Verilog code.

Figure 30. Creating amp con guration view.

Figure 31. New conguration window.

Figure 32. Selecting template.

views (veriloga, verilog, and schematic) for cell inv that can be used in simulation. We can use conguration view to select any of these three views to be used in simulation. For example, in the conguration view window, select schematic of inv to be used in simulation. In the ADE window, set the simulation tool as spectre (Note that in order to use spectreVerilog tool the circuit has to contain at least one digital component). Repeat the simulation, the obtained waveform is shown in Figure 39. Compare it with the simulation results obtained with using Verilog-A model.

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Figure 33. Conguration view.

Figure 34. Selecting cell view to be used in simulation.

This conguration mechanism gives designers a signicant freedom to take hierarchy design approach. To design the above example circuit, we can rst use inverter Verilog model which is a very abstract model in simulation to save time. Then, we use Verilog-A model which may contain certain electrical characteristics of the inverter circuit in simulation. After this circuit is designed, we can perform simulation with transistor-level implementation, which is capable of revealing more detail problems in the design. Beyond that, we can design the layout and used extracted view in simulation to consider more parasitic effects. The above example may not be a good candidate to illustrate the advantages of using hierarchy design approach. For more complicated systems, benets of using hierarchy design approach will be more obvious.

3. Description of Example Library

Some example circuits contained in the library a2dlib are briey discussed in this section.

3.1 Recording DAC outputs during simulation

Example design dac write demonstrates how to write DAC outputs into a text le during simulation. The text le can be read by matlab code to calculate DAC performance parameters (e.g. INL, DNL, gain error, offset, etc). The schematic of

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Figure 35. Invoking interface conguration window.

Figure 36. Conguring A/D interface.

Figure 37. Simulated outputs.

dac write is shown in Figure 40. Component DAC is an ideal 8-bit DAC. Component write ana result is implemented using Verilog-A. It writes DAC outputs into le result.txt, which is located in directory /simulation/dac write/spectre/schematic/netlist. Component write ana result has a parameter num samples, which controls how many DAC outputs will be written into result.txt. Also, it has parameters to specify clock voltage levels. Note that the clock signal of write ana result is a delayed version of the counters clock.

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Figure 38. Schematic view of inverter.

Figure 39. Simulation result.

Figure 40. Dac write schematic.

3.2 Recording ADC outputs during simulation

Example design adc write demonstrates how to write ADC outputs into a text le during simulation. The text le can be read by matlab code to calculate ADC performance parameters (e.g. INL, DNL, SNL, etc). The schematic of adc write is

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shown in Figure 41. Component ADC is an ideal 8-bit ADC. Component write dig result is implemented using Verilog-A. It writes ADC outputs (digital words) into le result.txt, which is located in directory /simulation/adc write/spectre/schematic/netlist. Component digital write has a parameter number points, which controls how many ADC outputs will be written into result.txt. Also, it has parameters to specify digital input and clock voltage levels. Note that the clock signal of write dig result is a delayed version of the ADCs clock.

Figure 41. Adc write schematic.

3.3 Example converter circuits

dac 6bit tb: It is a testbench for a 6-bit current-scaling DAC. The 6-bit DAC is fully implemented at transistor level. adc tran 6bit tb: It is a testbench for a 6-bit pipelined ADC. The ADC is fully implemented at transistor level except the clock generation circuit. It also includes digital correction circuits. adc tran 6bit2 tb: It is a testbench for a 6-bit pipelined ADC. The ADC is fully implemented at transistor level except the clock generation circuit. It doesnt include digital correction circuits. adc sd 1st: It is a testbench for a 7-bit oversampling ADC. It consists of a rst-order Sigma-Delta modulator and a digital comb lter. The sigma-delta modulator is implemented by VerilogA model. The digital low-pass lter is implemented at RTL level using Verilog. dac sd 1st: It is a testbench for a 8-bit oversampling DAC. It consists of a rst-order Sigma-Delta modulator and an analog low-pass lter. The Sigma-Delta modulator is implemented at RTL level using Verilog. The low-pass lter is implemented using Spectre component SVCVS. dac efb 1st: It is a testbench for a 8-bit oversampling DAC. It consists of a rst-order error feedback modulator and an analog low-pass lter. The modulator is implemented at RTL level using Verilog. The low-pass lter is implemented using Spectre component SVCVS.

4. Reference on evaluating ADC performance

Please refer to Maxim application notes (http://www.maxim-ic.com/appnotes10.cfm/ac pk/13). You can also download these note at the class web site.

5 Some simulation tips

1. Sometimes simply clicking Netlist and Run icon in the ADE window will not re-create netlist after you modify the schematic. For example, after you change some thing in the schematic and run simulation, the simulation result doesnt reect the change you just made. In this scenario, from the ADE window pull down Simulation menu. Select Netlist and click Recreate to force the simulation tool to generate an updated netlist. 16

2. Simulation directory /simulation contains many previous simulation results. If you run out of storage space, you can delete les in the simulation directory. 3. Always exit icms tool before you logout. Otherwise, your design will be locked. When you login next time, you will not be able to edit it. In case that you have a locked le, you can unlock it as follows. Assume your project directory is project, your library name is ece531, the locked view is the schematic view of cell amp. Go to directory /project/ece531/amp/schematic. Remove le sch.cdb.cdslck.

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