Format no LP 01 Issue No.01 Issue Date: 05.05.

06 EASWARI ENGINEERING COLLEGE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG LESSON PLAN
Sub Code Sub Name Faculty : CS 2202 :Digital Principles and System Design :D. Vydeki Degree/Branch: B. E. /CSE Year/Sem/Sec :II/III/ A&B Total No. of Hrs given in Syllabus: Tutorial:15 Lecture: 45 Total: 60

Sl.No

Topic UNIT I BOOLEAN ALGEBRA AND LOGIC GATES Binary Number systems Number base conversions (Decimal, Binary, Octal, Hexadecimal) Binary Arithmetic Complement Numbers Signed Binary Numbers Binary codes BCD Code, Other Decimal codes Gray Code ASCII Code Error Correcting Code Boolean Algebra Basic definitions Two valued Boolean algebra Basic theorems and properties Boolean function Canonical &` standard forms conversions from one to other. Simplification of Boolean fn using K-Map ( up to 5 variable)

No.of Periods

Reference Books

Page Nos

1.

T1

1-9

2.

T1

9-14

3.

T1 15-24

4.

T1

33-40

5. 6.

1 1 2 1

T1 T1 R3 T1

40-53 64-97 101-110 (2nd edn) 53-60

7. Tabulation method 8. Logic gates Extension to multiple inputs Positive & Negative logic Universal gate Implementation of SOP & POS Boolean functions using logic gates.

9. Tutorial Minimization of Boolean function using Boolean Laws K- map Tabulation method UNIT II COMBINATIONAL LOGIC 1 Combinational circuits, Analysis procedure 0. with example 1 Design Procedure 1. Half/Full Adder/Subtractor 1 Circuits for arithmetic operations 2. Binary Adder subtractor 1 3. 1 4. Decimal Adder Binary multiplier Magnitude Comparator

1 1 1 1 1 2 1

T1 T1 T1 T1 T1 T1 T1

111-115 115-118 119-125 125-130 131-134 116-118 99-102

1 Code conversion 5. BCD-to-Binary/Excess-3 and Vice-versa 1 Intro to HDL 6. History of verilog Verilog concepts What is HDL Verilog intro, features Data types, value set 1 Module, Port, Gate delays 7. Operators. Simple programs Full adder, full subtractor, code converter. 1 Tutorial 8. Realisation of code converters using logic gates Design of 8 bit comparator using IC 7485. Serial adders. UNIT III DESIGN WITH MSI DEVICES 1 Decoders 9. Binary decoder BCD to seven segment display decoder Realization of Boolean function

T1

102-106

T1

134-138

using decoders. 2 Encoders 0. Decimal to BCD encoder Octal to binary encoder Priority encoder. 2 Multiplexer 1. 2 to 1, 4 to 1, 8 to 1 MUX Implementation of combinational logic using MUX 2 Demultiplexers 2. 1 to 2, 1 to 4, 1 to 8 DEMUX Implementation of combinational logic using DEMUX 2 Memory and programmable logic 3. RAM organization Read & write operation Static & dynamic RAM Bipolar & MOSFET RAM cell Comparison of SRAM & DRAM 2 ROM organization 4. PROM EPROM EEPROM Implementation of Boolean function using ROM 2 Programmable logic Devices 5. PLA PAL Implementation of Boolean function using PLA Comparison of PAL & PLA Comparison of ROM & PLA FPGA 2 HDL for combinational circuits 6. Gate-level Modeling Dataflow Modeling 2 Behavioral Modeling 7. Writing a Simple test bench 2 Tutorial 8. Implementation of Boolean function using MUX Decoders ROM, PLA UNIT IV-SYNCHRONOUS SEQUENTIAL LOGIC

T1

139-141

T1

141-143

T1

144-147

T1

255-267

T1

267-277

T1

277-287

T1

147-152

1 3

T1

152-160

2 Sequential circuits 9. Latches 3 0. Flip-Flops race around condition Edge Triggered D FF

1 1

T1 T1

167-172 172-179

3 Analysis procedure 1. Analysis of clocked sequential circuits State table, state diagram 3 Design procedures 2. 3 State reduction and State Assignment with 3. example 3 Shift registers 4. Modes of operation SISO, SIPO, PISO, PIPO Bi-directional shift register Universal shift register 3 Counters 5. Asynchronous / Ripple counter Synchronous counter Synchronous Vs Asynchronous counter Design of modulo n counter. 3 HDL for Combinational and Sequential 6. circuits (flip flops and latches) HDL for Counters and shift registers 3 Tutorial 7. Design of Asynchronous counters sequence, non sequence Design of Synchronous counters sequence, non sequence Shift register applications Delay line PRBS generator UNIT V ASYNCHRONOUS SEQUENTIAL LOGIC 3 Analysis Procedure of Asynchronous 8. sequential circuits Transition Table Flow table Race conditions 3 Design Procedure 9. Primitive flow table

T1

180-190

1 2 1

T1 T1 T1

203-211 198-203 217-227

T1

227-244

1 3

T1

190-198, 244-249

T1

342-352

T1

360-366

 Transition table and logic diagram 4 Reduction of State and Flow table 0. Implication table Merging the flow table 4 Race free state assignment with example 1. 4 Hazards 2. Hazards in combinational circuits Hazards in sequential circuits Essential Hazards 4 ASM Chart 3. 4 Tutorial 4. Problems Hazards in combinational circuits Hazards in Sequential circuits Design of Asynchronous sequential circuits. Total Periods.

T1

367-374

2 1

T1 T1

374-379 379-384

1 3

T1

299-310

60

TEXT BOOKS: TI M. Morris Mano, Digital Design, 3rd edition, Pearson Education, 2003 REFERENCES: R1 Charles H. Roth, Jr Fundamentals of Logic design, 4th edition, Jaico Publishing House, Latest edition. R2 Donald D.Givone, Digital Principles and Design Tata McGraw- Hill, 2003. R3 M. Morris Mano, Digital Logic & Computer Design, Prentice Hall of India Private Limited, 2001.

Prepared by (D.Vydeki)

Reviewed by (B.Sridhar)

Approved by HoD/ECE