A Low Voltage High Output Impedance Bulk Driven Regulated Cascode Current Mirror

Naresh Lakkamraju
Department of ECE National Institute of Technology Durgapur, India-713209 mail2rajuvarma@gmail.com
Abstract This work proposes the design of a new low voltage high output impedance CMOS current mirror that offers enhanced output voltage compliance using bulk-driven technique. The input/output characteristics of the proposed current mirror are discussed. Designed circuit is simulated in a proprietary 180 nm CMOS process, using Cadence Spectre and BSIM3v3 models. Simulated results with 0.8 V power supply and 50 A input current reveal that the proposed implementation requires a minimum input and output voltages of 0.4 V and 0.39 V respectively. It yields an increase of the output impedance compared with that of existing bulk driven current mirrors, thus offering a potential solution to mitigate the effect of ultra-deep submicron CMOS transistors used in sub 1-V current mirrors and current sources. Compared to high output impedance gate driven regulated cascode current mirror (GDRCCM), low voltage high output impedance body driven regulated cascode current mirror (BDRCCM) supports higher output voltage swing. Thus, the proposed design finds wide acceptability in low voltage and low power CMOS analog integrated circuits. Keywords CMOS, Low Voltage, Low Power, Body Driven Technique, Current Mirror.

Ashis Kumar Mal

Department of ECE National Institute of Technology Durgapur, India-713209 akmal@ece.nitdgp.ac.in by controlling weak positive bias between bulk and source of transistors, thereby reducing the total supply voltage of circuits. Furthermore, it is completely compatible with the standard CMOS process. Hence, the bulk-driven technique is attracting more and more attention as an important method for low-voltage low-power design [2]. Current mirrors (CM) are essential and widely used building blocks in analog integrated circuits. They are used to perform current amplification, biasing, active loading and level shifting. Hence, their efficient design improves the overall performance of the system. The most important parameters of current mirrors are accuracy, input/output compliances, input/output impedances, bandwidth, linearity, noise and sensitivity to changes in load impedance. Due to technology down scaling and its intrinsic benefits, the trend in VLSI design is to reduce voltage supply. Hence, low voltage and low power circuit designs are in great demand. So, it is necessary to develop some new structures of CM under low voltage low power conditions to meet design requirements of low voltage CMOS analog integrated circuits [3-5]. There have been some current mirror realizations using bulk driven technique [6-8]. But the critical parameters such as accuracy, input/output impedances, linearity and input/output compliances of those current mirrors are limited. To attain high output impedance and linearity a new low voltage high output impedance regulated cascode current mirror is proposed. The rest of the paper is organized as follows. Section II discusses basic structure and principle of operation of the proposed design. Section III explores analytical formulations to extract parameters such as input/output impedances of the proposed current mirror and comparison of those with some existing current mirrors. Section IV presents the simulation results of both the proposed current mirror and its gate driven equivalent performed in a proprietary 180 nm CMOS process. On the basis of results analyzed, section V concludes the significance of the proposed design in various low voltage and low power analog integrated circuits. II. LOW VOLTAGE HIGH OUTPUT IMPEDANCE BODY DRIVEN REGULATED CASCODE CURRENT MIRROR The conceptual schematic of the PMOS version of proposed current mirror is shown in Fig. 1. Circuit consisting of M1, M2, M3, and IB2 forms output side of the

I.

INTRODUCTION

Colossal advances in CMOS technology have made it possible to design chips with high integration density, better performance, and lower power consumption. To attain these objectives, the feature size of the CMOS devices has faced aggressive scaling down to very small features and dimensions. However, the power supply voltage has not been scaled down proportionally to the device dimensions in ultra deep sub-micron technology. The fundamental limitation of low voltage circuit design using the existing design methodology is that the power supply must be at least equal to the sum of the magnitude of the cascode p-type and n-type threshold voltages. Thus, several possible techniques, such as bulk-driven, sub-threshold, selfcascode, and floating-gate have been developed to construct high performance analog circuits under low power supply voltages. The bulk-driven technique, which uses bulk terminal as signal input, is a promising method as it achieves enhanced performance without having to modify the existing structure of MOSFET circuits [1]. This technique may remove the limitation of threshold voltage effectively
___________________________________ 978-1-4244 -8679-3/11/$26.00 2011 IEEE

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current mirror. The feedback amplifier in this case is

realized by the commonsource amplifier consisting of M3 For the weak positive bias between bulk and source of transistor, the input voltage drop of low voltage high output impedance BDRCCM is less than or equal to 0.4 V, which is much lower than that of high output impedance GDRCCM. III. CIRCUIT ANALYSIS Analytical formulations to extract parameters of the proposed current mirror are performed in the following subsections. A. Output impedance analysis The small signal equivalent circuit to derive the analytical expression for output impedance is shown in Fig. 2. In the following analysis, stand for the transconductance, the trnsconductance due to body effect, the output impedance of the transistor, output impedance of IB1, and output impedance of IB2 respectively. Usually, [7]. The is approximately equal to 3 transistors numbers are indicated as subscripts of these parameters. All the derivations are listed as follows.

Fig. 1. Conceptual schematic of proposed circuit

and its current source IB2. The basic idea is to use a feedback amplifier to keep the drain to source voltage across M2 as stable as possible irrespective of the output voltage. The addition of this amplifier ideally increases the output impedance by a factor equal to one plus the loop gain over that which would occur for low voltage low power body driven cascode current mirror (BDCCM) [7]. The circuit consisting of M4, M5, M6, IB1, and Iin operates almost identical to a diode connected transistor, but is used instead to guarantee that all transistor bias voltages are accurately matched to those of the output circuitrary. As a result, Iout will very accurately match Iin. The gate voltages of all PMOS transistors are connected to a fixed voltage VG (the lowest potential of circuits usually ground) to form the conduction channel beneath the gate. Input signal is directly imported to the bulk terminals of M2 and M5 whose source drain currents are built by controlling weak positive bias between bulk and source of transistors. Low voltage high output impedance PMOS BDRCCM may eliminate the limitation of threshold voltage on the signal pathway, thereby achieving a low input/output voltage drop. The minimum input and output voltage drops of low voltage high output impedance BDRCCM may be described as

(5)
In the Eq. (5) and

(6) (7) (8)

In the Eq. (8)

(9)
And let Substituting Eq. (9) and Eq. (10) in Eq. (8) gives

(10)

(1) (2)
The minimum input and output voltage drops of high output impedance GDRCCM may be described as

(11)

(3) (4) And here

Fig. 2. Small signal equivalent circuit for output impedance calculation

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The Eq. (11) further reduces to

(22) (12)

Substituting Eq. (6) and Eq. (12) in Eq. (5) produces

(13)

Output impedance ( From Eq. (13)

(14)

Fig. 3. Small signal equivalent circuit for input impedance calculation

Therefore

(15)
Therefore Eq. (15) shows the overall output impedance of the proposed current mirror which is higher than that of low voltage low power BDCCM [7] by a factor equal to one plus loop gain. B. Input impedance analysis The small signal equivalent circuit to derive the analytical expression for input impedance is shown in Fig. 3 and all the derivations are listed below.

(23)
(24) By substituting Eq. (23) and Eq. (24) in Eq. (16) gives an expression for . From that expression, the input impedance can be defined as

(25)
Therefore

(16)
In the Eq. (5)

(26)
The Eq. (26) shows the overall input impedance of the proposed current mirror. To get a clear understanding of the low voltage high output impedance BDRCCM characteristics, they are compared with low voltage low power BDCCM [7] and high output impedance GDRCCM [9]. They are listed in Table I. As shown in Table I, the low voltage high output impedance BDRCCM has high output impedance than the low voltage low power BDCCM and lower input/output voltage drops than the high output impedance GDRCCM. In are the loop gains of the the Table I the parameters high output impedance GDRCCM. Thus, it can be seen that low voltage high output impedance BDRCCM has a good performance no matter as current mirror or current source. IV. SIMULATION RESULTS AND DISCUSSIONS The above implemented proposed current mirror was simulated along with its gate driven equivalent in 180 nm CMOS process using Cadence Spectre and BSIM3v3

(17) (18) (19)

In Eq. (19) Let Substituting Eq. (20) in Eq. (19) gives

(20)

(21)
In Eq. (21)

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models. The power supply used to simulate the proposed

TABLE I. Current mirror Output impedance

current

mirror is 0.8 V

rather

standard

available

THE CHARACTERISTICS OF DIFFERENT PMOS CURRENT MIRRORS

Input impedance

Output voltage drop

Input voltage Drop

Low voltage High output impedance BDRCCM Low voltage Low power BDCCM High output impedance GDRCCM
BDRCCM

power supply 1.8 V, which was used to simulate the gate driven equivalent of the proposed current mirror. Fig. 4 shows the DC output characteristics of the low voltage high output impedance BDRCCM with output voltage (Vout) swept from 0 to 0.8 V and input current (Iin) stepped from 45 A to 55 A in 5 steps. Fig. 5 shows the DC output characteristics of the high output impedance GDRCCM with output voltage (Vout) swept from 0 to 1.8 V and input current (Iin) stepped from 45 A to 55 A in 5 steps. From Fig .4 and Fig. 5, it is observed that the proposed current mirror has a bit lower or approximately equal output impedance than its gate driven equivalent. Fig. 6 and Fig. 7 shows the DC input characteristics of low voltage high output impedance BDRCCM and high output impedance GDRCCM respectively with Iin swept from 20 A to 55 A. Furthermore, it is observed that the proposed current mirror has much lower input voltage drop than its gate driven equivalent to get same amount of output current.

Fig. 8 and Fig. 9 shows the DC current transfer characteristics of low voltage high output impedance BDRCCM and high output impedance GDRCCM respectively with Iin swept from 35 A to 55 A. From these figures, a conclusion can be deduced that the proposed current mirror has the similar current transfer characteristics as high output impedance GDRCCM for higher order currents.

Fig. 5. DC output characteristics of high output impedance GDRCCM

Fig. 4. DC output characteristics of low voltage high output impedance

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Fig. 6. DC input characteristics of low voltage high output impedance BDRCCM

V.

CONCLUSION

With the aim of attaining a high output impedance and enhanced input/output voltage compliances under bulk driven technique, a low voltage high output impedance BDRCCM is designed and simulated using a 180 nm CMOS process. The proposed design exhibits enhanced output impedance than low voltage low power BDCCM and an input voltage drop of 0.4 V and an output voltage drop of 0.39 V for 50 A input/output current. Aforesaid simulation results quite well justify that these input/output voltage drops are much lower than high output impedance GDRCCM. Therefore, the proposed low voltage high output impedance BDRCCM would be suitable for various wide range of low voltage and low power analog applications. ACKNOWLEDGMENT

Fig. 7. DC input characteristics of high output impedance GDRCCM

The authors would like to express their gratitude to Dr. Debashis Datta, MCIT, Govt. of India, for extending the SMDP project at NIT Durgapur. The authors delightfully acknowledge Prof. S. K. Dutta, ex-chair of SMDP-II, NIT Durgapur, for helpful discussions and encouragement. They also express their cordial thanks to Mr. Rishi Todani, Mr. Kanchan B. Maji and Mr. Om Prakash Hari for all kinds of technical and moral support. REFERENCES
[1] B. J. Blalock, and P.E. Allen. Low-Voltage, Bulk-Driven MOSFETCurrent Mirror for CMOS Technology, IEEE ISCAS I995, vol. 3, pp.1972-1975, 1995. Wang Shaoxi. Nanometer Bulk-Driven Applications MOSFET Model Analysis 2010 International Conference On Computer Design And Appliations (ICCDA 2010). vol.4, pp. V4-197 - V4-200. Jonathan Rosenfeld, Mucahit Kozak, Eby G.Friedman, "A BulkdrivenCMOS OTA with 68dB DC gain," 11th IEEE International Conference on Electronics, Krakow, Poland, Circuits and Systems, IICECS.2004, pp.5-8, doi 10. 11.09. Khateb. F, Biolek. D, Khatib. N, and Vavra. J Utilizing the Bulkdriven technique in analog circuit design IEEE DDECS 2010, pp. 16 19, doi 14-16 April 2010. F. Khateb, Bulk-driven Op-Amps for low power applications, Elektrotechnika a informatika 2003, Ne tiny Castle, 2003, pp.51 -55. Z. Zhu, J. MO, Y. Yang, A low voltage Bulk-driving PMOS cascode current mirror, in Solid-State and Integrated-Circuit Technology, 2008, pp. 2008-2011. Li Yani, Yang Yintang, and Zhu Zhangming A Novel Low-voltage Low-power Bulk-driven Cascade Current Mirror 3rd International Conference on Advanced Computer Theory and Engineering (ICACTE)-2010, vol. 3, pp. V3-78 - V3-83. Aggarwal. B, Gupta. M Low-Voltage Cascode Current Mirror Based on Bulk-Driven MOSFET and FGMOS Techniques International Conference on Advances in Recent Technologies in Communication and Computing, 2009 (ARTCom '09). pp. 473 477. David A. Johns, Ken Martin, Analog Integrated Circuit Design, John wieley & sons, Inc.

[2]

[3]

Fig. 8. DC current transfer characteristics of low voltage high output impedance BDRCCM

[4]

[5]

[6]

[7]

[8]

[9]

Fig. 8. DC current transfer characteristics of high output impedance GDRCCM

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