A comprehensive simulation macromodel for
‘current feedback’ operational amplifiers
D.F. Bowers
M. Alexander
J. Buxton
Indexing terms: Simulation, Ampl@ers
Abstract: A SPICE compatible macromodel has
been devised for the simulation of ‘current feed-
back’ type operational amplifiers. Since the major
advantage of this type of amplifier is high speed,
the emphasis is on the accurate prediction of AC
characteristics. A practical example is given,
together with a comparison of measured and
simulated performance.
1 Introduction
The classic operational amplifier behaves as a voltage
controlled voltage source designed to allow feedback
control of closed-loop gain. Such a component is ideally
characterised by high impedance differential inputs,
nearly infinite voltage gain and a low impedance output.
Unfortunately, this simplified model rapidly loses validity
when attempts are made to obtain high speed per-
formance. The ‘current feedback‘ op amp [Z] is an ampli-
fier configuration intended to remove some of the AC
shortcomings of a conventional op amp. Before delving
into the main subject of this paper, a little background
information is in order.
2 Conventional high speed op amps
A conventional op amp with a single (or very dominant)
pole compensation scheme has a closed loop bandwidth
inversely proportional to closed loop gain [l]. Non-
dominant poles can produce significant deviation from
this constant gain-bandwidth product condition, but
nevertheless bandwidth degradation will still occur as the
overall gain is increased.
The (small signal) dominant pole behaviour can be
modelled as a constant transconductance input stage
feeding a fixed compensation capacitor, the gain band-
width product being given by
gbw = gJ(2 x n x C,)
(1)
The feedback potential divider acts as an attenuator to
the input stage, effectively reducing its transconductance
value, and this maintains the constant gain bandwidth
product at all finite closed-loop gains.
Paper 71686 (E10, E16). received 23rd Aueust 1989
The authors are with Precision Monolithics Incorporated, Santa Clara
CA 9SOS0, USA
IEE PROCEEDINGS, Vol. 137, Pt. G, No. 2, APRIL 1990
3 ‘Current feedback‘ op amps
The current feedback approach is shown conceptually in
Fig. 1.
Fig. 1 Conceptual layout of current feedback op amp
The input stage is now a unity-gain buffer forcing the
inverting input to follow the noninverting input. Thus,
unlike a conventional op amp, the latter input is at an
inherently low (ideally zero) impedance.
Feedback is thus always treated as a current and
because of the low impedance inverting terminal output,
R , is always present, even at unity gain. Voltage imbal-
ances at the inputs thus cause current to flow into or out
of the inverting input buffer. These currents are sensed
internally and transformed into an output voltage. The
transfer function of this transimpedance amplifier is A(s);
the units are ohms.
It can be shown that if A(s) is high enough (like the
open loop gain of a conventional op amp) no current
flows in the inverting input at balance. The overall closed
loop transfer function now becomes
V,,, = FA+) x (1 + R J R J (2)
which is the same as for a conventional op amp.
However, if the dominant pole is created by feeding the
current imbalances into the compensation capacitor, the
time constant will be set by the product of this capacitor
(C,) and the feedback resistor R , . The closed loop band-
width is now given by
bw = 1/(2 x n x C, x R2) (3)
and is independent of closed loop gain.
4 Large signal effects
The most often quoted large signal limitation of a con-
ventional op amp is the slew rate: the maximum possible
rate of voltage change at the output. From a modelling
137
point of view it is convenient (and accurate) to think of
this limitation as arising from a reduction in input stage
transconductance, ultimately close to zero, as the differ-
ential input signal increases. Under this condition the
charging current to the compensation capacitor becomes
independent of the input differential and the output
ramps at a relatively constant rate. This can impose a
very severe limitation on large signal bandwidth. In most
conventional op amps the maximum charge current is
well defined, i.e. the tail current of the input stage. The
situation for current feedback types is totally different.
Take the implementation of Fig. 2 as an example [3].
Fig. 2 Single gain stage implementationof currentfeedback op amp
While this is not the only possible architecture for
such an amplifier, it is almost certainly the fastest, being a
single gain stage implementation. Also, virtually all
present designs derive from this configuration, so at the
very least it can be considered representative.
The input buffer is an open-loop type consisting of Q1
to Q4 and associated current sources. Collector current
imbalances in Q3 and Q4 are ‘mirrored by Qs to Qs and
subtracted at the (high impedance) gain node to obtain
the required transimpedance. Q9 to Q l z serve as the
output buffer for the gain node.
Consider the case where a large input step has tempo-
rarily broken the feedback loop. A conventional op amp
under these circumstances has a large differential input
voltage; a phenomenon prevented in the current feedback
version by the input buffer. Instead, a differential voltage
between the inverting input and output forces a transient
current in R, . This current in turn flows through either
Q3 or Q4, via the respective current mirror into the com-
pensation capacitor, C, . The transient current, of course,
is equal to the differential input/output voltage divided
by the value of R , , which is also the value of the small
signal transconductance. There is thus no theoretical slew
rate limiting. Practical slew limiting does arise from a
multiplicity of second order effects, including finite slew
rate in the output buffer, beta rolloff in the current
mirrors and transistor transit time limitations. Despite
these effects, the large signal bandwidth of a current feed-
back op amp often approaches that of its small signal
value.
5 Conventional op amp models
Macromodels for a large number of conventional op
amps already exist in the device libraries of many of the
commercial simulators currently available. Most of them
are based on the original work done by Boyle et al. [4].
138
This macromodel was developed during the mid 1970s to
ease the CPU time crunch on the already overloaded
mainframe computers of the day. The approach taken by
Boyle was to eliminate all but two transistors from his
macromodel. These two remaining devices formed the
differential input stage of the op amp and all subsequent
stages were implemented with linear controlled sources,
passive components and diodes. The transistors in the
input stage were retained because they made simulation
of real world effects like bias currents and variation of
output dV/dt with differential input voltage easier.
While the Boyle model provides a convenient method
for simulating op amps in practical situations, there are
several deficiencies in its structure that can lead to
unrealistic results. First, only two poles (and no zeros) are
provided for frequency shaping. This is barely adequate
for lower speed op amps, and completely inadequate for
today’s higher speed devices. Secondly, all internal volt-
ages are referenced to ground, despite the fact that few op
amps have a ground terminal. This causes errors when
running from asymmetrical supplies such as those found
in video applications. Thirdly, all of the output current
flows from this mythical ground pin and not from the
supplies, as it would in any real amplifier. Since high
speed op amps are frequently required to drive low
impedance loads, this makes simulation of power supply
management impossible.
One attempt to improve conventional op amp macro-
modelling has already been made by the authors of this
paper [SI. This new macromodel retains the transistor
implementation for the input stage, but uses a ‘telescopic’
centre section to provide as many poles and zeros as
deemed necessary for a given op amp. Also, a realistic
output stage was devised that used no elements other
than those available in standard Berkeley SPICE. This is
important, because it makes the macromodel compatible
with virtually every available simulator (most of which
are SPICE derivatives anyway).
6 Principles of the ’current feedback’ model
The ‘current feedback’ model described in this paper uses
the same ‘telescopic’ frequency shaping technique as used
for the conventional op amp outlined in Reference [SI.
The output stage model is also retained since there is no
obvious reason to change it. However, the input stage, as
might be expected, requires a totally different treatment.
At this point it should be noted that this is not the first
attempt at modelling a ‘current feedback‘ amplifier. One
previous example is quoted in Reference [SI. This refer-
ence describes two topologies for modelling several com-
mercially available amplifiers. Although the second
topology used a hybrid n transistor model to emulate the
action of the input buffer, both topologies were pure
small signal AC models. No attempt was made to model
DC errors, large signal artifacts or output loading effects.
The model described here is based on the assumption
that the configuration of Fig. 2 is representative of pre-
sently available current feedback amplifiers. This assump-
tion will be given further justification in due course.
It is important that the input buffer be modelled fairly
accurately, since it has a marked effect on AC response.
Obviously, any AC limitations in the buffer will translate
to an overall limitation in the amplifier, but also finite
output impedance enters into the closed loop bandwidth
calculation. If the buffer output impedance is expressed
by Rb, , eqn. 3 can be written
+
bw = 1/{2 X n x c, X [I?, (1 4- R J R l ) ] X (4)
IEE PROCEEDINGS, Vol. 137, P f . G, No. 2, A P R I L I990
Since R , is a relatively high value, at low gains, when R 1
is also high, the effect of Rhf is negligible. At high gains,
when the value of R, becomes comparable to R , , / , the
effective bandwidth becomes significantly lower than that
predicted by eqn. 3. At higher gains, when the value of R ,
falls below R h f , the amplifier takes on a constant gain-
bandwidth product, just like a conventional op amp. In
practice, the buffer output impedance will be complex,
which further complicates this issue.
6.I The input (buffer) stage model
We chose to retain the idea of using existing SPICE
bipolar transistor models in the input stage for most of
the same reasons as did Boyle. All available current feed-
back amplifiers to date have used bipolar transistors in
the input stage and there did not seem much point in
redeveloping the Gummel-Poon model. Referring to Fig.
2, the core of the input stage consists of the four tran-
sistors, Q, to Q4. These transistors retain their identity
in the input stage model (Fig. 3). The effective output of
input stage
Fig. 3 Input and gain stages of the model
the input stage is at nodes 5 and 7, and these are coupled
into the gain stage via voltage controlled current sources,
g, and g, . Finite output impedance effects of the buffer
are modelled by choosing suitable operating currents for
Q3 and Q 4 . The actual values used in the circuit to be
modelled provide a good starting point for optimisation.
Theoretically, these currents would be set according to
I , = I , = kT/(2q x Rbuf) (5)
where Rbuf is the measured output impedance of the
buffer. Common mode rejection can also be included here
by suitable setting of the transistor Early voltages. The
change in base-emitter voltage of a bipolar transistor due
to varying collector-base voltage is given by
Ab, = k T / q In [(2 x AKb + % / ) / ( A b 4-E/)] (6)
where V./ is the Early voltage. If all the transistors have
the same Early voltage, the change in offset of the buffer
is actually double this because the input voltage controls
the V , of both Q, and Q3 (and their counterparts Q,
and Q4) which are effectively in series. If is large com-
IEE PROCEEDINGS, Vol. 137, Pt. G, No. 2, A P R I L 1990
pared to cn,then the effective CMRR will be
CMRR(dB) = 20 log [(2/V,,) x k T / q ] (7)
If is not large compared to Frnthen nonlinearities will
occur in the common mode performance of both the
model and the actual amplifier.
Our experience indicates that a pole needs to be added
to the input buffer to obtain a close frequency response
fit over a wide gain range. This pole is added to the input
buffer by R,,, R,,, C,, and C,,. The use of separate
networks for the upper and lower half of the model
ensures that AC supply rejection is not degraded,
although this particular model implementation does not
attempt to include PSRR effects. Stray capacitance at the
inverting input (buffer output) also has a marked effect
on the overall response, particularly high frequency
peaking, and this is accounted for by C,, and C., , again
split equally between the supplies for PSRR reasons.
These capacitances model package pin capacitance as
well as strays internal to the amplifier. Another limi-
gain stage
tation, previously unmodelled, is the input stage slew
rate. This slew rate is independent of the output slew rate
in practical amplifiers. Often it is faster, and is of little
practical consequence. Sometimes though, it is much
slower and becomes the dominant factor in determining
the overall transient response of the amplifier at low non-
inverting gains. This is modelled without additional ele-
ments in the macromodel, since the maximum currents
available to charge C,, and C p 2 are the values of I, and
I,. We chose to fix I, and 1, to determine the previously
mentioned operating currents in Q3 and Q4 without the
need for transistor scaling (agreed this is arbitrary). The
two variables R , and C , , then, relate to slew rate and
input stage pole frequency in a consistent manner. It may
be observed that this slew rate limitation does not occur
for C,, during negative transients or C,, during positive
ones, due to the follower action of Q, and 4,. It is an
elegant byproduct of the model that the output slew rate
is always limited by the lower of the input slew rates, and
no correction is needed for this.
The polynomial current source G,, is used to model
139
the residual input current at the inverting input. This
occurs as a result of circuit imbalances and consists of a
fixed term and an input dependent term (the latter is
referred to on most data sheets as inverting input
common mode rejection). The reference point for Gbl is a
supply midpoint set by R l s and R,, . Finally, input offset
voltage and noninverting input bias current are defined
by the voltage source V,, and the current source
respectively.
Although the Fig. 2 topology is quite representative of
existing amplifiers, variations do occur. One variation is
the use of complementary diode connected transistors in
the emitters of all four core transistors. This balances out
offsets caused by the fact that pnp transistors have a dif-
ferent V,, (on) to that of the npns. The major effect this
has on the model is to cause the buffer output impedance
to be low by a factor of two, compared with the actual
device being simulated. This is easily corrected by halving
the operating currents. Sometimes the transistors are
cascoded to improve CMRR, and this can be simulated
by giving the transistors in the model a high Early
voltage. The transistors Q, and Q2 are also sometimes
replaced by diodes; this could also be done in the model,
of course, but again a high Early voltage would give the
same result.
6.2 Gain stage
The ‘gain stage’ actually performs six important functions
within the model
(i) It defines the open loop transimpedance of the
amplifier. In conjunction with the input buffer output
impedance this also defines the maximum voltage gain
obtainable.
(ii) It adds the dominant pole to the AC characteristic.
(iii) It provides limits to the output excursions. (All
subsequent stages have unity gain.)
(iv) It level shifts the signal from two voltages referred
to the supplies to a single voltage referred to the mid-
point.
(v) It provides slew rate limiting.
(vi) It defines the overall supply current.
Referring to Fig. 3, the stage is composed of two voltage
controlled current sources, two resistors, two capacitors
and a voltage limiting network. The latter comprises a
w U U U
polelzero zerolpole common-mode
stoge stage gain stage
’p < f z f z < fp w i t h zero
Fig. 4 Frequency response shaping stage
140
pair of diodes, each connected to its own respective
voltage source. This prevents the stage, plus other inter-
nal nodes of the model, swinging beyond the power
supply rails during an input overdrive condition. The
voltage limiting has to be done here, otherwise ridicu-
lously a large voltage could be generated internally to the
model, which in turn can cause overflow errors or con-
vergence problems (the SPICE 2G bipolar transistor
equations exhibit a singularity if the collector-base
voltage ever becomes forward biased by an amount equal
to Kf. (This has been fixed in some simulators.) Resistors
R , and R,, in conjunction with G, and G , and R I
and R, in the input stage, define the transimpedance. If
R, = R , , R , = R , and G, and G , have equal coefficients
(there is no good reason to make them different) then the
transimpedance is given by
Rt,.,, = R3 x Ri X Gc2
where G,, is the second coefficient of G, and G, .
The dominant pole is set by capacitors C , and C , in
conjunction with R , and R,. Slew rate limiting is
obtained by limiting the available current to C, and C, .
This is done in the input stage by clamping the voltages
across R, and R, via V,, V, and their associated diodes.
Setting V, and V, to different values enables an asym-
metric slew rate to be modelled. Finally, there is a DC
component added to G, and G 2 to make up the bulk of
the overall supply current.
6.3 Frequency response shaping
Early on in the development of the basic macromodel
structure, it was decided that easy construction of op
amp models with large numbers of poles and zeros must
be facilitated. Investigation of op amp frequency response
had revealed that in most cases more than two poles
were needed to accurately simulate the gain and phase
variation of real devices at high frequencies. Yet the
model still had to be of a modular form so that many
different types of amplifier, with varying numbers of poles
and zeros, could easily be converted to a SPICE com-
patiable subcircuit without having to start from scratch
each time. The resulting structure thus uses a few basic
building blocks that are common to all individual ampli-
fier models, and are shown in Fig. 4.
pole stage
I E E PROCEEDINGS, Vol. 137, Pt. G , No. 2, A P R I L 1990
 The unity gain of all the frequency shaping blocks for
direct current results from the fact that the g, of each of
the two voltage controlled current sources is equal to the
reciprocal of each of the resistors connected from each
node to the supplies. A very useful feature of this topol-
ogy is the ability to ‘comment out’ separate poles or pole-
zero pairs during model generation for a specific
amplifier. This allows one to see their effect, individually,
on the overall amplifier frequency response and thus
makes pole-zero ‘tweaking’ rather easy. The procedure, of
course, does not alter the DC open-loop transimpedance
since all the frequency shaping blocks have unity gain for
direct current.
6.4 Output stage
The output stage of Fig. 5 deserves some explanation
because its operation is not entirely obvious. The internal
op amp output signal, after receiving all the appropriate
frequency shaping, appears at the last node prior to pro-
cessing by the output stage as a voltage referenced to V,.
The two voltage controlled current sources in the output
block drive two equal resistors connected to the supply
rails, as with the other blocks. Here, however, the g, of
the two controlled sources is arranged so that they act as
active current generators. Consequently, each g, source
generates just enough current to support the desired
voltage drop across its paralleled resistor. When there is
no load on the output of the model, no current is actually
drawn from either power supply rail by this configu-
ration. It thus behaves somewhat like an ideal unity gain
class-B type output stage with no crossover distortion.
Because the two resistors are each equal to twice the
open-loop output resistance, the output stage appears to
act as a voltage source referenced to V,, with the correct
DC output resistance. Simulating the right output resist-
ance means that the DC open loop transimpedance will
be properly reduced as the amplifier is loaded.
A subtle problem exists with this simple push-pull
output stage, however. Regardless of whether it is sinking
or sourcing current, the load current is always equally
split between both rails, not exactly what a real output
stage would do. What this means is that with a sourced
load current, for example, the net positive supply current
increases by only half that flowing in the load. The nega-
tive supply current decreases by the same amount. It is
previous stoge)
--
VE E
correction current output stage
sources
Fig. 5 Oufput stage wifh current correction
IEE PROCEEDINGS, Vol. 137, Pt. G , No. 2, A P R I L 1990
easy to compensate for this anomaly, though, by forcing
a current from the positive rail to this negative rail
exactly equal to half the load current. This correction
current must always flow in the same direction, even if
the output current reverses polarity.
Therefore, the effect of the two correction sources,
shown in Fig. 5, is to force a unipolar compensating
current between the power supply rails that is equal to
half the output current. In SPICE, because there is no
easy way to implement an absolute-value voltage con-
trolled current source, there have to be two linear correc-
tion sources, one for each half cycle of output current.
The diodes in series with each source perform halfwave
rectification, and the zeners ensure that there is always a
conductive path for each source when its current reverses
direction. The net result of all these additional elements is
an output stage whose DC behaviour very closely mimics
that of the real thing. An output inductor has been added
from the intermediate output node to the actual macro-
model output node to account for the typical rise in
emitter-follower output stage impedance with frequency.
The value of this inductor is determined on a trial and
error basis using capacitive loads on the model until the
amount of overshoot is very close to that observed with
the real op amp and the same load.
Short circuit current limiting is also a necessary
feature of any good op amp macromodel. It is accom-
plished here by clamping the output voltage from the
previous frequency shaping stage to the intermediate
output node using diodes and voltage sources. Remember
that the signal from the previous stage is always equal to
the ideal output voltage with no load, and that the
output stage behaves as a voltage source with a finite
output resistance. The action of the diodes and voltage
sources is, then, equivalent to clamping the voltage drop
across the effective output resistance. By appropriate
choice of each voltage source, the required output current
limiting is realised.
7 A practical example
To illustrate the practical use of this model, a netlist was
generated to represent (one half of) the OP-260 dual
current feedback op amp. The effective amplifier sche-
matic is shown in Fig. 6 [3], though it should be noted
that all model generation was performed from measured
parameters and not from knowledge of the circuit details.
The complete practical model is shown in Fig. 7a. The
associated netlist (in the form of a subcircuit) is shown in
Fig. 7b. The input stage bias sources (I, and I,) are set to
150 pA rather than the 300 PA used in the actual ampli-
fier to compensate for the balancing diodes mentioned
previously. C1 and C , set the input stage slew rate at
lo00 V / p s with a pole at 84 MHz. The effective trans-
impedance is set to 10 M a with a dominant pole at
26.5 kHz.
The frequency shaping section is a little unusual in
that it consists of three identical 80MHz poles but no
zeros. This is, however, not expected to be a general char-
acteristic for amplifiers of this topology.
Comparison of the results obtained with this netlist to
actual device measurements is quite good. The DC
results are, as might be expected, accurate to well within
the normal production parameter spreads, which is all
that can be reasonably required. Small signal AC results
are shown in Fig. 8.
All results use. a 2.5 kR feedback-resistor, which is the
suggested data sheet value. Fig. 8a shows a simulated
141
unity gain inverter amplitude response for five different
load conditions. The measured response of Fig. 86 is
quite close, except at frequencies well beyond the band of
interest, where third order effects start to shape the char-
3001
r- P
'27
h.- ix'l
Fig. 6
;" 300pA
Effective circuit used in modelfor (huyof)OP-260 dual current feedback op amp
=E!&
,-=E?!&,
fl,. ' fl,,
acteristic. Figs. 8c and d show a comparison of the phase
response under the same conditions. Figs. 8e to h show a
similar set of curves for a noninverting gain of ten. Again,
the fit is quite close and almost certainly within expected
production tolerances.
Obtaining an extremely close transient fit for any
model is virtually impossible because subtle effects like
settling time depend on so many variables. Also, any
attempt to synthesise such effects would slow down the
model to an unacceptable degree. The small signal tran-
sient response of Fig. 9 was obtained at a noninverting
gain of five. A 20 p F load capacitor was added to deliber-
ately induce some ringing. The fit to the measured result
is not exact, but it adequately indicates the magnitude,
frequency and duration of the observed ringing. Large
signal response is probably the most difficult to model,
mostly due to amplitude dependent parameters internal
to the amplifier. These effects also tend to be asymmetric,
which means (with the exception of slew rate) they cannot
as yet be modelled. Despite this, the simulated step
response (under the same conditions as Fig. 9) is similar
enough to the measured response of Fig. 9d to provide
acceptably accurate results in a practical system environ-
ment.
142
It is interesting to note that these results are in general
more accurate than those that were obtained from the
full transistor level model used in the design of the
OP-260.
1k l l
U
in
c2
0.6pF
12011
0 60
2x
v-
8 CPU efficiency
Since the whole object of a macromodel is to provide a
means of simulating many devices with a minimum of
CPU time, the question of model efficiency naturally
arises. Despite containing many more elements than the
conventional Boyle op amp model, similar types of
analysis reveal that the time overhead is only about a
factor of two on DC and small signal AC analysis. The
Boyle model runs about four times as fast on transient
analysis, but some of this is due to the fact that our new
macromodel generates considerably more detail in the
analysis.
9 Conclusion
A macromodel suitable for computer simulation of a
wide variety of 'current feedback' operational amplifiers
has been formulated. The macromodel has the capability
of generating a much more accurate AC response com-
pared to previous modelling techniques, while only incur-
ring a modest run time penalty.
I E E PROCEEDINGS, Vol. 137, Pt. G, No. 2, A P R I L I990
 99

Fig. 7 OP-260 model

a Compkte circuit IBI 99 1 2E-7
b Netlist RI1 17 99 IE6
VOS 3 1 IE-3 RI2 17 50 LE6
CSI 99 2 0.8E-12 C9 17 99 2E-15
CS2 50 2 0.8E-12 CIO 17 50 2E-I5

1
b
OP-260 SPICE Macro-model G7 99 I7 16 18 IE-6
GAIN STAGE AND DOMINANT POLE G8 I7 50 I8 16 IE-6
Node assignments RS 12 99 10E6 I OUTPUT STAGE
ir;iwi
non-inverting input R6 12 50 10E6
C3 12 99 0.6P RI3 18 99 3.33383
C4 I2 50 0.6P RI4 18 50 3.333E3
positive supply GI 99 12 POLY(1) 99 8 4E-3 0.258-3 RI5 23 99 I50
negative supply G2 12 50 POLY(1) IO 50 4E-3 0.258-3 RI6 23 50 I50
V3 99 I3 2.2 LI 23 24 1.5E-8
SUBCKTOP-260 I 2 249950 V4 14 SO 22 CFI 24 2 l.8P
D3 12 13 DX G9 21 50 17 23 6.666678-3
INPUTSTAGE D4 I4 12 DX GI0 22 50 23 17 6.666678-3
RI 99 8 4K GI1 23 99 99 17 6.66667E-3
POLE AT 80 MHZ GI2 50 23 17 50 6.66667E-3
R2 IO 50 4K
VI 99 9 11
~.
V5 19 23 1.55
R7 15 99 IEh V6 23 20 1.55
DI
~~~

9 8 DX R8 15 50 IE6
v2 I 1 50 1.1 DS 17 I9 DX
CS I S 99 2.58-15 D6 20 17 DX
D2 IO I I DX
~ ~~
C6 15 50 2.5E-I5
II 99 5 l50U D7 99 21 DX
G3 99 I5 12 I8 IE-6 D8 99 22 DX
I2 4 50 IMU G4 15 50 18 I2 1E-6 D9 50 21 DY
QI 50 3 5 QP
42 99 3 4 QN D10 50 22 DY
I POLE AT 80 MHZ
43 8 6 2 QN
44 IO 7 2 QP * MODELS USED
R9 16 99 1E6
R3 5 6 14.3K RIO 16 50 LE6
R4 4 7 14.3K C7 16 99 2.28-15
CI 99 6 0.133P C8 16 50 2.2E-I5
C2 50 7 0.133P G5 99 16 15 18 IE-6 MODEL QN NPN(BF = IE9 IS = LE-15 VAF = 150)
G6 16 50 I8 15 1E-6 MODEL QP PNWBF = IE9 IS = IE-15 VAF = 150)
* INPUT ERROR SOURCES MODEL DX D(IS = LE-15)
f POLE AT 80 MHZ MODEL DY D(IS = IE-I5 BV = S O )
CBI 99 2 POLY(1) I 18 3E-6 4E-8
ENDS OP-260
IEE PROCEEDINGS, Vol. 137, Pt. G , No. 2, A P R I L 1990
143
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-250 - - 250
-300 L -300
3 10 30 100 1 3 10 30 100
C frequency, M H z 9 frequency, M H z

I r
0-
451
-65 -
;-90-
P
-135 -

F -180 -
f

$ -225 -
0
& -270 -
\

-360
I
1 10 100
L
1
I I I I L 1 1 1 1
10 100
d frequency, M H z h frequency, M H z
Fig. 8 Small signal AC result for OP-260 model for various loads R ,
(I Simulated }
unity,gain inverter
b Measured amphlude respons
1'.
e Sirnulaled gam ten noninverting
:
f Measured amplifier amplitude response
c Simulated un~tygain inverter g Simulated gain ten noninverting
]
d Measured phase re&,
+
}
h Measured amplifier phase response
R, = 2.5 kn;V , = 15 V; 7' = 25°C; measured gain responses normalised to 0 dB

144 IEE PROCEEDINGS, Vol 137, P f G, N o 2, A P R I L 1990

- ~ ~
 -800
Y
0 100 200 300 400 500
time, ns
Fig. 9 Small signal transient response Jor goinfive noninverting ampliJier

Future refinements will be performed as more experi- 10 References

ence is gained with practical amplifiers. Obvious
enhancements include an automatic model generator and
the possibility of codng the model in a fully behavioural
language (like MAST from Analogy Inc.) for increased
efficiency. The present model does not attempt to model
noise or temperature effects (though device parameters
1 S O L O M O N , J.E.: T h e monolithic o p amp: A tutorial study’, IEEE
J.2 1974, sc-99 PP. 316332
2 ‘A new approach to OP a m p design’. Application Note 300-1, Corn-
linear Corporation, March 1985
3 BOWERS, D.F.: ‘A precision dual “current feedback operational
amplifier’. Proceedings of the BCTM, Sept. 1988, pp. 6G70
4 BOYLE, G.R.: ‘Macromodeling of integrated circuit operational

~ ~ o ~ a n g ~ ~ ~ ~ l ~ : , t ~ ~ ~ ~ a n$ ~! ? ?oi ~f : ?%
$ l ~ ~
properly. It is hoped to report on such developments in
5
~ ~
c:f:odel
22nd June 1989,pp. 115-118
improves spice’, Electron. Des.,

6 ‘Simulation macro-models for comlinear’s current feedback a m d i -

the near future. fiers’. Application Note OA-09, Comlinear Corporation, Jan. 1989

IEE PROCEEDINGS, Vol 137, Pt. G, N o 2, A P R I L 1990 145

~ ~- ~~ ~~ ~ ~~-