DDR3 Registered DIMM Spec Sheet

Features
DDR3 functionality and operations supported as defined in the component data sheet 240-pin, Registered Dual In-line Memory Module (RDIMM) Fast data transfer rates: PC3-8500, PC3-10600, PC3-12800 1GB(128 Meg x 72), 2GB (256 Meg x 72), 4GB (512Meg x 72), 8GB (1024Meg x 72) V DD = V DDQ = 1.5V 0.075V V DDSPD = 3.0V to 3.6V Supports ECC error detection and correction Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals Double rank On-board I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM 8 internal device banks Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) Selectable BC4 or BL8 on-the-fly (OTF) Gold edge contacts Pb-free Fly-by topology Terminated control, command, and address bus

Rev 1.0 Nov. 2010

DDR3 Registered DIMM Spec Sheet

Module Specification
Part Number SP001GBRTE106S01 SP001GBRTE133S01 SP002GBRTE106S01 SP002GBRTE133S01 SP004GBRTE133S01 SP004GBRTE133U01 SP004GBRTE133V01 SP008GBRTE133M0A Module Density & Configuration 1GB (128Mx72) 128Mx8 1Rank 2GB (256Mx64) 128Mx8 2Ranks 4GB (512Mx64) 128Mx8 4Ranks 4GB (512Mx64) 256Mx4 2Ranks 4GB (512Mx64) 256Mx8 2Ranks 8GB (512Mx64) 512Mx4 2Ranks Bandwidth PC3-8500 PC3-10600 PC3-8500 PC3-10600 PC3-10600 PC3-10600 PC3-10600 PC3-10600 Data Rate DDR3-1066 DDR3-1333 DDR3-1066 DDR3-1333 DDR3-1333 DDR3-1333 DDR3-1333 DDR3-1333 Timing (tCL-tRCD-tRP) 7-7-7 9-9-9 7-7-7 9-9-9 9-9-9 9-9-9 9-9-9 9-9-9

Note: This document supports all LTU Series DDR3 240Pin UDIMM products. Some item was be EOL in this list, Please contact with our sales Dep.

Rev 1.0 Nov. 2010

DDR3 Registered DIMM Spec Sheet

Pin Assignments
240-Pin DDR3 RDIMM Front
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1 2 Vrefdq Vss 31 32 DQ25 Vss 61 62 A2 Vdd 91 92 DQ41 Vss 121 122 Vss DQ4

240-Pin DDR3 RDIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol
151 152 Vss DM3/ DQS12/ TDQS12 NU/ DQS12#/ TDQS12# Vss DQ30 181 182 A1 Vdd 211 212 Vss DM5/ DQS14/ TDQS14 NU/ DQS14#/ TDQS14# Vss DQ46

3 4 5

DQ0 DQ1 Vss

33 34 35

DQS3# DQS3 Vss

63 64 65

NC NC Vdd

93 94 95

DQS5# DQS5 Vss

123 124 125

DQ5 Vss DM0/ DQS9/ TDQS9 NU/ DQS9#/ TDQS9# Vss DQ6 DQ7 Vss DQ12

153 154 155

183 184 185

Vdd CK0 CK0#

213 214 215

6 7 8 9 10 11

DQS0# DQS0 Vss DQ2 DQ3 Vss

36 37 38 39 40 41

DQ26 DQ27 Vss CB0 CB1 Vss

66 67 68 69 70 71

Vdd Vrefca Par_In Vdd A10 BA0

96 97 98 99 100 101

DQ42 DQ43 Vss DQ48 DQ49 Vss

126 127 128 129 130 131

156 157 158 159 160 161

DQ31 Vss CB4 CB5 Vss DM8/ DQS17 / TDQS17 NU/ DQS17#/ TDQS17# Vss CB6

186 187 188 189 190 191

Vdd EVENT# A0 Vdd BA1 Vdd

216 217 218 219 220 221

DQ47 VSS DQ52 DQ53 Vss DM6/ DQS15/ TDQS15 NU/ DQS15#/ TDQS15# Vss DQ54

12 13 14

DQ8 DQ9 Vss

42 43 44

DQS8# DQS8 Vss

72 73 74

Vdd WE# CAS#

102 103 104

DQS6# DQS6 Vss

132 133 134

DQ13 Vss

162 163

192 193 194

RAS# S0# Vdd

222 223 224

15 16 17 18 19 20

DQS1# DQS1 Vss DQ10 DQ11 Vss

45 46 47 48 49 50

CB2 CB3 Vss Vtt Vtt CKE0

75 76 77 78 79 80

Vdd S1# ODT1 Vdd NC Vss

105 106 107 108 109 110

DQ50 DQ51 Vss DQ56 DQ57 Vss

135 136 137 138 139 140

DM1/ DQS10/ 164 TDQS10 NU/ DQS10#/ 165 TDQS10# Vss 166 DQ14 DQ15 Vss DQ20 167 168 169 170

CB7 Vss NC RESET# CKE1 Vdd

195 196 197 198 199 200

ODT0 A13 Vdd NC Vss DQ36

225 226 227 228 229 230

DQ55 Vss DQ60 DQ61 Vss DM7/ DQS16/ TDQS16 NU/ DQS16# TDQS16# Vss DQ62

21 22 23

DQ16 DQ17 Vss

51 52 53

Vdd BA2 Err_Out#

81 82 83

DQ32 DQ33 Vss

111 112 113

DQS7# DQS7 Vss

141 142 143

DQ21 Vss DM2/ DQS11/ TDQS11 NU/ DQS11#/ TDQS11# Vss DQ22 DQ23 Vss DQ28 DQ29

171 172 173

A15 A14 Vdd

201 202 203

DQ37 Vss DM4/ DQS13/ TDQS13 NU/ DQS13# TDQS13# Vss DQ38 DQ39 Vss DQ44 DQ45

231 232 233

24 25 26 27 28 29 30

DQS2# DQS2 Vss DQ18 DQ19 Vss DQ24

54 55 56 57 58 59 60

Vdd A11 A7 Vdd A5 A4 Vdd

84 85 86 87 88 89 90

DQS4# DQS4 Vss DQ34 DQ35 Vss DQ40

114 115 116 117 118 119 120

DQ58 DQ59 Vss SA0 SCL SA2 Vtt

144 145 146 147 148 149 150

174 175 176 177 178 179 180

A12 A9 Vdd A8 A6 Vdd A3

204 205 206 207 208 209 210

234 235 236 237 238 239 240

DQ63 Vss Vddspd SA1 SDA Vss Vtt

Rev 1.0 Nov. 2010

DDR3 Registered DIMM Spec Sheet

Pin Description
Description Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A10 LOW, bank selected by A[15:0] Input BA[2:0]) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also used for BC4/BL8 identification as BL on-the-fly during CAS commands. The address inputs also provide the op-code during the mode register command set. A[13:0] address the 1Gb DDR3 devices. A[15:14] are needed to calculate parity on the command/address bus. Bank address inputs: BA[2:0] define the device bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register BA[2:0] Input (MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command. BA[2:0] are used as part of the parity calculation. Clock: CK and CK# are differential clock inputs. All control, command, and address input CK0, CK0# Input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal CKE[1:0] Input circuitry and clocks on the DRAM. Input data mask: DM is an input mask signal for write data. Input data is masked when DM is DM[8:0] sampled HIGH, along with the input data, during a write access. DM is sampled on both edges (TDQS[17:9], Input of the DQS. Although the DM pins are input-only, the DM loading is designed to match that of TDQS#[17:9]) the DQ and DQS pins. When TDQS is enabled, DM is disabled and TDQS and TDQS# provide termination resistance, otherwise the TDQS# pins are no function. On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DRAM. When enabled in normal operation, ODT is ODT[1:0] Input applied only to the following pins: DQ, DQS, DQS#, and DM. The ODT input will be ignored if disabled via the LOAD MODE command. Par_In Input Parity input: Parity bit for the address, RAS#, CAS#, and WE#. RAS#, CAS#, Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being Input WE# entered. Reset: RESET# is an active LOW CMOS input referenced to Vss. The RESET# input receiver Input RESET# (LVCMOS) is a CMOS input defined as a rail-to-rail signal with DC HIGH 0.8 Vdd and DC LOW 0.2 Vdd. Chip select: S# enables (registered LOW) and disables (registered HIGH) the command S#[3:0] Input decoder. Serial address inputs: These pins are used to configure the temperature sensor/SPD SA[2:0] Input EEPROM address range on the I2C bus. Serial clock for temperature sensor/SPD EEPROM: SCL is used to synchronize SCL Input communication to and from the temperature sensor/SPD EEPROM. CB[7:0] DQ[63:0] DQS[8:0], DQS#[8:0] SDA Err_Out# EVENT# Vdd Vddspd Vrefca Vrefdq Vss Vtt NC NU I/O I/O I/O I/O Check bits: Data used for ECC. Data input/output: Bidirectional data bus. Data strobe: DQS and DQS# are differential data strobes. Output with read data. Edge-aligned with read data. Input with write data. Center-aligned with write data. DQS# is used only when the differential data strobe mode is enabled via the LOAD MODE command. Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of the temperature sensor/SPD EEPROM on the module on the I2C bus. Symbol Type

Output Parity error output: Parity error found on the command and address bus. (open-drain) Output Temperature event: The EVENT# pin is asserted by the temperature sensor when critical (open-drain) temperature thresholds have been exceeded. Power supply: 1.5V 0.075V. The component Vdd and Vddq are connected to the module Supply Vdd. Supply Temperature sensor/SPD EEPROM power supply: +3.0V to +3.6V. Supply Reference voltage: Control, command, and address (Vdd/2). Supply Reference voltage: DQ, DM (Vdd/2). Supply Ground. Supply Termination voltage: Used for control, command, and address (Vdd/2). No connect: These pins are not connected on the module. Not used: These pins are not used in specific module configuration/operations.

Rev 1.0 Nov. 2010

DDR3 Registered DIMM Spec Sheet

Simplified Mechanical Drawing(x8 1Rank)

Note: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. Note: 2. The dimensional diagram is for reference only.

Rev 1.0 Nov. 2010

DDR3 Registered DIMM Spec Sheet

Simplified Mechanical Drawing(x8 2Ranks)

Note 1: All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. Note 2: The dimensional diagram is for reference only.

Rev 1.0 Nov. 2010

DDR3 Registered DIMM Spec Sheet

Simplified Mechanical Drawing(x8 4Ranks)

Note 1: All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. Note 2: The dimensional diagram is for reference only.

Rev 1.0 Nov. 2010

DDR3 Registered DIMM Spec Sheet

Simplified Mechanical Drawing(x4 1Rank)

Note 1: All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. Note 2: The dimensional diagram is for reference only.

Rev 1.0 Nov. 2010

DDR3 Registered DIMM Spec Sheet

Simplified Mechanical Drawing(x4 2Ranks)

Note 1: All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. Note 2: The dimensional diagram is for reference only.

Rev 1.0 Nov. 2010