IMP Digital Slides

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Sandeepani School of VLSI Design

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Digital Logic
For VLSI Design
Bangalore/Hyderabad
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System:
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Digital System!
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Combinational vs. Sequential
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Levels of integrated circuits
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Binary Valued Signals
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Binary Valued Signals contd
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Binary Valued Signals contd
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Two logic levels but very powerful
applications possible!
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VLSI: but why?
Integration improves the design:
lower parasitics = higher speed;
lower power;
physically smaller.
Integration reduces manufacturing cost-(almost) no
manual assembly.
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VLSI Applications
VLSI is an implementation technology for electronic
circuitry - analogue or digital
It is concerned with forming a pattern of
interconnected switches and gates on the surface of
a crystal of semiconductor
Microprocessors
personal computers
microcontrollers
Memory - DRAM / SRAM
Special Purpose Processors - ASICS (CD players, DSP
applications)
Optical Switches
Has made highly sophisticated control systems mass-
producible and therefore cheap
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What is a Silicon Chip?
A pattern of interconnected switches and gates on the
surface of a crystal of semiconductor (typically Si)
These switches and gates are made of
areas of n-type silicon
areas of p-type silicon
areas of insulator
lines of conductor (interconnects) joining areas
together
Aluminium, Copper, Titanium, Molybdenum,
polysilicon, tungsten
The geometry of these areas is known as the layout
of the chip
Connections from the chip to the outside world are
made around the edge of the chip to facilitate
connections to other devices
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Logic families
Commonly used are 3
Transistor-Transistor logic (TTL)
Complementary metal oxide semiconductor
(CMOS)
Emitter Coupled Logic (ECL)
Most important characteristics of TTL & CMOS
are that
TTL gates switch very fast
CMOS has very low power dissipation
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CMOS Technology: Modern Logic Design
First proposed in the 1960s. Was not seriously considered
until the severe limitations in power density and
dissipation occurred in NMOS circuits
Now the dominant technology in IC manufacturing
Employs both pMOS and nMOS transistors to form logic
elements
The advantage of CMOS is that its logic elements draw
significant current only during the transition from one
state to another and very little current between
transitions - hence power is conserved.
In the case of an inverter, in either logic state one of the
transistors is off. Since the transistors are in series, (~ no)
current flows.
See twin-well cross sections
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BiCMOS
A known deficiency of MOS technology is its limited load
driving capabilities (due to limited current sourcing and
sinking abilities of pMOS and nMOS transistors.
Bipolar transistors have
higher gain
better noise characteristics
better high frequency characteristics
BiCMOS gates can be an efficient way of speeding up VLSI
circuits
See table for comparison between CMOS and BiCMOS
CMOS fabrication process can be extended for BiCMOS
Example Applications
CMOS - Logic
BiCMOS- I/O and driver circuits
ECL - critical high speed parts of the system
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CMOS Inverter
V
DD
A Y
GND
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CMOS NAND gates
A
B
Y
V
dd
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CMOS NOR gates
A
B
Y
V
DD
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NMOS gates
Inverter
Nand
Nor
Nand/Nor preference
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Exercise
Implement AND,OR gates using CMOS
logic
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CMOS Vs Bipolar Technology
CMOS Technology
Low static power
dissipation
High i/p impedance
(low drive current)
Medium speed
High packing density
Low o/p drive current
Bidirectional capability
A near ideal switching
Bipolar Technology
High power dissipation
Low i/p impedance (high
drive current)
High speed
Low packing density
High o/p drive current
Essentially unidirectional
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Moores
Law
Gordon Moore: co-founder of Intel.
Predicted that number of transistors per
chip would grow exponentially (double
every 18 months).
Exponential improvement in technology
is a natural trend: steam engines,
dynamos, automobiles. Moores Law
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Moores Law plot
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CPLD Basics Review:
What is a CPLD?
Definition:
Complex
Programmable
Logic Device - A
hybrid of PLD
blocks and
interconnect for
mid-size logic
designs
IO/Registers/Logic IO/Registers/Logic Interconnect
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CPLD Architecture
I/O - Input Output block. The gateway between the CPLD fabric and the outside world
MC - Macrocell. The Part of the CPLD architecture containing the register
Logic Block - Where product terms are built
Product Term - Single logical function made out of AND and OR terms
Interconnect Array - Connection between the I/O, MC, and logic blocks
Function Block - The name for a logic block and its associated macrocells
I
n
t
e
r
c
o
n
n
e
c
t

A
r
r
a
y
MCn
MC0
I/O I/O
MCn
MC0
I/O I/O
Logic
Block
MCn
MC0
Logic
Block
Logic
Block
Logic
Block
MCn
MC0
Function Block
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CPLD Definitions:
High Performance
Pin-to-pin
combinatorial delay
Time from input
through interconnect
to output (ns)
Maximum registered
frequency
Fastest operation of
flip-flops (MHz)
Tpd (ns) Fmax (MHz)
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CPLDs versus FPGAs
CPLD architecture
FPGA architecture
Product term array
Interconnect array
Wide fanin
Deterministic timing
Pin locking
Look-up table based
X/Y routing matrix
Higher density
Additional features
DLL
Multipliers
I
n
t
e
r
c
o
n
n
e
c
t

A
r
r
a
y
MCn
MC0
I/O
I/O
MCn
MC0
I/O
I/O
Logic
Block
MCn
MC0
Logic
Block
Logic
Block
Logic
Block
MCn
MC0
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
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CPLD or FPGA?
CPLD
Non-volatile
Consistent pin-to-pin timing
Simple timing model
Very low power consumption
Lowest cost point
Fast internal performance
Small packages (CP56, 132)
Applications - Logic decode/
integration, state machines
FPGA
Volatile
Requires memory device
to load design at power up
Complex timing model
Large complex designs
Memory resources
Applications - PCI, high-
speed serial
communication, embedded
processors
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Field-programmable gate arrays
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FPGAs and VLSI
FPGAs are standard parts:
Pre-manufactured, shorter design cycle.
Dont worry (much) about physical design.
Time to market is less, but FPGAs are slower,
larger, more power-hungry.
Custom silicon:
Tailored to your application.
Generally lower power consumption.
Time to market is more
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Embedded Digital System: The big
picture
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A Historical Perspective: the
PLA
x
0
x
1
x
2
AND
plane
x
0
x
1
x
2
Product terms
OR
plane
f
0
f
1
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Two-Level Logic
Inverting format (NOR-
NOR) more effective
Every logic function can be
expressed in sum-of-products
format (AND-OR)
minterm
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Array-Based Programmable Logic
PLA PROM PAL
I
5
I
4
O
0
I
3
I
2
I
1
I
0
O
1
O
2
O
3
Programmable AND array
Programmable
OR array
I
5
I
4
O
0
I
3
I
2
I
1
I
0
O
1
O
2
O
3
Programmable AND array
Fixed OR array
Indicates programmable connection
Indicates fixed connection
O
0
I
3
I
2
I
1
I
0
O
1
O
2
O
3
Fixed AND array
Programmable
OR array
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Programming a PROM
f
0
1 X
2
X
1
X
0
f
1
NA NA
: programmed node
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More Complex PAL
From Smith97
i inputs, j minterms/macrocell, k macrocells
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Number System & Conversions
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Code conversions
Self-complementary code
Weighed & Non Weighed codes
Recap
Binary Addition
Binary Subtraction
Binary multiplication
Binary Division
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Exercise
Convert 101100.101 into hexadecimal, octal and
decimal.
Convert F4A into binary
Answers :
- 101100.101 (2) = 2C.A (16) = 44.625 (10)
- 101100.101 (2) = 54.5 (8)
- F4A (16 )=111101001010 (2)
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General Positional Number
Conversion
radix-r to decimal :
decimal to radix-r :
- Successive division of D by r
- The remainder of the long division will give the
digits starting from the least significant digit
D d r i
i n
p
i
=
=
1
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Example - Decimal to Binary :
179 (10)
179/2 = 89 ( 1 ) LSB
89/2 = 44 ( 1 )
44/2=22 ( 0 )
22/2=11 ( 0 )
11/2=5 ( 1 )
5/2=2 ( 1 )
2/2=1 ( 0 )
1/2=0 (1)MSB
Result : 10110011 (2)
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Hexadecimal Addition
Add digits in Convert each digit into decimal
decimal
Convert the result into Hexadecimal
Produce carry when digits sum is > = the radix (16 )
Example
1 0 1 0 1 0 1 0
2 F A 5 2 15 10 5
+ A 9 3 C 10 9 3 12
_________ _______________
D 8 E 1 (13) (16+8) (14) (16+1)
D 8 E 1
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Switching Algebra
Definition
Shannons expansion theorem
Principle of duality
Complementation rules
SOP and POS
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Duality
Axioms and Theorems come in
pairs
Get one of the pair from the other by:
1. Replacing AND with OR
2. Replacing OR with AND
3. Replacing 1 with 0
4. Replacing 0 with 1
If E is a valid Boolean expression,
then E
d
(its dual) is also valid
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Canonical Forms
Literal switching variable or its
complement (e.g., x or y)
Product Term or Implicant series of
literals related by AND operator
Sum Term Series of literals related by
OR operator
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Boolean Algebra
AXIOMS :
DEFINITIONS:
THEOREMS:
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Prove the following:
(Do not use K-maps)
1. A + AB = A+B
2. Sum of products of three variables is equal to 1.
3. Product of sums of three variables is equal to 0.
4. ABC+ABC+ABC+ABC+ABC = AB+C
Problems
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Representation Of Numbers: a revision
Signed magnitude
1s Complement
2s Complement
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Signed magnitude representation
Humans use a signed-magnitude system: we add + or - in front of a
magnitude to indicate the sign.
We could do this in binary as well, by adding an extra sign bit to the
front of our numbers. By convention:
A 0 sign bit represents a positive number.
A 1 sign bit represents a negative number.
Examples:
1101
2
= 13
10
(a 4-bit unsigned number)
01101 = +13
10
(a positive number in 5-bit signed magnitude)
1 1101 = -13
10
(a negative number in 5-bit signed magnitude)
0100
2
= 4
10
00100 = +4
10
(a positive number in 5-bit signed magnitude)
1 0100 = -4
10
(a negative number in 5-bit signed magnitude)
Range?
Limitation?
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The MSB represents the sign bit ( 0 = +ve , 1 = -ve )
The range for n-bit is :
Example: n=5
* Range : from -15 to 15
* 10011= -3 , 01100 = +12
* 00000= 0 , 10000 = - 0
Disadvantages :
1- Two possible representations of zero
2- Complicated digital adders
from to
n n
+

( ) ( ) 2 1 2 1
1 1
Signed Magnitude Representation
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Ones complement Representation
A different approach, ones complement, negates numbers by
complementing each bit of the number.
We keep the sign bits: 0 for positive numbers, and 1 for negative.
The sign bit is complemented along with the rest of the bits.
Examples:
1101
2
= 13
10
0 1101 = +13
10
(a positive number in 5-bit ones
complement)
1 0010 = -13
10
(a negative number in 5-bit ones
complement)
0100
2
= 4
10
0 0100 = +4
10
(a positive number in 5-bit ones complement)
1 1011 = -4
10
(a negative number in 5-bit ones
complement)
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Why is it called 1s complement?
Complementing a single bit is equivalent to subtracting it from 1.
0 = 1, and 1 - 0 = 1 1 = 0, and 1 - 1 = 0
Similarly, complementing each bit of an n-bit number is equivalent
to subtracting that number from 2
n
-1.
For example, we can negate the 5-bit number 01101.
Here n=5, and 2
n
-1 = 31
10
= 11111
2
.
Subtracting 01101 from 11111 yields 10010:
1 1 1 1 1
- 0 1 1 0 1
1 0 0 1 0
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1s complement addition
To add ones complement numbers:
First do unsigned addition on the numbers, including the sign
bits.
Then take the carry out and add it to the sum.
Two examples:
This is simpler and more uniform than signed magnitude addition.
0111 (+7)
+ 1011 + (-4)
1 0010
0010
+ 1
0011 (+3)
0011 (+3)
+ 0010 + (+2)
0 0101
0101
+ 0
0101 (+5)
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Twos complement
Our final idea is twos complement. To negate a number, complement
each bit (just as for ones complement) and then add 1.
Examples:
1101
2
= 13
10
0 1101 = +13
10
(a positive number in 5-bit twos complement)
1 0010 = -13
10
(a negative number in 5-bit ones complement)
1 0011 = -13
10
(a negative number in 5-bit twos complement)
0100
2
= 4
10
0 0100 = +4
10
(a positive number in 5-bit twos complement)
1 1011 = -4
10
(a negative number in 5-bit ones complement)
1 1100 = -4
10
(a negative number in 5-bit twos complement)
Range?
Limitation?
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Floating point numbers
Fixed point number can not represent very large and very small
numbers.
Example: N = M * B
E
for 8bit E range from 128 to +127
IEEE format
N= 1. M * 2
E - 127
(single precision 32 bit) E = E -127
1. M * 2
E - 1023
(single precision 64 bit) E = E 1023
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Problems
Q. Represent the following in single precision format
(i ) 0.0110 * 2
6
(ii) 1
(iii)(10)
10
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1. (500.21)
10
= ( ? )
2
2. (436.71)8 = ( ? )
16
3. Convert (231.3)Base 4 to Base 7
Convert Base 4 to Base 10
Convert Base 10 to Base 7
Ans : (63.515) Base 7
Examples
4. 316
8
451
8
= ? (Hint: Use 8s Complement)
5. CB2
H
972
H
= ? (Hint: Use 16s Complement)
6. 0011.1001
2
0001.1110
2
= ? Using 1s complement form
7. 79 - 26 in BCD representation? (Hint: Use 9s
Complement)
8. 5 - 8 in XS-3?
9. Divide (10)
10
by (4)
10
in binary representation.
10. Convert (847)
10
to gray code representation.
11. Perform direct subtraction: (9)
10
(10)
10
?
12. What is Hamming code?
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Gates: electronic circuit that realizes a logical expression
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Logical Expressions
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NAND/NOR Networks
Convert AND/OR Network into NAND/NOR
Network
Tips and Tricks
Think of bubbles on gates as inverters
Think of EXOR & EXNOR as parity ckts that
produce a 1 out if the number of 1s in is odd
or even respectively
Use alternative NAND/NOR symbols
A 2 level NAND-NAND /NOR-NOR ckt is
equivalent to a 2 level AND-OR / OR-AND ckt
respectively and realize SOP / POS logical
expressions
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Structural Model of gates
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Ideal and real gates are different
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Discussion
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K-Maps
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SOP and POS Implementation
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Some Arithmetic Circuits
Adders:
Half adder
Full adder
Serial adder
Ripple carry adder
Carry Bypass adder
Carry look ahead adder
Carry select adder
Multipliers:
2-bit by 2-bit Multiplier
4-bit by 3-bit Multiplier
Magnitude Comparator
2-bit Comparator
4-bit Comparator
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Adders
Adder delay is dominated by carry
chain.
Carry chain analysis must consider
transistor, wiring delay.
Modern VLSI favors adder designs
which have compact carry chains.
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Implementation of Half Adder
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Implementation of Full Adder
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4-Bit Ripple carry adder
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Ripple Carries
Cascade 64 full adders to get a 64-bit
ripple carry adder
Problem: Slow carries ripple
If stage delay = 20 nsec, Total delay =
64 X 20 = 1280 nsec
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Full adder
Computes one-bit sum, carry:
s
i
= a
i
XOR b
i
XOR c
i
c
i+1
= a
i
b
i
+ a
i
c
i
+ b
i
c
i
Half adder computes two-bit sum.
Ripple-carry adder: n-bit adder built
from full adders.
Delay of ripple-carry adder goes
through all carry bits.
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4-Bit Carry Adder-Subtractor
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Serial Adder
Delay
Xi
Yi
Si
Ci + 1
Ci
Full Adder
Q. Design a 4-bit serial adder with the help of two shift
register?
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Carry Look-ahead Adder
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Carry-look ahead adder
First compute carry
propagate,
generate:
P
i
= a
i
+ b
i
G
i
= a
i
b
i
Compute sum and
carry from P and G:
s
i
= c
i
XOR P
i
XOR G
i
c
i+1
= G
i
+ P
i
c
i
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Carry Equations
4 stage binary carry look-ahead adder
A
1-4
, B
1-4
are addends, C
0
is input carry
Outputs are Sum S
1-4
and Carries C
1-4
Multiply out equations:
C
1
= G
1
+ P
1
C
0
C
2
= G
2
+ P
2
C
1
= G
2
+ P
2
G
1
+ P
2
P
1
C
0
C
3
= G
3
+ P
3
C
2
= G
3
+ P
3
G
2
+ P
3
P
2
G
1
+
P
3
P
2
P
1
C
0
C
4
= G
4
+ P
4
C
3
= G
4
+ P
4
G
3
+ P
4
P
3
G
2
+
P
4
P
3
P
2
G
1
+ P
4
P
3
P
2
P
1
C
0
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Carry Look-Ahead Adder
Big speedup At most 4 logic delays to get all
carries
n = # full adder chips
t
total
= t
XOR
+ log
4
n X t
LACG
+ t
FA
t
XOR
= 10 nsec
t
LACG
= carry lookahead stage delay = 21 nsec
t
FA
= full adder delay = 15 nsec
t
total
= 10 nsec + 1 X 21 nsec + 15 nsec = 46
nsec
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Depth-4 carry-look ahead
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Analysis
Deepest carry expansion requires gates
with large fan in: large, slow.
Carry-look ahead unit requires complex
wiring between adders and look ahead
unitvalues must be routed back from
look ahead unit to adder.
Layout is even more complex with
multiple levels of look ahead.
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4 bit Carry Look-ahead Adder
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Carry-skip adder
Looks for cases in which carry out of a
set of bits is identical to carry in.
Typically organized into b-bit stages.
Can bypass carry through all stages in a
group when all propagates are true: P
i
P
i+1
P
i+b-1
.
Carry out of group when carry out of last
bit in group or carry is bypassed.
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Two-bit carry-skip structure
AND
P
i
P
i+1
P
i+b-1
OR
C
i+b-1
c
i
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Carry-skip structure
b adder stages
skip
P[0,b-1] Carry out
b adder stages
skip
P[b,2b-1] Carry out
b adder stages
skip
P[2b,3b-1]
Carry out
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Worst-case carry-skip
Worst-case carry-propagation path goes
through first, last stages:
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Delay analysis
Assume that skip delay = 1 bit carry
delay.
Delay of k-bit adder with block size b:
T = (b-1) + 0.5 + (k/b 2) + (b-1)
block 0 OR gate skips last block
For equal sized blocks, optimal block
size is sqrt(k/2).
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Carry-select adder
Computes two results in parallel, each
for different carry input assumptions.
Uses actual carry in to select correct
result.
Reduces delay to multiplexer.
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Carry select adder
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Carry-select structure
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Carry-save adder
Useful in multiplication.
Input: 3 n-bit operands.
Output: n-bit partial sum, n-bit carry.
Use carry propagate adder for final sum.
Operations:
s = (x + y + z) mod 2.
c = [(x + y + z) 2] / 2.
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Pseudo or Carry Save Adder
Advantage only final stage of partial-
product addition needs to propagate
carries
A
16
B C
IN
Carries Sum
16 16
16 16
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Carry Save Addition (CSA)
A full adder sums 3 inputs and produces 2 outputs
Carry output has twice weight of sum output
N full adders in parallel are called carry save adder
Produce N sums and N carry outs
Z
4
Y
4
X
4
S
4
C
4
Z
3
Y
3
X
3
S
3
C
3
Z
2
Y
2
X
2
S
2
C
2
Z
1
Y
1
X
1
S
1
C
1
X
N...1
Y
N...1
Z
N...1
S
N...1
C
N...1
n-bit CSA
CG-CoreEl
CG-CoreEl
CSA Application
Use k-2 stages of CSAs
Keep result in carry-save redundant form
Final CPA computes actual result
4-bit CSA
5-bit CSA
0001 0111 1101 0010
+
1011
0101_
0001
0111
+1101
1011
0101_
X
Y
Z
S
C
0101_
1011
+0010
X
Y
Z
S
C
A
B
S
CG-CoreEl
CG-CoreEl
CSA Application
4-bit CSA
5-bit CSA
0001 0111 1101 0010
+
1011
0101_
01010_ 00011
0001
0111
+1101
1011
0101_
X
Y
Z
S
C
0101_
1011
+0010
00011
01010_
X
Y
Z
S
C
01010_
+ 00011
A
B
S
CG-CoreEl
CG-CoreEl
CSA Application
4-bit CSA
5-bit CSA
0001 0111 1101 0010
+
1011
0101_
01010_ 00011
0001
0111
+1101
1011
0101_
X
Y
Z
S
C
0101_
1011
+0010
00011
01010_
X
Y
Z
S
C
01010_
+ 00011
10111
A
B
S
10111
CG-CoreEl
CG-CoreEl
Adder comparison
Ripple-carry adder has highest
performance/cost.
Optimized adders are most effective in
very long bit widths (> 48 bits).
CG-CoreEl
CG-CoreEl
0
50
100
150
200
250
300
350
8
4
0
7
2
Bits
C
o
s
t

(
C
L
B
s
)
0
50
100
150
200
250
300
350
400
8
3
2
5
6
8
0
Bits
P
e
r
f
o
r
m
a
n
c
e
-
C
o
s
t

R
a
t
i
o
Ripple
Complet e
CLA
Skip
RC-select
1998 IEEE
0
20
40
60
80
100
120
8
3
2
5
6
8
0
Bits
O
p
e
r
a
t
i
o
n
a
l

T
i
m
e

(
n
s
)
CG-CoreEl
CG-CoreEl
Serial adder
May be used in signal-processing
arithmetic where fast computation is
important but latency is unimportant.
Data format (LSB first):
0 1 1 0
LSB
CG-CoreEl
CG-CoreEl
Serial adder structure
LSB control signal clears the carry shift
register:
CG-CoreEl
CG-CoreEl
BCD Adder
CG-CoreEl
CG-CoreEl
2bit X 2bit Multiplier
CG-CoreEl
CG-CoreEl
4bit X 3bit Multiplier
CG-CoreEl
CG-CoreEl
Q. Design a 2-bit digital comparator that accepts two
words A and B and gives three outputs :
G(>),
E(=) and
L(<).
CG-CoreEl
CG-CoreEl
Q. Design a 4-bit digital comparator that accepts two
words A and B and gives three outputs :
G(>),
E(=) and
L(<).
CG-CoreEl
CG-CoreEl
2-bit Magnitude Comparator
Answer:
let x
1
= (A
1
ex-nor B
1
)
x
0
= (A
0
ex-nor B
0
)
Z
A=B
= x
1
. x
0
Z
A>B
= A
1
B
1
+ x
1
. A
0
B
0
Z
A<B
= A
1
B
1
+ x
1
. A
0
B
0
CG-CoreEl
CG-CoreEl
4-bit Magnitude Comparator
Answer:
Z
A=B
= x
3
. x
2
. x
1
. x
0
Z
A>B
= A
3
B
3
+ x
3
. A
2
B
2
+x
3
. x
2
. A
1
B
1
+ x
3
. x
2
. x
1
. A
0
B
0
Z
A<B
= A
3
B
3
+ x
3
. A
2
B
2
+x
3
. x
2
. A
1
B
1
+ x
3
. x
2
. x
1
. A
0
B
0
CG-CoreEl
CG-CoreEl
A0
B0
A1
B1
A2
B2
A>B
A<B
A=B
A=B
output
A<B
output
A>B
output
CG-CoreEl
CG-CoreEl
Binary Multipliers
1. Extremely complex even for small
word length
2. Very hard to test
3. Truth table expansion varies with
word length
4. Must use at least one carry
propagating full adder to sum up
partial products
CG-CoreEl
CG-CoreEl
Multiplication Equations
Multiplicand A = A
h
X 2
4
+ A
l
Multiplier B = B
h
X 2
4
+ B
l
Product P = A X B = A
h
X B
h
X 2
8
+ (A
h
X
B
l
+ A
l
X B
h
) X 2
4
+ (A
l
X B
l
)
Must sum the 4 partial products
Since A & B are 8 bits, product is 16 bits
Need 5 full adders to do this
CG-CoreEl
CG-CoreEl
74LS274 Produces 8-bit product
4X4 bit Binary Multiplier
CG-CoreEl
CG-CoreEl
Example
Cell 1
X
11
X
12
X
1l
Z
11
Z
12
Z
1m
Cell 2
X
21
X
22
X
2l
Z
21
Z
22
Z
2m
Y
21
Y
22
Y
2k
Cell i
X
i1
X
i2
X
il
Z
i1
Z
i2
Z
im
Y
i1
Y
i2
Y
ik
Y
i1
Y
i2
Y
ik
CG-CoreEl
CG-CoreEl
Multiplication
Example:
1100 : 12
10
0101 : 5
10
1100
0000
1100
0000
00111100 : 60
10
CG-CoreEl
CG-CoreEl
Multiplication
Example:
M x N-bit multiplication
Produce N M-bit partial products
Sum these to produce M+N-bit product
1100 : 12
10
0101 : 5
10
1100
0000
1100
0000
00111100 : 60
10
multiplier
multiplicand
partial
products
product
CG-CoreEl
CG-CoreEl
General Form
Multiplicand: Y = (y
M-1
, y
M-2
, , y
1
, y
0
)
Multiplier: X = (x
N-1
, x
N-2
, , x
1
, x
0
)
Product:
1 1 1 1
0 0 0 0
2 2 2
M N N M
j i i j
j i i j
j i i j
P y x x y

+
= = = =
| |
| |
= =
|
|
\ .
\ .

x
0
y
5
x
0
y
4
x
0
y
3
x
0
y
2
x
0
y
1
x
0
y
0
y
5
y
4
y
3
y
2
y
1
y
0
x
5
x
4
x
3
x
2
x
1
x
0
x
1
y
5
x
1
y
4
x
1
y
3
x
1
y
2
x
1
y
1
x
1
y
0
x
2
y
5
x
2
y
4
x
2
y
3
x
2
y
2
x
2
y
1
x
2
y
0
x
3
y
5
x
3
y
4
x
3
y
3
x
3
y
2
x
3
y
1
x
3
y
0
x
4
y
5
x
4
y
4
x
4
y
3
x
4
y
2
x
4
y
1
x
4
y
0
x
5
y
5
x
5
y
4
x
5
y
3
x
5
y
2
x
5
y
1
x
5
y
0
p
0
p
1
p
2
p
3
p
4
p
5
p
6
p
7
p
8
p
9
p
10
p
11
multiplier
multiplicand
partial
products
product
CG-CoreEl
CG-CoreEl
16X16 Mult. Dot Diagram
Each dot represents a bit
partial products
m
u
l
t
i
p
l
i
e
r

x
x
0
x
15
CG-CoreEl
CG-CoreEl
Parallel Binary Multiplier
+
Y
P C
Y
X
CO
PO
X
CG-CoreEl
CG-CoreEl
X
+
Y
P C
Y
X
CO
PO
One-Bit Multiplier Cell
CG-CoreEl
CG-CoreEl
Comparator Time Delays
Linear connection
t
c
= individual comparator delay
t
total
= m t
c
, for m comparators = 4
X 27 = 162 nsec (4-bit slices)
Cascaded connection
t
total
= (log
4
m + 1) X t
c
= 2 X 27 = 54
nsec
CG-CoreEl
CG-CoreEl
Problems
Q.1. Design a circuit which will accept 4-bit binary and
will provide 5-bit BCD code?
Q.2. Design a 3-bit squarer?
Q.3. A circuit accepts a 4-bit I/p data & generates an o/p
Z=1whenever I/p is a prime number. Design the
circuit?
CG-CoreEl
CG-CoreEl
Problems
Q.4. The conditions under which an insurance company
will issue a policy are :
A married female 25 years old or older, or
A female under 25 years or
A married male under 25 years with no accident record, or
A married male with accident record, or
A married male under 25 years or older with no accident
record.
Obtain a simplified logic expression starting to whom a policy can be
issued.
CG-CoreEl
CG-CoreEl
Universal Logic Element
CG-CoreEl
CG-CoreEl
Universal Logic Element
Which of these are Universal logic
elements?
1. 2:1 MUX
2. Ex-or2
3. {f(x,y)=xy}
4. {f(x,y,z)=(x+y)z}
5. Nand2
CG-CoreEl
CG-CoreEl
Universal Logic Gate
Introduction
A set of gates is said to be universal if any
combinational system can be implemented using
gates just from that set.
The set {AND,NOT} or {OR,NOT} is universal .
So any set of gates that can implement either
{AND,NOT} or {OR,NOT} is universal.
CG-CoreEl
CG-CoreEl
Universal Logic gate : Nand2
Lets start with NAND gate.
NAND(x,y)= (xy) NAND(x,x)=(xx)=x NOT(x)=NAND(x,x)
NOT gate can be implemented by a NAND gate
AND(x,y)= xy = ((xy))=(NAND(x,y)) . From the previous step, we know
how to implement NOT gate by a NAND gate
AND(x,y)=(NAND(x,y))=NAND(NAND(x,y), NAND(x,y))
So,AND gate can be implemented by only using NAND gates
Since we can implement AND and NOT by only NAND gates,
{NAND, NOR} is a universal set,even without NOR gate.
CG-CoreEl
CG-CoreEl
Universal Logic Gate NAND Function
NAND ::= Negative AND
Y = ( A B )
NOT
OR
AND
Y
INV
A
A Y
A
B
A
B
AND 2
Y
Y
OR 2
B
Y
A
Y
A
B
=
=
=
NAND 2
Y
Y
A
B
A
Y
A A
NAND 2
B
Y
Y
NAND 2
B
B
A
A
NAND 2
A
NAND 2
B
Y
Y
A
NAND 2
B
Y
A
B
Y
B
CG-CoreEl
CG-CoreEl
Universal Logic Gate NOR Function
NOR ::= Negative OR
Y = ( A + B )
NOT
OR
AND
NOR 2
Y
INV
A
A Y
A
B
A
B
AND 2
Y
Y
OR 2
B
Y
A
Y
A
B
=
=
=
A
NOR 2
B
Y
Y A
A
A
NOR 2
B
Y
Y
A
NOR 2
B
Y
A
B
Y
B
Y
A A
NOR 2
B
Y
Y
NOR 2
B
B
A
CG-CoreEl
CG-CoreEl
Universal Logic Gate Multiplexor Function
Multiplexor
Y = A S + B S
NOT
OR AND
Y
Y
A
Y
V C C
G N D
G N D
G N D
G N D
Y
S 1 S 0
Y
D 0
D 1
D 2
D 3
D 0
D 1
D 2
D 3
M X 4 M X 4
M X 4
A
B
Y
Y
Y
Y
V C C
S 1 S 0
V C C
Y
D 0
D 1
D 2
D 3
S 1 S 0
Y
A
B
Y
Y
Implement the same using 2 to 1 Multiplexer
CG-CoreEl
CG-CoreEl
Basic Data Processing Circuits
CG-CoreEl
CG-CoreEl
2-4 line Decoder with Enable Input
CG-CoreEl
CG-CoreEl
Decoder (3:8)
CG-CoreEl
CG-CoreEl
Problems using Decoder
Q1. Implement 4:16 Decoder using two 3:8 Decoders
Q2. Realize a full adder using one 3:8 decoder & residual gates
Q3. Design BCD to decimal converter
with false data rejected
with false data accepted
CG-CoreEl
CG-CoreEl
4:16 Decoder using 3:8 Decoder
CG-CoreEl
CG-CoreEl
Full Adder using Decoder
CG-CoreEl
CG-CoreEl
Encoder
Decimal-to-BCD Encoder
Octal-to-Binary Encoder
Limitations?
CG-CoreEl
CG-CoreEl
4-Input priority Encoder
CG-CoreEl
CG-CoreEl
Multiplexer
CG-CoreEl
CG-CoreEl
4:1 line Multiplexer
CG-CoreEl
CG-CoreEl
Q1. Realize the following using only one 2:1 Mux
1. NOT
2. And2
3. OR2
4. Ex-or2
5. Ex-nor2
6. Latch
Problems
CG-CoreEl
CG-CoreEl
Q2. Show how two 2-to-1 multiplexers (with no added gates)
could be connected to form a 3-to-1 MUX. Input selection should
be as follows:
If AB = 00, select Io
If AB = 01, select I1
If AB = 1 (B is don`t care), select I2.
Problems
Q3. Realize the function F(A,B,C,D)=m(1,2,3,6,8,9,11,14) using an
8-to-1 MUX with control inputs A,B, and C.
Q4. Repeat Q2 with control inputs A,C, and D.
Q5. Repeat Q2 using a 4-to-1 MUX and added gates.
CG-CoreEl
CG-CoreEl
2-input mux
as programmable logic block
F
A 0
B
S
1
Configuration
A B S F=
0 0 0 0
0 X 1 X
0 Y 1 Y
0 Y X XY
X 0 Y
Y 0 X
Y 1 X X
1
Y
1 0 X
1 0 Y
1 1 1 1
XY
XY
X
Y
CG-CoreEl
CG-CoreEl
Q6. Design a sequence generator that generates the sequence
11100011.
Q7. Design 1:8 demultiplexer using two 1:4 demultiplexers.
Q8. Implement the following boolean function using 8:1 MUX,
F(A,B,C,D) = E(0,1,3,4,8,9,15)
Problems, more problems
CG-CoreEl
CG-CoreEl
Buffer
A Buffer is a logic circuit which has one I/p line & one output line.
It is a current amplifier & also called as driver.
A Tri-State Buffer
Q. Implement a 2-to-1 Mux with Tri-state buffers
CG-CoreEl
CG-CoreEl
Answer
Or
2-1 line Mux with Tri-state buffer
CG-CoreEl
CG-CoreEl
Wired logic
Power dissipation in LOW output state increases
Speed of the operation increases
Fan out decreases
CG-CoreEl
CG-CoreEl
Clock Generator Circuit ?
CG-CoreEl
CG-CoreEl
Now, solve this?
Look at the circuit diagram is given.
The thermometer to binary
conversion logic is a simple
combination circuitry which is to be
designed to provide a natural binary
representation using b
1
and b
0
for
the analog input V
in
, here b1 is the
most significant bit. Also realize the
logic for b
1
and b
o
using 2-input
NAND gates only.
Try to find the resolution of this
circuit.
What circuit is this?
CG-CoreEl
CG-CoreEl
Combinational.
Output depends only on current input values.
Sequential.
Output depends on current input values and
present state of the circuit, where the present
state of the circuit is the current value of the
devices memory.
Sequential circuits
CG-CoreEl
CG-CoreEl
Bistable Elements
The simplest sequential circuit.
It consist of a pair of inverters connected as
shown below. Notice the feedback loop.
CG-CoreEl
CG-CoreEl
Digital Analysis
Two stable states.
If Q is HIGH then the lower inverter has a HIGH at its
input and a LOW at its output. This in turn forces the
upper inverters input to be LOW and its output to be
HIGH.
If Q is LOW then the lower inverter has a LOW at its
input and a HIGH at its output. This in turn forces the
upper inverters input to be HIGH and its output to be
LOW.
CG-CoreEl
CG-CoreEl
Analog Analysis
Metastable behavior:
Consider the middle intersecting point in the
diagram shown below.
What would happen if a small amount of noise
varies either input voltage.
CG-CoreEl
CG-CoreEl
Latches and Flip-Flops
Binary cells capable of storing 1 bit of
information.
Generates one of two possible stable states.
Two outputs labeled Q and Q.
One or more inputs.
These sequential devices differ in the way their
outputs are changed:
The output of a latch changes independent
of a clocking signal.
The output of a flipflop changes at specific
times determined by a clocking signal.
CG-CoreEl
CG-CoreEl
SR Latch with Control Input
CG-CoreEl
CG-CoreEl
D Latch
This latch eliminates the problem that occurs in the SR latch when R=S=0.
C is an enable input:
When C=1 then the output follows the input D and the latch is said to be
open. Due to this fact this latch is also called transparent latch.
When C=0 then the output retains its last value and the latch is said to
be closed.
CG-CoreEl
CG-CoreEl
D Latch
For proper operation
the D input must
not change during a
time interval around
the falling edge of C.
CG-CoreEl
CG-CoreEl
Edge Triggered D Flip-Flop
This flip-flop is made out of two D latches. The first latch is the master, and
the second the slave.
When CLK_L= 1 the master is open and the slave is closed. Q
m
and D
s
follow D
m
.
CG-CoreEl
CG-CoreEl
Edge Triggered D Flip-Flop
Positive edge-triggered D flip-flop.
Q* = D
CG-CoreEl
CG-CoreEl
JK Flip Flop
(USING D flip flop)
CG-CoreEl
CG-CoreEl
Excitation table of Flip Flops
CG-CoreEl
CG-CoreEl
Flip Flop to Flip Flop conversions
CG-CoreEl
CG-CoreEl
FF FF conversions
1. D-T D=TQ
2. T-D T=DQ
3. D-JK D=QJ+QK
4. D-SR
5. T-SR
6. JK-SR
7. SR-JK
CG-CoreEl
CG-CoreEl
D from JK Flip Flop
CG-CoreEl
CG-CoreEl
Problems (doubts)
Q. Design a circuit that generates two waveforms of 90 phase shift.
Q. Design a 50% duty cycle frequency doubler for an input
clk pulse of 50% duty cycle.
More Problems, Many more Problems. Let us continue!
CG-CoreEl
CG-CoreEl
Timing Issues
CG-CoreEl
CG-CoreEl
Timing Issues
Timing parameters
Timing diagram
Set up time
Hold time
Clock Skew
Slack
Critical path
Maximum Frequency of Operation
CG-CoreEl
CG-CoreEl
Timing parameters
CG-CoreEl
CG-CoreEl
Timing parameterscontd
CG-CoreEl
CG-CoreEl
Timing parameterscontd
CG-CoreEl
CG-CoreEl
Timing diagram
CG-CoreEl
CG-CoreEl
Setup and Hold Time
Setup and hold time define a window of time which the D input must
be valid and stable in order to assure valid data on the Q output.
Setup Time (Tsu) Setup time is the time that the D input must be valid before
the Flip-Flop samples.
Hold Time (Th) Hold time is the time that D input must be maintained valid
after the Flip-Flop samples.
Propagation Delay (Tpd) Propagation delay is the time that takes to the
sampled D input to propagate to the Q output.
CG-CoreEl
CG-CoreEl
FF1 FF2
Q1
Q2
CLOCKD
A LONG SLOW PATH
IN
CLK
Clock Skew
Synchronous systems using edge triggered flip-flops work
properly only if all flip-flops see the triggering edge at the
same time.
The difference between arrival times of the clock at different
devices is called clock skew.
CG-CoreEl
CG-CoreEl
Slack
At each node is a group of events modeling signal transitions
Arrival Time (AT) - when the signal arrives
AT
D Q
QB
RT
Required Time (RT) - when the signal is needed
SLEW
Slew (SLEW) - time for signal transition from logic levels
CG-CoreEl
CG-CoreEl
Slack
AT RT
SLEW
Q. Am I meeting timing at this node?
SLACK = RT - AT
+SLACK
Timing is met when slack is greater than or equal to zero
CG-CoreEl
CG-CoreEl
Maximum Operating Frequency
CG-CoreEl
CG-CoreEl
Recap
Shift registers: SISO, PISO, PIPO, SIPO
Shift register counters- ring counters and twisted
ring counters
Asynchronous/ synchronous counters
CG-CoreEl
CG-CoreEl
Counters
Clocked sequential circuit with single-cycle state
diagram
Modulo-m counter = divide-by-m counter
Most Common:
n-bit binary counter, where m = 2
n
n flip-flops, counts 0
2
n
-1
S3
S2
S1
Sm
CG-CoreEl
CG-CoreEl
Ripple Counter
Q
Q
T
Q
Q
T
Q
Q
T
Q
Q
T
CLK
Q0
Q1
Q2
Q3
1 bit
divide-by-2
2 bit
divide-by-4
3 bit
divide-by-8
4 bit
divide-by-16
Uses
Minimal
Logic!
CG-CoreEl
CG-CoreEl
Ripple Counter Timing
CLK
Q0
Q1
Q2
0 1 2 3 4
1A
2A
3A
CG-CoreEl
CG-CoreEl
CLK
Q0
Q1
Q2
7 Should be 0! 1 2
n - T
CQ
for MSB change for n-bit ripple counter => minimum clk period
1A
2A
3A
Ripple Counter Problem (Its Slow!)
CG-CoreEl
CG-CoreEl
Synchronous Counters
All clock inputs connected to common
CLK signal
So all flip-flop outputs change
simultaneously t
CQ
after CLK
Faster
More Complex Logic
Most Frequently Used Type of Counter
CG-CoreEl
CG-CoreEl
Synchronous Serial Counter
Flip-flops enabled
when all lower
flip-flops = 1.
Enable
propagates
serially limits
speed
Requires
(n-1) A t < T
CLK
All outputs
change
simultaneously
t
CQ
after CLK
>T
Q EN
CLK
CNTEN Q0
Q1
Q2
Q3
Q EN
>T
Q EN
>T
Q EN
>T
Equation?
Delay?
A t
A t
A t
CG-CoreEl
CG-CoreEl
Synchronous Parallel Counter
Single-level
enable logic per
flip-flop
Fastest and most
complex type of
counter
Requires A t <
T
CLK
All outputs
change
simultaneously
t
CQ
after CLK
>T
Q EN
>T
Q EN
>T
Q EN
>T
Q EN
CLK
CNTEN Q0
Q1
Q2
Q3
Equation?
Delay?
CG-CoreEl
CG-CoreEl
CLOCK
/S0
/S1
/S2
/S3
/S4
/S5
/S6
/S7
0
1
2
3
4
5
6
7
0
1
Decoded Modulo-8 Counter: Glitches!
More than 1 bit changes simultaneously
Glitches NOT a problem for synchronous inputs.
Glitches BAD for asynchronous inputs!
CG-CoreEl
CG-CoreEl
Solve these:
Q1: Design a JK counter that goes through the states
1,2,3,6,7,8,11,13,1, Implement the circuit and avoid loc-out
condition
Q2. Design a MOD 5 counter (divide by 5) counter using JK
flip-flop. Also construct the timing diagram. Also draw the
timing diagram of MOD 10 counter.
CG-CoreEl
CG-CoreEl
Solve these: contd
Q3. Design a asynchronous MOD 10 (decade) counter.
Q4. Design a non-sequential ripple counter, which will go
through the states 3,5,7,8,9,10,3,4,..
Q5. Determine f
max
for the 4-bit synchronous counter if t
pd
for each flip-flop is 50 ns and tpd for each AND gate is 20 ns.
Compare this with fmax for a MOD-16 ripple counter.
CG-CoreEl
CG-CoreEl
Interesting Problems:
Q1. Design a divide-by-3 counter with 50% duty cycle?
Question: Why in most of the designs only 50% duty cycle clocks
are used? Why can't we use a lesser duty cycle (less than 50%)
clock?
CG-CoreEl
CG-CoreEl
Q2. Design a divide-by 1.5 counter?
Q3. Design a black box whose input clock and
output relationship as shown in diagram
below.
Interesting Problems contd
CG-CoreEl
CG-CoreEl
Finite State Machines
CG-CoreEl
CG-CoreEl
Topics
FSM Basics
Types of Machines
Example Designs
CG-CoreEl
CG-CoreEl
Example
Assume a stream of 50k bits are given to the
circuit whose output Z=1 when no. of 1`s in
50k bits are odd else Z = 0. Design the circuit.
CG-CoreEl
CG-CoreEl
Finite state machines are so named because the
sequential logic that implements them can be in
only a fixed number of possible states.
FSM is a systematic way of specifying any
sequential logic.
Ideally suited for complex sequential logic.
Finite State Machines
CG-CoreEl
CG-CoreEl
What is an FSM?
Design Specification Point of View
State machines are a means of specifying
sequential circuits which are generally
complex in their transition sequence
and depend on several control inputs.
CG-CoreEl
CG-CoreEl
State machines are a group of flip-flops, whose
group-state transition pattern from one set of
values to another and depends on several
control inputs
What is an FSM?
Digital Circuit Point of View
CG-CoreEl
CG-CoreEl
CLOCK
ASYNC
CONTROL
CURRENT
STATE
CONTROL
INPUTS
NEXT
STATE
CURRENT
STATE
COMB.
LOGIC
for
NEXT
STATE
STATE
REGISTER
FLIP-FLOPS
PORTS
FSM Structure
COMBO. FOR
OUTPUT
OUTPUTS
MEALY
CG-CoreEl
CG-CoreEl
Mealy Machine
The outputs depend on the current state and
the present value of the inputs.
Mealy outputs are asynchronous and can
change in response to any changes in the
inputs, independent of the clock.
Glitches-How to avoid?
Require less no. of states compared to
Moore Machine.
CG-CoreEl
CG-CoreEl
Moore Machine
The outputs depend only on the present
state.
The outputs are computed by a
combinational logic block whose only
inputs are the flip-flops' state outputs
The outputs change synchronously with the
state transition and the clock edge.
CG-CoreEl
CG-CoreEl
Finite state machine
FSM Structure:-
. State register
- Stores current state
. Next state decoder logic (A)
- Decides next state based on
current state and inputs
. Output logic (B)
-Decodes state (or states and
inputs) to produce outputs
.Outputs from the FSM can be a
function of:
- Current state only (moore)
- Current state and the current
inputs (Mealy)
A
B
A
B
c1k
c1k Moore FSM
Mealy FSM
CG-CoreEl
CG-CoreEl
FSM Design examples
Q1. Design a circuit that asserts its single output
whenever its input string has two 1's in
sequence.
Cases:
(i) Non-overlapping
(ii) Overlapping of sequence
CG-CoreEl
CG-CoreEl
Q2. Assume a stream of 50k bits are given to the
circuit whose output Z=1 when no. of 1`s in
50k bits are odd else Z = 0. Design the
circuit. (using Mealy machine)
FSM Design examples
CG-CoreEl
CG-CoreEl
Q3. Design a circuit to detect a sequence 010
(i) non-overlapping
(ii) overlapping
using Mealy machine.
FSM Design examples
CG-CoreEl
CG-CoreEl
FSM design example
Design a circuit to detect a sequence 1010
(i) non-overlapping
(ii) overlapping
using Mealy machine.
CG-CoreEl
CG-CoreEl
FSM design example
Design a circuit to detect a overlapping
sequence 101
using
(1) Mealy machine.
(2) Moore machine
And compare the two designs
CG-CoreEl
CG-CoreEl
Q4. A sequential circuit accepts two i/p`s X & Y
and generates an o/p Z = 1 whenever the i/p`s
are equal & same in the present as well as
previous clock cycle. Design a Mealy
machine.
Note: If any state machine has n inputs, no.
of arrows leaving the state will be 2
n
.
FSM Design examples
CG-CoreEl
CG-CoreEl
FSM design example
A sequential circuit has one input (X) and one
output (Z).The circuit examines groups of 4
consecutive inputs and produces an output
Z=1 if the input sequence 0101 or 1001
occurs. The circuit resets after every 4 inputs.
Find the Mealy state graph.
Ex: X= 0101 | 0010 | 1001 | 0100
Z= 0001 | 0000 | 0001 | 0000
CG-CoreEl
CG-CoreEl
Q5.Design a Moore finite state recognizer that
has one input (X) and one output (Z). The
output is asserted whenever the input
sequence 010 has been observed, as long
as the sequence 100 has never been
seen.(Overlapping)
FSM Design examples
CG-CoreEl
CG-CoreEl
Q6. A sequential circuit has one I/p and one
o/p. when I/p sequence 110 occurs the o/p
becomes 1 and remains 1 until the sequence
110 occurs in which case the o/p returns
to zero. The output remains zero until 110
occurs the third time. Draw the state
diagram and state table.
FSM Design examples
CG-CoreEl
CG-CoreEl
Q7. State diagram of a transmitter is shown below.
Sketch the state diagram for the receiver.
Tx
Rx
X
X
Y
Y
0 1
1/0
0/0
0/1
1/1
Tx
Rx
??
FSM Design examples
CG-CoreEl
CG-CoreEl
Problems, more
problems
Design a pulse train generator circuit using
shift register for the following pulse train:
1 0 0 0 1 1 0
Next Question: Now can you design a circuit
to generate a specified waveform.
CG-CoreEl
CG-CoreEl
Introduction to Memories
CG-CoreEl
CG-CoreEl
Classification
MEMORY
RAM
HYBRID
ROM
SRAM
DRAM
FLASH
EEPROM
PROM
EPROM
MASKED
CG-CoreEl
CG-CoreEl
Memory array architecture
CG-CoreEl
CG-CoreEl
Latch and Register based Memory
CG-CoreEl
CG-CoreEl
CG-CoreEl
CG-CoreEl
RAM
Types : SRAM& DRAM
Primary difference: lifetime of the data they
store.
Which to choose & on what basis?
Speed, Area & Cost.
CG-CoreEl
CG-CoreEl
CG-CoreEl
CG-CoreEl
Types : MASKED, PROM& EPROM
They are class of PLD s.
Distinguished by the methods used to write new
data to them (usually called programming) and
the number of times they can be rewritten.
ROM
CG-CoreEl
CG-CoreEl
MASKED : Programmed by manufacturer.
PROM: One time programmable.
EROM: Erased & re-programmable again & again.
ROM
CG-CoreEl
CG-CoreEl
PLD s
CG-CoreEl
CG-CoreEl
ROM
CG-CoreEl
CG-CoreEl
ROM
CG-CoreEl
CG-CoreEl
Exercise on PLAs
Design a full adder using PLA
Design a Binary to Gray code converter
using PLA
It is desired to generate the following 3
Boolean functions:
F1=abc+abc+bc
F2=abc+bc+abc
F3=abc+abc+ac
CG-CoreEl
CG-CoreEl
BY using OR gate array write down the terms
p1,p2,p3,p4 and p5
p1 *
p2 * *
p3 *
P4 *
p5 *
f1 f2 f3
CG-CoreEl
CG-CoreEl
CG-CoreEl
CG-CoreEl
CG-CoreEl
CG-CoreEl
HYBRID
Combine features of both
EEPROM: Once written, the new data will remain
in the device forever--or at least until it is
electrically erased.
FLASH: The major difference is that flash devices
can only be erased one sector at a time, not byte-
by-byte as in EEPROM.
CG-CoreEl
CG-CoreEl
CG-CoreEl
CG-CoreEl
Comparison: memories
Type Volatile Writeable Erase Size Cost(per Byte) Speed
SRAM Yes Yes Byte Expensive Fast
DRAM Yes Yes Byte Moderate Moderate
RAM No No N/A Inexpensive Fast
PROM No Only once N/A Moderate Fast
EPROM No Yes Entire Chip Moderate Fast
EEPROM No Yes Byte Expensive Fast
FLASH No Yes Sector Moderate Fast
CG-CoreEl
CG-CoreEl
Problems
Expanding word size, capacity and both
Store 16 8 bit words using 16x4 RAMs
Obtain 1Kx8 module using 1Kx1 RAMs
Store 32 4 bit words using 16x4 chips
Obtain 8Kx8 ROM using 2Kx8 ROMs
Obtain 4Kx8 ROM using 1Kx4 ROMs
CG-CoreEl
CG-CoreEl
CG-CoreEl
CG-CoreEl
CG-CoreEl
CG-CoreEl
CG-CoreEl
CG-CoreEl
CG-CoreEl
CG-CoreEl
CG-CoreEl
CG-CoreEl
CG-CoreEl
CG-CoreEl
CG-CoreEl
CG-CoreEl
CG-CoreEl
CG-CoreEl
CG-CoreEl
CG-CoreEl
Introduction to
STATIC TIMING ANALYSIS
CG-CoreEl
CG-CoreEl
Concepts Covered
Introduction to STA
Timing Paths
Skew
Problems
Clock & Timing Constraints
Exceptional Paths
Multicycle relations with multiple clocks
CG-CoreEl
CG-CoreEl
STA is an exhaustive method of analyzing, debugging and
validating the timing performance of a design.
STA What is Static Timing Analysis?
Advantages:
Much faster than timing-driven, gate-level
simulation.
Exhaustive
Vector generation NOT required.
CG-CoreEl
CG-CoreEl
Setup Requirement
Hold Requirement
What are our circuit timing
requirements?
Clk
100 200 300 400 500 0
Data
Data Cannot
Change Within
These Windows
Data
Clk
D Q
QB
Output
OutputBar
CG-CoreEl
CG-CoreEl
Setup Requirement
Hold Requirement
Clk
100 200 300 400 500 0
Data
Clk
100 0
Data
Early
Required Time
Late
Required Time
CG-CoreEl
CG-CoreEl
Limitations of STA
Multiple clocks
False paths: Proper circuit functionality is not checked
Latches
Multicycle paths
Works best with synchronous (not asynchronous)
logic
Complex to learn
Must define timing requirements / exceptions
Difficulty in handling:
CG-CoreEl
CG-CoreEl
What is Dynamic Timing Analysis?
Advantage:
Can be very accurate (spice-level)
Disadvantages:
Analysis quality depends on stimulus vectors
Non-exhaustive, slow
CG-CoreEl
CG-CoreEl
STA in ASIC Design Flow Pre layout
Logic Synthesis
Design For test
Floor planning
Constraints
(clocks, input drive,
output load)
Static Timing Analysis
(estimated parasitics)
CG-CoreEl
CG-CoreEl
STA in ASIC Design Flow Post
Layout
Floor planning
Clock Tree Synthesis
Place and Route
Parasitic Extraction
SDF
(extracted parasitics)
Constraints
(clocks, input drive,
output load)
(estimated parasitics)
(extracted parasitics)
CG-CoreEl
CG-CoreEl
Wire Load Model
CG-CoreEl
CG-CoreEl
Timing Graphs
CG-CoreEl
CG-CoreEl
STA - Timing Graph Introduction
Data
Clk
D Q
QB
Output
OutputBar
A node exists for every
Model pin 4
Cell Pin 8
Bottom
Top
Hierarchical pin 2
14
Q. How many nodes are in our design?
Node: where timing information is stored on the design
CG-CoreEl
CG-CoreEl
STA - Node Types
Data
Clk
D Q
QB
Output
OutputBar
Top
Clock Nodes
All nodes along clock path
Created from force clock constraints
Data Nodes
CG-CoreEl
CG-CoreEl
STA - Events
At each node is a group of events modeling
signal transitions
Arrival Time (AT) - when the signal arrives
AT
D Q
QB
RT
Required Time (RT) - when the signal is needed
SLEW
Slew (SLEW) - time for signal transition from logic levels
CG-CoreEl
CG-CoreEl
STA - Meeting Timing
AT RT
SLEW
Q. Am I meeting timing at this node?
SLACK = RT - AT
+SLACK
Timing is met when slack is greater than or equal to
zero
CG-CoreEl
CG-CoreEl
STA - Meeting Timing
AT
RT
Q. Am I meeting late mode timing at this node?
SLACK = RT - AT
+SLACK
No, the falling edge slack is negative...
AT
RT
-SLACK
HINT: RT should always be after AT
CG-CoreEl
CG-CoreEl
STA - Levels
Q. How many levels of logic are in this design?
1
Q. How many timing levels are in this design?
HINT: Determine the nodes first
2
3
4
1 2
3
5
7
8
9
10
6
HINT: Timing Levels = 2 * Logic Levels + 2
4
CG-CoreEl
CG-CoreEl
1.0
1.0
1.0
1.0
1.0
STA - Calculating AT
STEP 1 : Calculate timing level for each node
8
10
7
9
6
1
1
1
1
1
2
2
2
2
2
3
3
9
5
5
4
4
4
STEP 2 : Calculate AT from level 1 to level n
Simplifying assumptions:
Input arrival time of 1
Wire delay 0.2 ; gate delay 0.5
3.8
1.2
1.2
1.2
1.2
1.2
3.3
4.0
1.7
1.7
3.1
1.9
1.9
1.9
2.4
2.4
2.6
2.6
CG-CoreEl
CG-CoreEl
1.0
1.0
1.0
1.0
1.0
STA - Calculating RT
STEP: Calculate RT from level n to level 1
8
10
7
9
6
1
1
1
1
1
2
2
2
2
2
3
3
9
5
5
4
4
4
3.8
1.2
1.2
1.2
1.2
1.2
3.3
4.0
1.7
1.7
3.1
1.9
1.9
1.9
2.4
2.4
2.6
2.6
Simplifying assumptions:
One number for rise and fall
Output required time of 2.8
Wire delay 0.2 ; gate delay 0.5
2.8
2.6
2.1
1.9
2.1
1.4
-0.2
1.2
0.5
-0.2
0.5
0.5
1.2
1.4
0.7
1.4
1.9
1.2
0.7
0.7
0.0
1.4
0.0
CG-CoreEl
CG-CoreEl
1.0
1.0
1.0
1.0
1.0
STA - Calculating Slack
8
10
7
9
6
1
1
1
1
1
2
2
2
2
2
3
3
9
5
5
4
4
4
3.8
1.2
1.2
1.2
1.2
1.2
3.3
4.0
1.7
1.7
3.1
1.9
1.9
1.9
2.4
2.4
2.6
2.6
2.6
2.1
1.9
2.1
1.4
-0.2
1.2
0.5
-0.2
0.5
0.5
1.2
1.4
0.7
1.4
1.9
1.2
0.7
0.7
0.0
1.4
0.0
SLACK = RT - AT
Q: What is the formula for late mode slack?
-0.5
-1.2
0.2
-0.5
-1.2
-1.2
-0.5
-1.2
-1.2
-1.2
-1.2
-1.2
-0.5
-0.5
-1.2
-0.5
-1.2
-0.5
-0.5
-1.2
-1.2
-0.5
0.2
2.8
Slack is calculated on an as needed basis
CG-CoreEl
CG-CoreEl
What Does Register Bound Mean ?
D Q
QB
D Q
QB
D Q
QB
D Q
QB
Register bound implies that the combinational logic is
bounded by registers on the inputs and the outputs.
Combinational logic is represented by a symbolic blob.
CG-CoreEl
CG-CoreEl
STA Introduction Summary
Basics (setup, hold)
Timing Graph (Clock nodes, Data nodes)
Event description (RT, AT, slew)
Timing information for a design is stored on nodes
At each node a group of events models signal
transitions.
Slack expresses the relationship between signal
arrival time and required time at a node.
Specifying the clocks constraints all register-to-
register (register-bound) paths.
CG-CoreEl
CG-CoreEl
Basic Terminologies
CG-CoreEl
CG-CoreEl
Concepts Covered
Minimum clock
period
Hold constraint
Clock skew
Clock latency
Clock jitter
Setup time
Hold time
Clock-to-Q time
Cause and effect of
timing violations
Critical path
False path
Multicycle path
Specifying clocks
Ideal and computed
clocks
Generated clocks
CG-CoreEl
CG-CoreEl
Basic Terminologies
Critical path: The slowest path on the chip
between flops or flops and pins. The critical
path limits the maximum clock speed.
CG-CoreEl
CG-CoreEl
Setup time:
The amount of time the synchronous input
must be stable before the active edge of clock.
Hold time:
The amount of time the synchronous input
must be stable after the active edge of clock.
Basic Terminologies
CG-CoreEl
CG-CoreEl
Recovery time: It is the time available between the
asynchronous signal going inactive to the active clock
edge.
Removal time: It is the time between active clock edge
and asynchronous signal going inactive.
Recovery time:
Like setup time for asynchronous port (set, reset)
Removal time:
Like hold time for asynchronous port (set, reset)
Basic Terminologies
CG-CoreEl
CG-CoreEl
Three Steps in Static Timing Analysis
Circuit is broken down into sets of timing
paths.
Delay of each path is calculated.
Path delays are checked to see if timing
constraints have been met.
CG-CoreEl
CG-CoreEl
What is a Timing Path?
A Timing Path is a point-to-point path in a
design which can propagate data from one flip-
flop to another.
Each path has a startpoint and an endpoint
Startpoints:
Input ports, Clock pins of flip-flops
Endpoints:
Output ports, Data input pins of flip-flops
CG-CoreEl
CG-CoreEl
Types of Timing Paths
CG-CoreEl
CG-CoreEl
Organizing Timing Paths Into Groups
Timing paths are grouped into path groups by the
clocks controlling their endpoints.
Synthesis tools like Prime Time and Design
Compiler organize timing reports by path groups.
CG-CoreEl
CG-CoreEl
Critical path??
CG-CoreEl
CG-CoreEl
Critical path??
CG-CoreEl
CG-CoreEl
Basic Terminologies
Maximum Clock Frequency/ Minimum Clock
Period
The clock frequency for a synchronous
sequential circuit is limited by the timing
parameters of its flip-flops and gates. This limit
is called the maximum clock frequency for the
circuit. The minimum clock period is the
reciprocal of this frequency.
CG-CoreEl
CG-CoreEl
Condition for Hold time
To satisfy hold time: Tc2q + Tpd (minimum) > Thold
D Q
QB
D Q
QB
clkbar
CG-CoreEl
CG-CoreEl
CG-CoreEl
CG-CoreEl
D Q Combinational
logic
D Q
CLK
t
ffpd
t
comb
t
setup
& t
hold
t
ffpd
- CLK to Q, FF propagation delay (min, max)
t
comb
- combinational logic dely (min, max)
t
setup
- input stable before clock (min)
t
hold
- input stable after clock (min)
JAL
Synchronous System -
Detailed Timing
CG-CoreEl
CG-CoreEl
Example Timing Violations: Good Timing
CG-CoreEl
CG-CoreEl
Required: t
clk,min
> t
ffpd,max
+ t
comb,max
+ t
setup,min
Difference = Setup time margin
>= 0 for guaranteed operation
Required: t
ffpd, min
+ t
comb,min
> t
hold,min
Difference = Hold time margin
>= 0 for guaranteed operation
Synchronous System - Detailed Timing
CG-CoreEl
CG-CoreEl
t
comb
= 2 ns, min and 20 ns, max t
ffpd
= 3 ns, min and 15 ns, max
t
setup
= 5 ns, min
t
hold
= 2 ns, min
Setup margin @ 10 MHz clk?
Max Frequency?
Hold Margin?
Combinational
logic
State
Register
Q3
Q2
Q1
in1
in2
JAL
Synchronous System Example
CG-CoreEl
CG-CoreEl
t
comb
= 2 ns, min and 20 ns, max t
ffpd
= 3 ns, min and 15 ns, max
t
setup
= 5 ns, min
t
hold
= 2 ns, min
Setup margin @ 10 MHz clk? 100 - (15 + 20 +5) = 60 ns
Max Frequency? t
clk,min
>= 40 ns, so f
max
<= 25 MHz
Hold Margin? (3 + 2) -2 = 3ns
Combinational
logic
State
Register
Q3
Q2
Q1
in1
in2
Synchronous System Example
CG-CoreEl
CG-CoreEl
74LS74 Data Sheet Timing
Parameter Min Max Units
t
W
Pulse Width - Clock High 18 ns
- Preset Low 15 ns
- Clear Low 15 ns
t
SU
Setup Time 20 ns
t
H
Hold Time 0 ns
f
MAX
Max Clock Frequency 20 MHz
t
PLH
Prop Delay, Clock-to-Q 35 ns
t
PLH
Prop Delay, Preset-to-Q 35 ns
t
PLH
Prop Delay, Clear-to-Q 35 ns
CG-CoreEl
CG-CoreEl
Functional Timing Diagram
Shows no delays, so all edges line up
Shows what happens each clock, ignoring exact
delays
Illustrates operation, but does not specify upper and
lower limits
INSUFFICIENT information for a REAL system design
Clock
Sig1
Sig2
CG-CoreEl
CG-CoreEl
t
H
t
L
Clock
t
ffpd
flip-flop
outputs
combinational
outputs
t
comb
t
clk
setup-time
margin t
setup
t
hold
flip-flop
inputs
CG-CoreEl
CG-CoreEl
Example Timing Violations: Setup Violation
CG-CoreEl
CG-CoreEl
Example Timing Violations: Hold Violation
CG-CoreEl
CG-CoreEl
Clock Skew
Clock Skew: The maximum difference in arrival time of the
clock signal to each register in the design
clock
Clock arrival
time at 1.1ns
Clock arrival
time at 1.3ns
Skew = 1.3ns - 1.1ns = .2ns
CG-CoreEl
CG-CoreEl
Absolute Clock Skew A Definition
Your chip
clock input
Flip
Flop
Time from clock input (at pin) to
clock input at a given flip flop
CG-CoreEl
CG-CoreEl
Relative Clock Skew
Your chip
clock input
Flip
Flop
Time between 2 flip flops receiving
the clock signal
Flip
Flop
CG-CoreEl
CG-CoreEl
Failure / Data loss Due To Large
Skew
Combinational
Logic
Flip
Flop
Flip
Flop
o delay
clk
B
Aout Ain
A
Bin
If new data (Ain) gets to point
Bin before clock does, system
will fail by simply skipping over
old data
For this illustration - ignore t
setup
CG-CoreEl
CG-CoreEl
Combinational
Logic
Flip
Flop
Flip
Flop
o delay
clk
B
Aout Ain
A
Bin
Clock arrives at point A
T = 0ns
CG-CoreEl
CG-CoreEl
Data arrives at combo logic input
Combinational
Logic
Flip
Flop
Flip
Flop
o delay
clk
B
Ain
A
Bin
Aout
T = t
clk-to-Q
CG-CoreEl
CG-CoreEl
Data Exits Comb Logic
Combinational
Logic
Flip
Flop
Flip
Flop
o delay
clk
B
Ain
A
Aout
new
Bin
Bin
T = t
clk-to-Q
+ t
logic
CG-CoreEl
CG-CoreEl
Clock Reaches B
Combinational
Logic
Flip
Flop
Flip
Flop
clk
B
Ain
A
Aout
new
Bin
Bin
o delay
T = t
clk-to-Q
+ t
logic
T
skew
= t
o
CG-CoreEl
CG-CoreEl
Failure!!!
Combinational
Logic
Flip
Flop
Flip
Flop
clk
B
Ain
A
Aout
new
Bin
Bin
o delay
New
Bin
What happened to old Bin???
If t
clk-to-Q
+t
logic
< t
o
it fails
CG-CoreEl
CG-CoreEl
Clock Jitter
jitter
clock
CG-CoreEl
CG-CoreEl
Clock jitter is caused by:
temperature and voltage variations over time
temperature and voltage variations across different locations on a chip
manufacturing variations between different parts
etc.
Clock Jitter
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CG-CoreEl
More on Skew
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CG-CoreEl
Positive & Negative Skew
R1
In
(a) Positive skew
Combinational
Logic
D Q
t
CLK1
CLK
delay
t
CLK2
R2
D Q
Combinational
Logic
t
CLK3
R3

D Q
delay
R1
In
(b) Negative skew
Combinational
Logic
D Q
t
CLK1
delay
t
CLK2
R2
D Q
Combinational
Logic
t
CLK3
R3

D Q
delay CLK
CG-CoreEl
CG-CoreEl
Positive Skew

CLK1
CLK2
T
CLK
o
T
CLK
+ o
+
t
h
o
2
1
4
3
R1
In
Combinational
Logic
D Q
t
CLK1
CLK
delay
t
CLK2
R2
D Q
Combinational
Logic
t
CLK3
R3

D Q
delay
CG-CoreEl
CG-CoreEl
Negative Skew

CLK1
CLK2
T
CLK
o
T
CLK
-
o
2
1
4
3
R1
In
Combinational
Logic
D Q
t
CLK1
delay
t
CLK2
R2
D Q
Combinational
Logic
t
CLK3
R3

D Q
delay CLK
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CG-CoreEl
Example Timing Violations: Minimum Clock Period
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CG-CoreEl
Example Timing Violations: Hold Constraint
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CG-CoreEl
Analysis of Timing Report
#### Path 1 ############################################
Start rp.PC.outreg_reg[0]/Q
End rp.PC.outreg_reg[15]/D
Reference rp.PC.outreg_reg[15]/CK
Path slack 1p
Reference arrival time 704
+ Cycle adjust (clock:R#1 vs. clock:R#2) 13000
- Margin -100
- Setup time -646
---------------------------------------- -----
End-of-path required time (ps) 12957
Starting arrival time 0
+ Clock path delay 704
+ Data path delay 12252
---------------------------------------- -----
End-of-path arrival time (ps) 12956
Starting and ending points
Slack
time = 0
starting and
reference edge
arrival time
data
slack = required time - arrival time
clock period
data arrival
time
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CG-CoreEl
A Timing Example:
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CG-CoreEl
Example 1
D Q
Q
CK
Q
T
W
max t
PFF
+ t
su
For the 7474, max t
PLH
= 25ns, max t
PHL
= 40ns, t
su
= 20ns
T
W
max (max t
PLH
+ t
su,
max t
PHL
+ t
su)
T
W
max (25+20, 40+20) = 60
CG-CoreEl
CG-CoreEl
D Q
CK
Q
T
W
max t
PFF
+ max t
PINV
+ t
su
Example 2
CG-CoreEl
CG-CoreEl
D Q
Q
D Q
Q
MUX
0
1
Q0 Q1
CK
T
W
max t
PFF
+ max t
PMUX
+ t
su
Example 3
CG-CoreEl
CG-CoreEl
Paths from Q1 to Q1:
None
T
W
max t
PDFF
+t
JKsu
= 20 +10 = 30 ns
T
W
max t
PDFF
+ max t
AND
+ t
JKsu
= 20 + 12 + 10 = 42 ns
T
W
max t
PJKFF
+ t
OR
+ T
Dsu
= 25 + 10 + 5 = 40 ns
T
W
max t
PJKFF
+ max t
AND
+ t
JKsu
= 25 + 12 + 10 = 47
TW 47 ns
Example 4
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CG-CoreEl
Example 5 : Effect of clock skew on clock rate
Q1
Q2
D Q
Q
D Q
Q
CK
C1
C2
D2
T
W
max T
PFF
+ max t
OR
+ t
su
(if clock not skewed, i.e., t
INV
= 0)
T
W
max T
PFF
+ max t
OR
+ t
su
- min t
INV
(if clock skewed, i.e., t
INV
> 0)
Clock C2 skewed after C1
CG-CoreEl
CG-CoreEl
Example 6: Maximum Allowable Clock Skew
How much skew between C1 and C2 can be tolerated in the
following circuit?
Case 1: C2 delayed after C1
D Q
Q
D Q
Q
C2
Q1
D2
C1
t
PFF
> t
h
+ t
SK
t
SK
< min t
PFF
- t
h
CG-CoreEl
CG-CoreEl
Case 2: C1 delayed from C2
D Q
Q
D Q
Q
C2
Q1
D2
C1
CG-CoreEl
CG-CoreEl
How does additional delay between the flip-flops affect the
skew calculations?
t
SK
min t
PFF
- t
h
t
sk
min t
PFF
+ min t
MUX
- t
h
Example 7
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CG-CoreEl
Understanding
And
Describing Clocks
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CG-CoreEl
Defining Clocks
A clock is defined by its period, waveform and slew time.
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CG-CoreEl
Specifying Clocks
Standard clock
Inverted clock
Virtual clock
Derived clock
Gated clock
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CG-CoreEl
Blast Fusion(MAGMA) clock command:
force timing clock node period slew time
-waveform {-rise R fall F } virtual name name
Equivalent SDC command:
create_clock period waveform name name
Example syntax:
force timing clock $m/clk 10n
Q. Why aren`t we using waveform option?
A. The default waveform start at 0 with a 50% duty cycle.
Standard Clock Specification
0 5 10
clk
D Q
QB
D Q
QB
clk
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CG-CoreEl
create_clock -period 20 -waveform {0 8}
create_clock -period 20 waveform {10 18}
Standard Clock Specification
SDC commands
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CG-CoreEl
Inverted Clock
Blast Fusion clock command
force timing clock $m/clkbar 5n
Q. What is an inverted clock with a 10/50 duty cycle shifted by 2ns ?
-waveform {-fall 2n rise 3n}
D Q
QB
D Q
QB
clkbar
0 1 2 3 4 5 6
clk
clkbar
0 1 2 3 4 5 6
clkbar
0 1 2 3 4 5 6
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CG-CoreEl
Virtual Clock
A virtual clock has no sources. It exists in memory but is not part of
a design. A virtual clock lets you associate arrival and required
times with clocks external to the chip or block.
The name of virtual clock must be a unique name that is not
associated with any port or instance in the synthesized design.
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CG-CoreEl
Generated Clock
clk
D Q
QB
D Q
QB
D Q
QB
force timing clock $m/clk 5n
force timing clock $m/f0/Q generated source $m/clk divider 2
f0
D Q
QB
A design might include clock dividers or other
structures that produce a new clock from a
master source clock.
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CG-CoreEl
Gated Clock
CLOCK
CLKEN
GCLK
CLOCK
CLKEN
CGLK
Clock gating reduces power consumption by switching off
the clock to flip-flops when the value of those flip-flops does
not change.
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CG-CoreEl
Gated Clock: Setup and Hold Margins for
AND & NAND gates
The setup margin is measured relative to the falling transition of
the gating cell clock input.
The hold margin is measured relative to the rising transition of
the clock input.
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CG-CoreEl
Gated Clock: Setup and Hold Margins for OR &
NOR gates
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CG-CoreEl
Describing Clock Variations
Clock latency (delay)
Clock skew
Jitter
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CG-CoreEl
Source, Network and IO
Latency
Chip
D Q
D Q D Q
D Q
network latency
(on-chip)
source latency
(off-chip)
Clock
IO
latency
IO
latency
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CG-CoreEl
Source, Network and IO
Latency
CG-CoreEl
CG-CoreEl
Clock Generation
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CG-CoreEl
CG-CoreEl
CG-CoreEl
Summary: Clocks
A clock is defined by its period, waveform and
slew time
Clock variations that can be described for timing
calculation include latency, skew and jitter.
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CG-CoreEl
False Paths
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CG-CoreEl
What are False paths?
Paths that physically exist in a design but are not
logic/functional paths
These paths never get sensitized under any input
conditions
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CG-CoreEl
Logically Impossible Example
Mux 1
C C1 C2 A
B
Mux 2
S
B1 B2
OUT
A path may exist in the circuit but no combination of
input vectors may ever exercise it
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CG-CoreEl
Logic Removal Example
A block may be reused and certain signal functions are
no longer required
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CG-CoreEl
Most STA`s can`t leave combinational loops in the
design, because a race condition will occur
"I want to break the
combinational loop at
U1/B"
force timing break -from $m/U1/B -to $m/U1/Z
D Q
QB
D Q
QB
A
B
Z
U0
A
B
Z
U1
broken arc
Combinational Loop Example
CG-CoreEl
CG-CoreEl
Multicycle Path
A start point, end point and/or "through" point is
specified, along with the number of allowed clock
cycles.
Multicycle paths are paths which intentionally
require more than one clock cycle to propagate.
This information cannot possibly be inferred by the
timing analyzer, so it must be specified by the
designer so the analyzer can mark the path and
correctly compute the timing.
CG-CoreEl
CG-CoreEl
D Q
QB
D Q
QB
CK
U1 U2
force timing multicycle -from $m/U1/Q -to $m/U2/D -cycle 2
Multicycle Path: Example
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CG-CoreEl
Handling Multiple Clocks
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CG-CoreEl
Multiple Clocks
Step1: Determine the Least Common Multiple (LCM)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
A
(6 ns)
B
(8 ns)
What is the LCM between these two clocks?
The timer needs to calculate the delays of the
circuit to the LCM to find all path relationships
CG-CoreEl
CG-CoreEl
Setup Relationship: A Rising, B Rising
Find the Setup Relationship between A rising and B rising
The setup relationship is the closest distance between the launching
clock edge (A) and the receiving clock edge (B)
D Q
QB
D Q
QB
CG-CoreEl
CG-CoreEl
Setup Relationship: A Rising, B Falling
Find the Setup Relationship between A rising and B falling
D Q
QB
D Q
QB
CG-CoreEl
CG-CoreEl
Setup Relationship: A Falling, B Rising
Find the Setup Relationship between A falling and B rising
D Q
QB
D Q
QB
CG-CoreEl
CG-CoreEl
Setup Relationship: A Falling, B Falling
Find the Setup Relationship between A falling and B falling
D Q
QB
D Q
QB
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CG-CoreEl
Hold Relationship: A Rising, B Rising
Find the Hold Relationship between A rising and B rising
The hold relationship is the closest distance between the
launching clock edge (A) and the previous receiving clock
edge (B)
D Q
QB
D Q
QB
CG-CoreEl
CG-CoreEl
Hold Relationship: A Rising, B Falling
Find the Hold Relationship between A rising and B falling
D Q
QB
D Q
QB
CG-CoreEl
CG-CoreEl
Hold Relationship: A Falling, B Rising
Find the hold Relationship between A falling and B rising
D Q
QB
D Q
QB
CG-CoreEl
CG-CoreEl
Hold Relationship: A Falling, B Falling
Find the hold Relationship between A falling and B falling
D Q
QB
D Q
QB
CG-CoreEl
CG-CoreEl
Pipelining Concept
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CG-CoreEl
Pipelining
Concept
CG-CoreEl
CG-CoreEl
Anatomy of a Pipeline Stage
Combinational
Logic
T
clock-to-Q
T
logic
T
setup
Flip
Flop
|
Flip
Flop
|
One clock cycle
setup logic Q to clock cycle
T T T T + + =

CG-CoreEl
CG-CoreEl
Anatomy of a Synchronous System
Comb
Logic
Flip
Flop
|
Flip
Flop
|
Comb
Logic
Flip
Flop
|
Comb
Logic
input input input
Overall system cycle time
determined by longest pipeline stage (taking
input arrival times into account)
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CG-CoreEl
Latency in Pipelines
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CG-CoreEl
Pipelining Example
Original circuit
Two logic levels between SOURCE_FFS and
DEST_FF
f
MAX
= ~207 MHz
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CG-CoreEl
Pipelined circuit
One logic level between each set of flip-flops
f
MAX
= ~347 MHz
Pipelining Examplecontd
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CG-CoreEl
Review Question
Given the original circuit, what is wrong with
the pipelined circuit?
How can the problem be corrected?
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CG-CoreEl
Retiming Concept
Register balancing in order to balance the timing
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CG-CoreEl
Time Borrowing
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TIME BORROWING
* Time borrowing occurs in latch-based designs
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CG-CoreEl
TIME BORROWINGcontd
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CG-CoreEl
There is a short delay on the first timing path and a
long delay on the second timing path.
The question is whether time borrowing can
eliminate negative slack
TIME BORROWINGcontd
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CG-CoreEl
GLUE LOGIC
CG-CoreEl
CG-CoreEl
AVOID GLUE LOGIC
THE NAND GATE AT THE TOP LEVEL SERVERS ONLY
TO GLUE THE INSTATIATED CELLS
OPTIMIZATION IS LIMITED BECAUSE THE GLUE
LOGIC CANNOT BE ABSORBED
X
clock
RegA
X
clock
RegB
X
clock
RegA
GLUE
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CG-CoreEl
REMOVE GLUE LOGIC BETWEEN BLOCKS
THE GLUE LOGIC CAN NOW BE OPTIMIZED WITH
OTHER LOGIC
TOP LEVEL DESIGN IS ONLY A STRUCTURAL
NETLIST, DOESNT NEED TO BE COMPILED
X
clock
RegA
X
clock
RegB
X+GLUE
clock
RegA
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CG-CoreEl
Signal Interface
CG-CoreEl
CG-CoreEl
Signal Interface: Model
CG-CoreEl
CG-CoreEl
Interface Taxonomy (Parallelism)
CG-CoreEl
CG-CoreEl
Interface Taxonomy (Topology)
CG-CoreEl
CG-CoreEl
Interface Taxonomy (Timing)
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CG-CoreEl
Interface Taxonomy (Signaling)

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CG-CoreEl

Sandeepani School of VLSI Design

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