A

MINOR PRO1ECT REPORT

I n partial IulIillmentoI the requirements Ior the award oI
Bachelor oI Technology Degree in
ELECTRONICS & COMMUNICATION ENGINERING






Submitted To: Submitted By:
r.Vikas Sharma Ajay Sharma (3908214)
Head oI deptt. Darshan (3908213)
.I.E.T. Suraj (3908221)


KURUKSHETRA UNIVERSITY KURUKSHETRA
KURUKSHETRA

ACKNOWLEDGEMENT

e take this opportunity as a privilege to thank all individuals without whose support an
guidance we could not have completed our project in this stipulated period oI time.First and
Ioremost we would like to express our deepest gratitude to our Project Supervisor
Er.ManpreetKaur,( Department of Electronics and Communication Engineering), Ior his
invaluable support, guidance , motivation and encouragement throughout the period this
work was carried out .

e are also grateIul toMr.Vikas Sharma (HOD) Ior their valued suggestions and inputs during
the course oI the project work. His readiness Ior advice at all times, his educative comments and
inputs, his concern and assistance even with practical things have been extremely helpIul

e would also like to thank all Lecturers, and members of the Department of (ECE) Ior
their generous help in various ways Ior the completion oI the Project.



Ajay Sharma (3908214)
Darshan (3908213)
Suraj (3908221)















CERTIFICATE


This is to certiIy that the Project entitled 'Serial Communication using UART submitted
byAjaySharma,Darshan&Suraj in partial IulIillment oI the requirements Ior the award oI
Bachelor oI Technology Degree in Electronics andCommunication Engineering at
ModernInstituteofEngineeringTechnology (KURUKSHETRAUNIV.KURUKSHETRA)
is an authentic work carried out by them under my supervision and guidance.
To the best oI my knowledge, the matter embodied in the Project has not been submitted to any
other University/Institute Ior the award oI any Degree or Diploma.




r.VikasSharma(H.O.D)

Department oI E.C.E




























PREFACE

The aim oI Project is to designing UART with VHDL language Ior Serial Transmission oI data.
VHDL is a hardware description language that can be used to model a digital system.
Chapter 1 describes the Iundamental oI VHDL language & type oI representation.
Chapter 2 describe the UART
Chapter3 describe the tx,rx.,baud gen.
Chapter4 describe simulation
e are thankIul to our HOD & all teachers Ior continuous support with us.

Ajay Sharma
Darshan
Suraj
























CONTENT
CHAPTER 1:Fundamental OI VHDL
1.1Introduction to VHDL
1.2Type oI represention
1.3VHDL Programing structure
1.4examples
CHAPTER 2:Introduction To UART
2.1 UART
2.2 Serial Vs. Parallel
2.3 Synchronous Serial Transmission
2.4 A synchronous Serial Transmission
2.5 Baud,Bits& Symbol
2.6 Asynchronous serial reception
2.7 Other UART Iunction
CHAPTER-3:UART ODEL
3.1 UART TRANSITTER
3.2UART RECEIVER
3.3 BUD GENERTOR
3.4SPECIFICATION

CHAPTER-4: SIULATION
4.1Simulation Step
4.2 waveIorms

CHAPTER-5
5.1 conclusion
APPENDIX-A
(a)code Ior complete UART
(b)Code Ior Transmitter
(c)code Ior Receiver
(d)code Ior Baud Genrtor
APPENDIX-B
(a)RTL Ior COPLETE UART
REFRENCES


























CHAPTER-1

Fundamentals oI VHDL Programming

1.1Introduction:

VHDL (Very High Speed IC Hardware description Language) is one oI the standard hardware
description language used to design digital systems. VHDL can be used to design the lowest
level (gate level) oI a digital system to the highest level (VLSI module). VHDL though being a
rigid language with a standard set oI rules allows the designer to use diIIerent methods oI design
giving diIIerent perspectives to the digital system.

Other than VHDL there are many hardware description languages available in the market Ior the
digital designers such as Verilog, ABEL, PALAS, CUPL, and etc but VHDL and Verilog are
the most widely used HDLs. The major diIIerence between hardware description programming
languages and others is the integration oI time .Timing speciIications are used to incorporate
propagation delays present in the system.

1.2Types of Representation:

VHDL representation can be seen as text Iile describing a digital system. The digital system
can be represented in diIIerent Iorms such as a behavioral model or a structural model. ost
commonly known as levels oI abstraction, these levels help the designer to develop complex
systems eIIiciently.

Behavioral Model:

Behavioral level describes the system the way it behaves instead oI a lowerabstraction oI its
connections. Behavioral model describes the relationshipbetween the input and output signals.
The description can be a RegisterTransIer Level (RTL) or Algorithmic (set oI instruction) or
simple Booleanequations.

Register Transfer Level:

RTL typically represents data Ilow withinthe systems like data Ilow between registers. RTL is
mostly used Ior design oIcombinational logics.

Algorithmic Level:

In this method, speciIic instruction set oIstatements deIine the sequence oI operations in the
system. Algorithmiclevel is mostly used Ior design oI sequential logics.





Structural Model:

Structural level describes the systems as gates or component blockinterconnected to perIorm the
desired operations. Structural level is primarilythe graphical representation oI the digital system
and so it is closer to the
actual physical representation oI the system.
1.3VHDL Programming Structure:

Entity and Architecture are the two main basic programming structures in VHDL.

Entity: Entity can be seen as the black box view oI the system. e deIine the inputs and outputs
oI the system which we need to interIace.
Entity AND GATE is
Port (A: in stdlogic;
B: in stdlogic;
Y: out stdlogic);
End entity ANDGATE;
Entity name ANDGATE is given by the programmer, each entity must have a name
.
Architecture: Architecture deIines what is in our black box that we described using ENTITY.
e can use either behavioral or structural models todescribe our system in the architecture. In
Architecture we will haveinterconnections, processes, components, etc.

Architecture AND1 oI ANDGATE is
--declarations
Begin
--statements
Y A AND B;
End architecture AND1;
Entity name or architecture name is user deIined. IdentiIiers can haveuppercase alphabets,
lowercase alphabets, and numbers and underscore().First letter oI identiIier must be an alphabet
and identiIier cannot end withan underscore.
In VHDL, keywords and user identiIiers are case insensitive.VHDL is strongly typed language
i.e. every object must be declared.
examples:

Note:
1) Every statement should end with a semi-colon
2) Statement Iollowed by -- is a comment statement
Basic VHDL operations:
AND gate:
--This is a comment line. elcome to VHDL programming
--The next two lines are the libraries that are included



LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
--The andgate entity is deIined. In this module A and B are deIined as the
input ports oI the
--halI-adder and C is deIined as the output port. The keyword in and out
Iollowing the colon
-- deIines it as input and output ports respectively and these ports can
supportstdlogic data
--types deIined by the library included above
entityandgateis
port(A,B:instdlogic;
C:outstdlogic);
endandgate;
architectureb of andgateis
begin
--and is a basic VHDL operation. represents the signal assignment
CA and B;
endb;
Now lets implement an OR gate.















OR gate:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entityorgateis
port(A,B:instdlogic;
C:outstdlogic);
endorgate;
architectureb of orgateis
begin
CA or B;
endb;
Similarly you can try out other basic gates like NAND, NOR, XOR, NOT andget Iamiliarized
with the entity and architecture declaration.
odels:
Implementation oI HalI Adder using Behavioral and Structural odels:
The section oI VHDL code below implements the halI adder.

Behavioral Modeling of Half Adder
RTL:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entityhalIadderis
port(A ,B:instdlogic;
S, C:outstdlogic);
endhalIadder;
architecturebehavioral of halIadderis
begin
-- Sum S is calculated as Axor B. The output is obtained aIter 5ns delay. --Similarly
carry C is obtained
-- aIterXns might be used to speciIy the delays and it works Iine with simulation.
But you might want to ---use the gate delays which will be added by deIault with
the ALTERA boards that you use Ior lab
SA xorB aIter 5ns;
CA and B aIter 5ns;
enda;


Algorithmic:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entityhalI-adder is
port(A, B:in stdlogic;
S, C:outstdlogic);
endhalI-adder;
architecturebehavior of halI-adder is
begin
--Process statement can be used Ior sequential statements and give a more
powerIul description oI
--behavior. In the Iollowing line sum denotes the name oI the process and A,B are
the sensitivity list
--which deIines when the process should be re-evaluated
sum: process(A,B)
begin
--II loop. Similar to other programming languages
if(AB)then
S'0';
else
S(A or B);
end if;
end process;
carry :process(A,B)
begin
caseA is
when '0'~CA;
when '1'~CB;
end case;
end process;
endbehavior;
Structural Approach:
LIBRARY IEEE;
USE IEEE.STDLOGIC1164.ALL;
entityhalI-adder is
port(A, B:in stdlogic;
S,C :out stdlogic);
endhalI-adder;
entityandgate is
port(X, Y:in stdlogic;
Z:outstdlogic);
endandgate;
architecturebehavioral of andgateis
begin
Z X and Y;
endbehavioral;
entityxorgateis
port(L, :in stdlogic;
N:outstdlogic);
endxorgate;
architecturebehavioral of xorgateis
begin
SL xor;
endbehavioral;
architecturestructural of halI-adder is
--andgate is deIined as a sub-block oI the entity halI-adder
--Component declaration
componentandgate
port(X, Y:in stdlogic; Z:out stdlogic);
endcomponent;
componentxorgate
port(L, :in stdlogic; N:out stdlogic);
endcomponent;
begin
--Component Instantiation
--Port mapping oI the input and output ports
A0:andgate port map( X~A;Y~B;Z~C);
X0:xorgate port map( L~A;~B;N~C);
endstructural;




















CHAPTER-2
Introduction to UART
2.1UART:
A UART is a (universal asynchronous receiver&tranmiter) is the microchip that controls a
computer interIace to its attached serial devices speciIically,it provides the computer with the
RS-232 data terminal equipment (DTE) interIace so that it can talk to & exchange data
with modems & other serial devices as part oI this interIace,the UART also:
O Convert the byte it receives Irom the computer along parallel circuit into a single
serial bit stream Ior outbound transmission
O On inbound transmission converts serial stream into the byte the computer handle
O Adds a parity bit (iI its been selected) on outbound transmission & checks the parity
oI incoming byte (iI selected) & discards the parity bit
O Adds start & stop delineators on the outbound & strips them Irom inbound
transmission
O Handle interrupt Irom keyboard & mouse (which are serially device with serial
ports)
Serial transmission is commonly used with modems Ior non-networked communication b\w
computer terminal & other devices


Fig: Serial data transmission





The communication links across which computer or port oI computer talk to one another
may be serial or parallel. A parallel link transmits several stream oI data (perhaps
representing particular bit oI stream oI bytes) along multiple channels (wires, printed circuit
tracks optical Iiber etc)
A serial links transmits a single stream oI data.at Iirst sight it would seem that a serial link
must be inIerior to parallel one, because it can transmit less data on each clock tick
.however ,it is oIten the case that serial links can be clocked cinderably Iaster than parral
links,& achieving a higher data rate .A number oI Iactor allow serial to be clocked at a
greator rate
Clock skew between diIIerent channel is not an issue (Ior unclocked serial links)
A serial connection requires Iever interconnecting cables(e.g. wires/Iiber) & hence
Occupies less space .the extra space allows Ior better isolations oI the channels Irom
its surroundings
Cross talk is less oI an issue ,because there are Iewer conductor is proximity in many
case,serial is better option because it is cheaper to implement many IC`s
Have serial interIace, as opposed to parallel ones ,so that they have Iewer pins &
thereIor cheaper



In telecommunications and computer science, serial communications is the process oI sending
data one bit at one time, sequentially, over a communications channel orcomputer bus. This is in
contrast to parallel communications, where all the bits oI each symbol are sent together. Serial
communications is used Ior all long-haul communications and most computer networks, where
the cost oI cable and synchronization diIIiculties make parallel communications impractical.
Serial computer buses are becoming more common as improved technology enables them to
transIer data at higher speeds.

2.1Serial versus parallel
The Serial Port is harder to interIace than the Parallel Port. In most cases, any device you
connect to the serial port will need the serial transmission converted back to parallel so
that it can be used. This can be done using a UART. On the soItware side oI things, there
are many more registers that you have to attend to than on a Standard Parallel Port. (SPP)

So what are the advantages oI using serial data transIer rather than parallel?



1. Serial Cables can be longer than Parallel cables. The serial port transmits a '1' as -3 to -25
volts and a '0' as 3 to 25 volts where as a parallel port transmits a '0' as 0v and a'1' as
5v. ThereIore the serial port can have a maximum swing oI 50V compared to the parallel
port which has a maximum swing oI 5 Volts. ThereIore cable loss is not going to be as
much oI a problem Ior serial cables than they are Ior parallel.

2. You don't need as many wires than parallel transmission. II your device needs to be
mounted a Iar distance away Irom the computer then 3 core cable (Null odem
ConIiguration) is going to be a lot cheaper that running 19 or 25 core cable. However
you must take into account the cost oI the interIacing at each end.

3. InIra-Red devices have proven quite popular recently. You may oI seen many electronic
diaries and palmtop computers which have inIra-red capabilities build in. However could
you imagine transmitting 8 bits oI data at the one time across the room and being able to
(Irom the devices point oI view) decipher which bits are which? ThereIore serial
transmission is used where one bit is sent at a time. IrDA-1 (The Iirst inIra-red
speciIications) was capable oI 115.2k baud and was interIaced into a UART .The pulse
length however was cut down to 3/16th oI a RS232 bit length to conserve power
considering these devices are mainly used on diaries, laptops and palmtops.


4. icrocontrollers have also proven to be quite popular recently. any oI these have in
built SCI (Serial Communications InterIaces) which can be used to talk to the outside
world. Serial Communication reduces the pin count oI these PU's. Only two pins are
commonly used, Transmit Data (TXD) and Receive Data (RXD) compared with at
least 8 pins iI you use a 8 bit Parallel method (You may also require a Strobe).
There are two primary Iorms oI serial transmission: Synchronous and Asynchronous.
Depending on the modes that are supported by the hardware, the name oI the
communication sub-system will usually include a A iI it supports Asynchronous
communications, and a S iI it supports Synchronous communications. Both Iorms are
described below.

2.3 Synchronous Serial Transmission
Synchronous serial transmission requires that the sender and receiver share a clock with one
another, or that the sender provide a strobe or other timing signal so that the receiver knows
when to 'read the next bit oI the data. In most Iorms oI serial Synch.communication, iI there is
no data available at a given instant to transmit, a Iill character must be sent instead so that data is
always being transmitted. Synchronous Comm. is usually more eIIicient because only data bits
are transmitted between sender and receiver, and synchronous communication can be more
costly iI extra wiring and circuits are required to share a clock signal between the sender and
receiver .A Iorm oI Synch. Transmission is used with printers and Iixed disk devices in that the
data is sent on one set oI wires while a clock or strobe is sent on a diIIerent wire. Printers and
Iixed disk devices are not normally serial devices because most Iixed disk interIace
standards send an entire word oI data Ior each clock or strobe signal by using a separate wire Ior
each bit oI the word. In the PC industry, these are known as Parallel devices. The standard serial
communications hardware in the PC does not support Synchronous operations. This mode is
described here Ior comparison purposes only.


2.4 Asynchronous Serial Transmission
Asynchronous serial communication describes an asynchronous transmission protocol
in which a start signal is sent prior to each byte, character or code word and a stop signal
is sent aIter each code word. The start signal serves to prepare the receiving mechanism






Ior the reception and registration oI a symbol and the stop signal serves to bring the receiving
mechanism to rest in preparation Ior the reception oI the next symbol. A common kind oI start-
stop transmission is ASCII over RS-232, Ior example Ior use in teletypewriter operation.In the
diagram, a start bit is sent, Iollowed by eight data bits, no parity bit and one stopbit, Ior a 10-bit
character Irame. The number oI data and Iormatting bits, and the transmission speed, must be
pre-agreed by the communicating parties .AIter the stop bit ,the line may remain idle
indeIinitely, or another character may immediately be started.

2.5 Bits, Baud and Symbols
Baud is a measurement oI transmission speed in asynchronous communication. Because
oI advances in modem communication technology, this term is Irequently misused when
describing the data rates in newer devices. Traditionally , a Baud Rate represents the number oI
bits that are actually being sent over the media, not the amount oI data that is actually moved
Irom one DTE device to the other. The Baud count includes the over head bits Start, Stop and
Parity that are generated by the sending UART and removed by the receiving UART. This means
that seven-bit words oI data actually take 10 bits to be completely transmitted. ThereIore, a
modem capable oI moving 300 bits per second Irom one place to another can normally only
move 30 7-bit words iI Parity is used and one Start and Stop bit are present. II 8-bit data words
are used and Parity bits are also used, the data rate Ialls to 27.27 words per second, because it
now takes 11 bits to send the eight-bit words, and the modem still only sends 300 bits per
second. The Iormula Ior converting bytes per second into a baud rate and vice versa was simple
until error correcting modems came along. These modems receive the serial stream oI bits Irom
the UART in the host computer (even when internal modems are used the data is still Irequently
serialized) and converts the bits back into bytes. These bytes are then combined into packet sand
sent over the phone line using a Synchronous transmission method. This means that the Stop,
Start, and Parity bits added by the UART in the DTE(the computer) were removed by the
modem beIore transmission by the sending modem. hen these bytes are received by the remote
modem, the remote modem adds Start, Stop and Parity bits to the words, converts them to a
serial Iormat and then sends them to the receiving UART in the remote computer, who then
strips the Start, Stop and Parity bits. The reason all these extra conversions are done is so that the
two modems can perIorm error correction, which means that the receiving modem is able to ask
the sending modem to resend a block oI data that was not received with the correct checksum.
This checking is handled by the modems, and the DTE devices are usually unaware that the
process is occurring. By striping the Start, Stop and Parity bits, the additional bits oI data that the
two modems must share between themselves to perIorm error-correction are mostlyconcealed
Irom the eIIective transmission rate seen by the sending and receiving DTEequipment.
For example, iI a modem sends ten 7-bit words to another modem without including the Start,
Stop and Parity bits, the sending modem will be able to add 30 bits oI its own inIormation that
the receiving modem can use to do error-correction without impacting the transmission speed oI
the real data.The use oI the term Baud is Iurther conIused by modems that perIorm compresion.
A single 8-bit word passed over the telephone line might represent a dozen words that were txd
to the sending modem. The receiving modem will expand the data back to its original content
and pass that data to the receiving DTE. odern modems also include buIIers that allow the rate
that bits move across the phone line (DCE to DCE) to be a diIIerent speed than the speed that the
bits move between the DTE and DCE on both ends oI the conversation. Normally the speed
between the DTE and DCE is higher than the DCE to DCE speed because oI the use oI
comprsion by the modems. Because the number oI bits needed to describe abyte varied during
the trip between the two machines plus the diIIering bits-per-seconds speeds that are used present
on the DTE-DCE and DCE-DCE links, the usage oI the term Baud to describe theoverall
communication speed causes problems and can misrepresent the true transmission speed. So Bits
Per Second (bps) is the correct term to use to describe the transmission rate seen at the DCE to
DCE interIace and Baud or Bits Per Second are acceptable terms to use when a connection is
made between two systems with a wired connection, or iI a modem is in use that is not
perIorming error-correction or compression. odern high speed modems (2400, 9600, 14,400,
and 19,200bps) in reality still operate at or below 2400 baud, or more accurately, 2400 Symbols
per second. High speed modem are able to encode more bits oI data into each Symbol using a
technique called Constellation StuIIing, which is why the eIIective bits per second rate oI the
modem is higher, but the modem continues to operate within the limited audio band width that
the telephone system provides. odems operating at 28,800 and higher speeds have variable
Symbol rates, but the technique is the same.

2.6 Asynchronous Serial Reception
A multiplexed data communication pulse can only be in one oI two states but there are many
names Ior the two states. hen on, circuit closed, low voltage, current Ilowing, ora logical zero,
the pulse is said to be in the "space" condition. hen oII, circuit open ,high voltage, current
stoped, or a logical one, the pulse is said to be in the "mark" condition. A character code begins
with the data communication circuit in the space condition. II the mark condition appears, a
logical one is recorded otherwise a logical zero.

Figure 1 shows this multiplexing Iormat.

start,- Iive to eight data bits -~, stop bit(s)
0 ---- - - - - - - - - - - -
Space(logic low, high data-wire voltage)
, , , , , , , , , , , ,
, S , 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , S , S ,
, , , , , , , , , , , ,
1 - - - - - - - - - - - --------
ark(logic high, low data-wire voltage)

The least-signiIicant bit is always transmitted Iirst. II parity is present, the parity bit comes aIter
the data bits but beIore the stop bit(s).The start bit is always a '0' (logic low), which is also called
a space. Ironically, the logic low '0' corresponds to a high voltage on the data wire. The start bit
signals the receiving DTE that a character code is coming. The next Iive to eight bits, depending
on the codeset employed, represent the character. In the ASCII code set the eighth data bit may
be aparity bit. The next one or two bits are always in the mark (logic high, i.e., '1') condition and
called the stop bit(s). They provide a "rest" interval Ior the receiving DTE so that it may prepare
Ior the next character which may be aIter the stop bit(s). The rest interval was required by the old
mechanical Teletypes which used a motor driven camshaIt to decode each character. At the end
oI each character the motor needed time to strike the character bail (print the character) and reset
the cam shaIt. There are six basic steps in receiving a serial character code into a parallel
register. First ,to keep track oI time, the receiver employs a clock which "ticks." hen the line is
in the space condition, the receiver samples the line 16 times the data rate. In other words, a
data interval is equal to 16 clock ticks. In this way the receiver can determine the beginning oI
the start bit and "move over" to the center oI the bit time Ior data sampling. Second, when the
line goes into the mark state, declare a "looking Ior start bit" condition and wait one halI the bit
interval or eight clock ticks. Third, sample the line again and iI it has not remained in the mark
condition, consider this to be a spurious voltage change and go back to step one. Fourth, iI the
line was still in the mark state, then consider this a valid start bit. ShiIt the start bit into an eight-
bit shiIt register and wait one bit time or 16clock ticks. FiIth, aIter one bit time sample the line
(the data should have been there Ior the last eight clock ticks, and should remain Ior eight more
clock ticks). Now shiIt the sample into the shiIt register. Sixth, continue steps Iour and Iive seven
more times. AIter the eighth shiIt, the start bit will "migrate" into a Ilip-Ilop indicating character
received .Go to step one.

BeIore the transmitter and receiver UARTs will work, they must also agree on the same values
oI Iive parameters. First, both sides must agree on the number oI bits per character. Second, the
speed or Baud oI the line must be the same on both sides. Third ,both sides must agree to use or
not use parity. Fourth, iI parity is used, both sides must agree on using odd or even parity. FiIth,
the number oI stop bits must be agreed upon. Having said all this, most DTEs today employ
eight data bits, no parity, and one stop bit .Thus there is a rule-oI-thumb that the number oI
characters per second is equal to the Baud divided by 10 Ior a typical RS-232 or RS-423 data
line.

1.7 Other UART Functions
In addition to the basic job oI converting data Irom parallel to serial Ior transmission and Irom
serial to parallel on reception, a UART will usually provide additional circuits Ior signals that
can be used to indicate the state oI the transmission media, and to regulate the Ilow oI data in the
event that the remote device is not prepared to accept more data.


For example, when the device connected to the UART is a modem, the modem may report
the presence oI a carrier on the phone line while the computer may be able to instruct the
modem to reset itselI or to not take calls by raising or lowering one more oI these extra signals.
The Iunction oI each oI these additional signals is deIined in the EIA RS232-Cstandard.

CHAPTER-3
UART MODEL

The VHDL model oI the UART is divided into three major VHDL processes.Theprocesses are
called "main", "receiver" and "transmitter". First we will look at the globalsignals and variables
(local to a process) used in the model and their Iunctions. Then, wewill brieIly study each oI the
three processes.

Process Descriptions

The VHDL model consists oI three major processes ("main", "receiver" and"transmitter"). e
will brieIly discuss each oI them.

Main Process

The "main" process has the primary task oI being an interIace to the CPU. It uses theinternal
device clock "clk". On getting a reset (internal/external), the main processinitializes the global
signals, local variables and ports.Then, at every rising clock edge, itchecks Ior signals Irom the
CPU. Since a mode command (Irom the CPU) mustimmediately Iollow a reset, it stores the next
CPU control word in the "mode" globalsignal. On getting the mode word, it computes the
Iollowingparameters :

(a) number oI bits per character
(b) number oI clock cycles per bit
(c) number oI stop-bit clock cycles (Async mode)
d) number oI clock cycles through which RxD has to remain low Ior Break-Detect
in Asynchronous receive.
These parameters are assigned to global signals and are used by the "transmitter" and"receiver"
processes. Then, the process waits Ior SYNC character(s), iI InternalSynchronization ode has
been programmed. The SYNC character(s) are also assignedto global signals Ior use by the
"transmitter" and "receiver" processes. Then the processwaits Ior a command word Irom the
CPU. ( II Internal Synchronization ode has notbeen programmed, the process waits Ior a
command immediately aIter getting a modeword, since no SYNC character(s) are expected.) The
command word is assigned to aglobal signal "command" and various operations (e.g. Internal
reset, error Ilag reset, enterHUNT ODE) are perIormed, depending on which bits are set in the
command word.AIter this initial phase, other control words sent by the CPU are interpreted as
Commandwords. II the CPU sends data characters Ior transmission, that character is stored in the
global signal "TxbuIIer" (iI the transmitter is enabled) and the TxRDY status bit is reset.It also
notes whether "CTSBAR" (clear-to-send input) was low when the character waswritten, by
conditionally setting the global signal "Txwrwhilects". The CPU maywant to read a data
character that has been received by the USART. In that case, (iI thereceiver is enabled) the data
bits in global signal"RxbuIIer" are placed on the data buspins and "RxRDY" is reset. The CPU
may want to read the status oI the USART. In thatcase, the bits in global signal "status" are
placed on the data bus pins and"SYNDETBD" is reset.








llg uA81 block dlagram


Main Process In UART

(a) Tx process
(b)Rx process
(c) Baud genertor


Transmitter process

The "transmitter" process uses the transmitter clock "TxCBAR". On getting a resetExternal
,internal, the transmitter process initializes the global signals, local variablesand ports. II the
TxRDY status bit is reset (which means that "TxbuIIer" is Iull), the itchecks whether the tx has
been enabled and "CTSBAR" (clear-to-send input)is low. II all oI these conditions are satisIied
or it Iinds that "TxbuIIer" contains acharacter that was written while "CTSBAR" was low
(signiIied by high value on signal"Txwrwhilects"), the transmitter prepares to transmits the
data character. II thetransmitter is disabled or CTSBAR is low, he transmitter send a
ARKING (high)
signal on "TxD" unless it has been commanded to send a BREAK (continous low). In
"Internal Synchronization ode" , iI the transmitter is enabled and CTSBAR is low, but
"TxbuIIer" is empty, then the transmitter sends the SYNC character(s) as Iillers. For
transmitting the data character, the transmitter transIers the data Irom "TxbuIIer" to
"serialTxbuIIer". It sets the TxRDY status bit because the USART can accept a new
character while this one is being transmitted. It also resets TxEPTY to signiIy that the
"serialTxbuIIer" is Iull. II the mode is asynchronous, it Iirst transmits a start bit (low).

In asynchronous mode, every bit is transmitted Ior a number oI clock (TxCBAR)
cyclesdepending on the baud rate. In synchronous mode, every bit is sent Ior only one clock
cycle. The counter "clkcount" is used to keep track oI the number oI clock cycles thathave
passed. Bits are shiIted out at the Ialling edge oI TxCBAR. The data bits are thentransmitted.
The counter "charbitcount" is used to count the number oI character bitstransmitted. II parity is
enabled, the appropriate (even/odd) parity bit is transmitted aIterthe data bits. Then, TxEPTY
is reset to signiIy that the "serialTxbuIIer" is empty. IIthe mode is asynchronous, then the
required number oI stop bits (high) are transmitted.




Receiver Process

The "receiver" process uses the transmitter clock "RxCBAR". On getting a reset Internal
external,the receiver process initializes the global signals, local variables andports. The receiver
process is best understood by considering synchronous andAsynchronous reception separately




Asynchronous mode

II the mode is asynchronous and the receiver is enabled, then RxD is Iirst sampled. IIRxD is low,
then the receiver is not ready to receive a start bit yet and it waits till the nextrising edge on
RxCBAR and samples RxD again. II RxD stays low through a periodequal to two character
sequences,a break is detected. A counter "brkcount" is used tokeep track oI thenumber oI clock
cycles through which RxCBAR has stayed low. Thiscounter is reset whenever RxD goes high.
II RxD is high, the receiver is ready to receive a Start-Bit (low). It waits Ior a Ialling edgeonRxd
(Start-Bit). II the baud rate is 16X or 64X, the receiver waits Ior a number oIRxCBAR cycles
equal to halI the baud rate ( Irom now, we will call this number"halIbaud" -- e.g. Ior 16X baud
rate, "halIbaud" will be 8 RxCBAR cycles).Then itsamples RxD again to see iI its still low
(False Start-Bit Detection Scheme).II its stilllow, then it proceeds to wait Ior another "halIbaud"
RxCBAR cycles and then startsassembling the character. II its high, this is a Ialse Start-Bit and
it goes back to waitingIor a Ialling edge on RxD.For baud rate 1X, there is no Ialse start-bit
detection. For baud rate 1X, data bits andparity bit (iI enabled) are sampled at the next rising
edge RxCBAR edge. For baud rate16X or 64X, data bits and parity bit (iI enabled) are sampled
at their "nominal center".This is done by waiting Ior "halIbaud" RxCBAR cycles and then
sampling RxD at thenextRxCBASR rising edge. Then, the receiver waits Ior "halIbaud"
RxCBARcycles.The variable "clkcount" is used to count the number oI RxCBAR cycles
passed. Thereceiver assembles data characters by shiIting in bits Irom RxD
intoThe"serialRxbuIIer", Ior the required number character bits (counted by"charbitcount").
II parity has been programmed, then the parity bit is received aIter the data bits and parity
error is checked. The parity error Ilag is set, iI error is detected. The assembled istransIerred
Irom the "serialRxbuIIer" to the "RxbuIIer". ( The CPU can read thisbuIIer, via the "main"
process.) II the receiver is enabled, RxRDY is set to signal theCPU that a received character is
waiting to be read.II the previously received character (iI any) is still unread by the CPU, then
this newcharacter overwrites it and overrun error is detected. Then, the receiver checks the stop
bit (high) at the next rising edge oI clock. II RxD is low, then Iraming error Ilag isasserted.













BAUDRATE GENERATOR



Specification

The Intel 8251 Universal Synchronous/Asynchronous Receiver/Transmitter (USART),
designed Ior data communication with Intel's microprocessor Iamilies. It is used as a
peripheral device and is programmed by the CPU to operate using many serial data
transmission techniques. The USART accepts data characters Irom the CPU in parallel
Iormat and then converts them into a continuous serial data stream. It accepts serial data
streams and converts them into parallel data characters Ior the CPU. The USART will
signal the CPU whenever it can accept a new character Ior transmission or whenever it
has received a character Ior the CPU. The CPU can read the status oI the USART at any
time. The status includes data transmission errors and control signals SYNDET/BD,
TxEPTY, TxRDY, RxRDY.

Ports

RESET ( 1 BIT, INPUT PORT ) :
This is the master reset Ior the 8251 chip. D7 to D0 ( 8 PINS, 1 BIT each, INOUT
PORTS) : These are the bi-directional data bus pins (8 bits) used Ior transIerring
data/control/status words transIer the USART and the CPU. These are usually connected
to the CPU's data-bus, although the CPU always remains in control oI the bus and
initiates all transIers.

CSBAR ( 1 BIT, INPUT PORT ) :

This is the Chip-Select line. A low on this line enables data communication between the
CPU and the USART.

RDBAR ( 1 BIT, INPUT PORT ) :

This is the read line. A low on this line causes the USART to place the status word or the
( received ) data word on the data bus pins("D7" to "D0").

RBAR ( 1 BIT, INPUT PORT ) :
This is the write line. A low on this line causes the USART to accept the data on the data
bus pins ( "D7" to "D0") as either a control word or as a data character (Ior
transmission).

CDBAR ( 1 BIT, INPUT PORT ) :

This is the "Control/Data" pin. It is used while transIerring data to/Irom the CPU using
the data bus pins ("D7" to "D0").
During a read operation : II CDBAR - 1, the USART places its status on the data bus
pins. II CDBAR - 0, the USART places the (received) data character on the data bus
pins.
During a write operation : II CDBAR - 1, the USART reads a control word Irom the
data bus pins. II CDBAR - 0, the USART reads a data character (Ior transmission)
Irom the data bus pins.

RxD( 1 BIT, INPUT PORT ) :

This is the receiver data pin. Characters are received serially on this pin and assembled
into parallel characters.

TxD( 1 BIT, OUTPUT PORT ) :

This is the transmitter data pin. Parallel characters received by the CPU are transmitted
serially by the USART on this line.

RxCBAR( 1 BIT, INPUT PORT ) :

This is the receiver clock. Data on "RxD" is sampled by the USART on the rising edge
oI "RxCBAR".
TxCBAR( 1 BIT, INPUT PORT ) :

This is the transmitter clock. Data is shiIted out serially on "TxD" by the USART, on the
Ialling edge oI "TxCBAR".
CLK ( 1 BIT, INPUT PORT ) :

This clock is used Ior internal device timing. It needs to be Iaster than "TxCBAR" and
"RxCBAR".

TxEPTY( 1 BIT, OUTPUT PORT ) :

A high on this line indicates that the serial buIIer in the transmitter is empty. This line
goes low only while a data character is being transmitted by the USART. It goes high as
soon as the USART completes transmitting a character and a new one has not been
loaded in time.

TxRDY( 1 BIT, OUTPUT PORT ) :

This pin signals the CPU that the USART is ready to accept a new data character Ior
transmission. "TxRDY" is reset when the USART receives a data character Irom the
CPU.

RxRDY( 1 BIT, OUTPUT PORT ) :

This pin signals the CPU that the USART has received a character on its serial input
"RxD" and is ready to transIer it to the CPU. "RxRDY" is reset when the character is read
by the CPU.



SYNDETBD (1 BIT, INOUT PORT ) :

In the Synchronous mode, this line can be in two ways (while receiving characters). In
the "Internal-Synchronization" mode, this line is used as an output which goes high when
the programmed "SYNC-characters" are detected on the "RxD" line. In the "External-
Synchronization" mode, this line is used as an input and the USART starts assembling
data characters at the next clock ("RxCBAR") edge aIter a rising edge on this line. In the
Asynchronous mode, this line is used as a "Break-Detect" output which goes high iI the
"RxD" line has stayed low Ior two consecutive character lengths (including start, stop
and parity bits).

RTSBAR (1 BIT, OUTPUT PORT) :

This "Request-ToSend" is a general purpose output signal that can be asserted by a
"command word" Irom the CPU. It may be used to request that the modem prepare itselI
to transmit.

CTSBAR (1 BIT, INPUT PORT) :

This "Clear-To-Send" is an input signal that can be read by the CPU as part oI the
"status-word". A low on this line enables the USART to transmit data. A low on
"CTSBAR" is normally generated as a response to an assertion on "RTSBAR".

DTRBAR (1 BIT, OUTPUT PORT) :

This "Data-Terminal-Ready" is a general purpose output signal that can be asserted by a
"command word" Irom the CPU.

DSRBAR (1 BIT, INPUT PORT) :

This "Data-Set-Ready" is a general purpose input signal that can be read by the CPU as
part oI the "status-word".

General Operation

Programming the UART

The complete Iunctional deIinition oI the 8251 is programmed by the system's soItware.
A set oI control words must be sent out by the CPU to initialize the 8251 to support the
desired communication Iormat. These words must immediately Iollow a reset
(internal/external).





The ode word

Immediately aIter a reset, the CPU has to send the 8-bit "mode" word. The 8251 can be
used Ior either synchronous/asynchronous data communication. To understand how the
mode instruction works, its best to view the device as two separate components, one
synchronous and the other asynchronous.

Synchronous mode word

, Bit 0 , Bit 1 ,
, 0 , 0 ,
The two least signiIicant bits must be both 0 in Synchronous mode.
28
Character length : (bits per character)

, Bit 3 , Bit 2 ,, ,
,-------,-------,,-------------,
, 0 , 0 ,, 5 bits ,
,,,,,
, , ,, ,
, 0 , 1 ,, 6 bits ,
,,,,,
, , ,, ,
, 1 , 0 ,, 7 bits ,
,,,,,
, , ,, ,
, 1 , 1 ,, 8 bits ,
,,,,,
Parity :

, Bit 5 , Bit 4 ,, ,
,-------,-------,,-------------,
, 0 , 0 ,, No parity ,
,,,,,
, , ,, , Bit 4 -- Parity Enable
, 0 , 1 ,, Odd parity ,
,,,,, Bit 5 -- Even Parity
, , ,, ,
, 1 , 0 ,, No parity ,
,,,,,
, , ,, ,
, 1 , 1 ,, Even parity ,
,,,,,
29
Synchronization scheme :

, Bit 7 , Bit 6 ,, ,
,-------,-------,,-----------------------------------------------,
, 0 , 0 ,, Internal sync detect, Double Sync character ,
,,,,,
, , ,, ,
, 0 , 1 ,, External sync detect (Irom SYNDETBD input) ,
,,,,,
, , ,, ,
, 1 , 0 ,, Internal sync detect, Single Sync character ,
,,,,,
, , ,, ,
, 1 , 1 ,, External sync detect (Irom SYNDETBD input) ,
,,,,,
Bit 6 -- External Synchronization
Bit 7 -- Single Sync character (Internal Synchronization)

Asynchronous mode word

Baud Rate :In asynchronous mode, the baud rate deIines the number oI clock
(RxCBAR/TxCBAR) cycles over which each bit is transmitted/received.( e.g. At baud
rate 64X, each bit is transmitted over 64 clock cycles).

, Bit 1 , Bit 0 ,, ,
,-------,-------,,---------------------------------,
, 0 , 0 ,, Not relevant (Synchronous mode) ,
,,,,,
, , ,, ,
30
, 0 , 1 ,, 1X baud rate ,
,,,,,
, , ,, ,
, 1 , 0 ,, 16X baud rate ,
,,,,,
, , ,, ,
, 1 , 1 ,, 64X baud rate ,
,,,,,
Character length : (bits per character)

, Bit 3 , Bit 2 ,, ,
,-------,-------,,-------------,
, 0 , 0 ,, 5 bits ,
,,,,,
, , ,, ,
, 0 , 1 ,, 6 bits ,
,,,,,
, , ,, ,
, 1 , 0 ,, 7 bits ,
,,,,,
, , ,, ,
, 1 , 1 ,, 8 bits ,
,,,,,

Parity :

, Bit 5 , Bit 4 ,, ,
,-------,-------,,-------------,
, 0 , 0 ,, No parity , Bit 4 -- Parity Enable
,,,,,
, , ,, , Bit 5 -- Even Parity
, 0 , 1 ,, Odd parity ,
,,,,,
, , ,, ,
, 1 , 0 ,, No parity ,
,,,,,
, , ,, ,
, 1 , 1 ,, Even parity ,
,,,,,
No oI Stop Bits :

, Bit 7 , Bit 6 ,, ,
,-------,-------,,---------------,
, 0 , 0 ,, Invalid ,
,,,,,
, , ,, ,
, 0 , 1 ,, 1 stop bit ,
,,,,,
, , ,, ,
, 1 , 0 ,, 1.5 stop bits ,
,,,,,
, , ,, ,
, 1 , 1 ,, 2 stop bits ,
,,,,,

The Command word and SYNC characters

In the "Internal Synchronization" mode, the control words (Irom the CPU) that Iollow the
mode word, must be SYNC characters. In Single-Sync mode, only one SYNC character
(SYNC1) is loaded. In Double-Sync mode, two consecutive SYNC characters (SYNC1
Iollowed by SYNC2) must be loaded. The SYNC character(s) have the same number oI
bits as the data characters (as programmed in the mode word).The SYNC characters (iI
present, i.e. in "Internal Synchronization" mode) are Iollowed by the command word
Irom the CPU. Data words (Ior transmission) can Iollow that.Actually, the command
word can be written by the CPU at any time in the data block during the operation oI the
USART. To write a new ode word, the master reset in the Command instruction can be
set to initiate an "Internal Reset".

Command ord

Bit 0 : Transmitter Enable
Bit 1 : DTR (Data Terminal Ready) -- Controls DTRBAR output( iI this is high,
DTRBAR is low)
Bit 2 : Receiver enable
Bit 3 : Send Break -- Assertion oI this Iorces "TxD" pin low
Bit 4 : Error Reset -- Reset all error Ilags (parity error, Iraming error overrun error) in the
status word .
Bit 5 : RTS (Request To Send) -- Controls RTSBAR output ( iI this is high, RTSBAR
is low)
Bit 6 : Internal Reset -- Resets the USART and makes it ready to accept a new mode
word.
Bit 7 : Enter Hunt ode -- ( used only in synchronous receive). II this is high, the
USART tries to achieve synchronization by entering the "hunt mode". In "Internal
Synchronization" mode, the USART starts looking Ior the programmed SYNC
character(s) at the "RxD" input. In "External Synchronization" mode, the USART starts
looking Ior a rising edge on the "SYNDETBD" input. Once synchronization is
achieved, the USART gets out oI "hunt mode" and starts assembling characters at the
next rising edge oI "RxCBAR".

The Status ord

The CPU can read the "status word" Irom the USART at any time.
Bit 0 :TxRDY -- This signiIies whether the transmitter is ready to receive a new
character Ior transmission Irom the CPU. However, in order Ior the "TxRDY" PIN to be
high, three conditions must be satisIied :
(a) TxRDY STATUS BIT must be high
(b) "CTSBAR" must be low
(c) The transmitter must be enabled ( Bit 0 in the Command word must be
high).
Bit 1 :RxRDY -- Same as "RxRDY" pin.
Bit 2 :TxEPTY -- Same as "TxEPTY" pin.
Bit 3 : Parity Error -- hen parity is enabled and a parity error is detected in any
received character, this bit is set.
Bit 4 : Overrun Error -- hen the CPU does not read a received character beIore the next
one becomes available, this bit is set. However, the previous character is lost.
Bit 5 : Framing Error -- Used only in asynchronous mode. hen a valid stop bit (high) is
not detected at the end oI a received character, this bit is set.
(Note : All three error Ilags are reset by the "Error Reset" command bit. Also, the setting
oI these error Ilags does not inhibit the USART operation.)
Bit 6 : SYNDETBD -- Same as "SYNDETBD" pin.
Bit 7 : DSR (Data Set Ready) -- Controlled by "DSRBAR" pin. (II "DSRBAR" pin is
low, his status bit is high.)

CHAPTER-4
SIULATION
Simulation Step:
1



2



3


4




5




6

7



8


9


10

11

12

13












Waveform:


2



3


4

CHAPTER-5
CONCLUSION

CONCLUSION:
Hence, in the project titled ' Serial Communication using UART the Iunctioning oI a
8251 chip according to RS232 C standards was studied with VHDL programming.

Ajay Sharma

Darshan
Suraj
















APPENDIX-A



VHDL CODES























(a)CODE:COMPLETE UART

libraryieee;
use ieee.stdlogic1164.all;
entity UART is
port (SCIsel, R, clk, rstb, RxD : in stdlogic;
ADDR2: in stdlogicvector(1 downto 0);
DBUS :inoutstdlogicvector(7 downto 0);
SCIIRQ, TxD : out stdlogic);
end UART;

architecture uart1 oI UART is
componentUARTReceiver
port (RxD, BclkX8, sysclk, rstb, RDRF: in stdlogic;
RDR: out stdlogicvector(7 downto 0);
setRDRF, setOE, setFE: out stdlogic);
end component;

componentUARTTransmitter
port (Bclk, sysclk, rstb, TDRE, loadTDR: in stdlogic;
DBUS: in stdlogicvector(7 downto 0);
setTDRE, TxD: out stdlogic);
end component;

componentclkdivider
port (Sysclk, rstb: in stdlogic;
Sel: in stdlogicvector(2 downto 0);
BclkX8: buIIer stdlogic;
Bclk: out stdlogic);
end component;

signal RDR : stdlogicvector(7 downto 0); -- Receive Data Register
signal SCSR : stdlogicvector(7 downto 0); -- Status Register
signal SCCR : stdlogicvector(7 downto 0); -- Control Register
signal TDRE, RDRF, OE, FE, TIE, RIE : stdlogic;
signalBaudSel : stdlogicvector(2 downto 0);
signalsetTDRE, setRDRF, setOE, setFE, loadTDR, loadSCCR : stdlogic;
signalclrRDRF, Bclk, BclkX8, SCIRead, SCIrite : stdlogic;

begin

RCVR: UARTReceiver port map(RxD, BclkX8, clk, rstb, RDRF, RDR, setRDRF,
setOE, setFE);
XIT: UARTTransmitter port map(Bclk, clk, rstb, TDRE, loadTDR, DBUS,
setTDRE, TxD);
CLKDIV: clkdivider port map(clk, rstb, BaudSel, BclkX8, Bclk);
-- This process updates the control and status registers
process (clk, rstb)

begin

iI (rstb '0') then
TDRE '1'; RDRF '0'; OE '0'; FE '0';
TIE '0'; RIE '0';
elsiI (risingedge(clk)) then

TDRE (setTDRE and not TDRE) or (not loadTDR and TDRE);
RDRF (setRDRF and not RDRF) or (not clrRDRF and RDRF);
OE (setOE and not OE) or (not clrRDRF and OE);
FE (setFE and not FE) or (not clrRDRF and FE);
iI (loadSCCR '1') then TIE DBUS(7); RIE DBUS(6);
BaudSel DBUS(2 downto 0);
end iI;
end iI;
end process;

-- IRQ generation logic

SCIIRQ '1' when ((RIE '1' and (RDRF '1' or OE '1'))
or (TIE '1' and TDRE '1'))
else '0';

-- Bus InterIace

SCSR TDRE & RDRF & "0000" & OE & FE;
SCCR TIE & RIE & "000" &BaudSel;
SCIRead '1' when (SCIsel '1' and R '0') else '0';
SCIrite '1' when (SCIsel '1' and R '1') else '0';
clrRDRF '1' when (SCIRead '1' and ADDR2 "00") else '0';
loadTDR '1' when (SCIrite '1' and ADDR2 "00") else '0';
loadSCCR '1' when (SCIrite '1' and ADDR2 "10") else '0';
DBUS "ZZZZZZZZ" when (SCIRead '0')

-- tristate bus when not reading

else RDR when (ADDR2 "00")

-- write appropriate register to the bus

else SCSR when (ADDR2 "01")
else SCCR; -- dbus sccr, iI ADDR2 is "10" or "11"
end uart1;



(b) Code For Transmitter
libraryieee;
use ieee.stdlogic1164.all;
entityUARTTransmitter is
port(Bclk, sysclk, rstb, TDRE, loadTDR: in stdlogic;
DBUS:instdlogicvector(7 downto 0);
setTDRE, TxD: out stdlogic);
endUARTTransmitter;

architecturexmit oI UARTTransmitter is

typestateType is (IDLE, SYNCH, TDATA);
signal state, nextstate : stateType;
signal TSR : stdlogicvector (8 downto 0); -- Transmit ShiIt Register
signal TDR : stdlogicvector(7 downto 0); -- Transmit Data Register
signalBct: integer range 0 to 9; -- counts number oI bits sent
signalinc, clr, loadTSR, shItTSR, start: stdlogic;
signalBclkrising, Bclkdlayed: stdlogic;

begin

TxD TSR(0);
setTDRE loadTSR;
Bclkrising Bclk and (not Bclkdlayed);

-- indicates the rising edge oI bit clock

XmitControl: process(state, TDRE, Bct, Bclkrising)

Begin

inc '0'; clr '0'; loadTSR '0'; shItTSR '0'; start '0';

-- reset control signals

case state is

when IDLE ~ iI (TDRE '0' ) then
loadTSR '1'; nextstate SYNCH;
elsenextstate IDLE;
end iI;

when SYNCH ~

-- synchronize with the bit clock

iI (Bclkrising '1') then
start '1'; nextstate TDATA;
elsenextstate SYNCH;
end iI;

when TDATA ~
iI (Bclkrising '0') then nextstate TDATA;
elsiI (Bct / 9) then
shItTSR '1'; inc '1'; nextstate TDATA;
elseclr '1'; nextstate IDLE; end iI;
end case;
end process;

Xmitupdate: process (sysclk, rstb)

begin
iI (rstb '0') then
TSR "111111111"; state IDLE; Bct 0; Bclkdlayed '0';
elsiI (sysclk'event and sysclk '1') then
state nextstate;
iI (clr '1') then Bct 0; elsiI (inc '1') then
Bct Bct 1; end iI;
iI (loadTDR '1') then TDR DBUS;
end iI;
iI (loadTSR '1') then TSR TDR & '1';
end iI;
iI (start '1') then TSR(0) '0';
end iI;
iI (shItTSR '1') then TSR '1' & TSR(8 downto 1);
end iI;

-- shiIt out one bit

Bclkdlayed Bclk; -- Bclk delayed by 1 sysclk
end iI;
end process;
endxmit;







(c)Code for Receiver
libraryieee;
use ieee.stdlogic1164.all;
entityUARTReceiver is
port(RxD, BclkX8, sysclk, rstb, RDRF: in stdlogic;
RDR: out stdlogicvector(7 downto 0);
setRDRF, setOE, setFE: out stdlogic);
endUARTReceiver;

architecturercvr oI UARTReceiver is

typestateType is (IDLE, STARTDETECTED, RECVDATA);
signal state, nextstate: stateType;
signal RSR: stdlogicvector (7 downto 0); -- receive shiIt register
signal ct1 : integer range 0 to 7; -- indicates when to read the RxD input
signal ct2 : integer range 0 to 8; -- counts number oI bits read
signal inc1, inc2, clr1, clr2, shItRSR, loadRDR : stdlogic;
signal BclkX8Dlayed, BclkX8rising : stdlogic;

begin

BclkX8rising BclkX8 and (not BclkX8Dlayed);

-- indicates the rising edge oI bitX8 clock

RcvrControl: process(state, RxD, RDRF, ct1, ct2, BclkX8rising)

Begin

-- reset control signals

inc1 '0'; inc2 '0'; clr1 '0'; clr2 '0';
shItRSR '0';
loadRDR '0';
setRDRF '0';
setOE '0';
setFE '0';

case state is

when IDLE ~ iI (RxD '0' ) then nextstate STARTDETECTED;
elsenextstate IDLE;
end iI;
when STARTDETECTED ~
iI (BclkX8rising '0') then nextstate STARTDETECTED;
elsiI (RxD '1') then clr1 '1'; nextstate IDLE;
elsiI (ct1 3) then clr1 '1'; nextstate RECVDATA;
else inc1 '1'; nextstate STARTDETECTED;
end iI;
when RECVDATA ~
iI (BclkX8rising '0') then nextstate RECVDATA;
else inc1 '1';
iI (ct1 / 7) then nextstate RECVDATA;

-- wait Ior 8 clock cycles

elsiI (ct2 / 8) then
shItRSR '1'; inc2 '1'; clr1 '1';
-- read next data bit

nextstate RECVDATA;
else
nextstate IDLE;
setRDRF '1'; clr1 '1'; clr2 '1';
iI (RDRF '1') then setOE '1'; -- overrun error
elsiI (RxD '0') then setFE '1'; -- Iraming error
elseloadRDR '1'; end iI; -- load recv data register
end iI;
end iI;
end case;
end process;
Rcvrupdate: process (sysclk, rstb)

Begin

iI (rstb '0') then state IDLE; BclkX8Dlayed '0';
ct1 0; ct2 0;
elsiI (sysclk'event and sysclk '1') then
state nextstate;
iI (clr1 '1') then ct1 0; elsiI (inc1 '1') then
ct1 ct1 1; end iI;
iI (clr2 '1') then ct2 0; elsiI (inc2 '1') then
ct2 ct2 1; end iI;
iI (shItRSR '1') then RSR RxD& RSR(7 downto 1); end iI;

-- update shiIt reg.

iI (loadRDR '1') then RDR RSR; end iI;
BclkX8Dlayed BclkX8; -- BclkX8 delayed by 1 sysclk
end iI;
end process;
endrcvr;


(d)VHDL Code for Baud Rate Generator
libraryieee;
use ieee.stdlogic1164.all;
useieee.stdlogicunsigned.all; -- use '' operator, CONVINTEGER Iunc.
entityclkdivider is
port(Sysclk, rstb: in stdlogic;
Sel: in stdlogicvector(2 downto 0);
BclkX8: buIIer stdlogic;
Bclk: out stdlogic);
endclkdivider;

architecturebaudgen oI clkdivider is
signal ctr1: stdlogicvector (3 downto 0): "0000"; -- divide by 13 counter
signal ctr2: stdlogicvector (7 downto 0): "00000000"; -- div by 256 ctr
signal ctr3: stdlogicvector (2 downto 0): "000"; -- divide by 8 counter
signal Clkdiv13: stdlogic;

begin

process (Sysclk) -- Iirst divide system clock by 13
begin
iI (Sysclk'event and Sysclk '1') then
iI (ctr1 "1100") then ctr1 "0000";
else ctr1 ctr1 1; end iI;
end iI;
end process;

Clkdiv13 ctr1(3); -- divide Sysclk by 13
process (Clkdiv13) -- clkdivdr is an 8-bit counter
begin
iI (risingedge(Clkdiv13)) then
ctr2 ctr2 1;
end iI;
end process;

BclkX8 ctr2(CONVINTEGER(sel)); -- select baud rate
process (BclkX8)
begin
iI (risingedge(BclkX8)) then
ctr3 ctr3 1;
end iI;
end process;
Bclk ctr3(2); -- Bclk is BclkX8 divided by 8
endbaudgen;

APPENDIX-B
RTL

UART

References:

1. www.wikipedia.org
2. www.google.com
3. VHDL Primer by J. Bhasker
4. The 8086 icroprocessors byBurchandi