Application Form

(Tick the appropriate Boxes) (FILL IN CAPITAL LETTERS)

A Hands-on-training Experience in

VLSI Design

Name: Category: Student

Faculty

Industry

College / Organizations Name: Address for Correspondence:

26th 30th December 2011

Phone/Mobile: Email: Educational Qualification Highest Degree: College Name: Subject / Specialization: Grade / Division: Forwarding remark of the Head of the Department / Institute

Dept. of Applied Electronics & Instrumentation & Electronics and Tele-Communication Engineering

Signature (with seal)

Silicon Institute of Technology Bhubaneswar-751 024.

Course Objective
FEES: Very Large Scale integrated Circuits (VLSI) have become the prime medium of realization of modern Electronic Systems. There has been a great thrust to train professionals in the VLSI Design to meet the requirements of semiconductor industry. CMOS concepts have become the key of VLSI & ULSI for highperformance computing and other engineering applications. The main objective of this course is to train students & Professionals with hands on experience on the software and CAD tools used for VLSI design. Student 300/-

Information
Faculty 500/Industry 500/-

Please note that Special Discount will be given if more than 2 Faculties/Students register from the same institute. Registration Fee Includes: Registration Manual, Daily Tea & Lunch, and Certificate. Kit, Lab

Syllabus As Per BPUT and many more

1. Tanner Design Flow, Schematic and Layout of NAND, NOR, CMOS Inverter, DYNAMIC Logic using 0.35 micron Technology (i) Schematic & Layout Simulation (ii) Calculation of Delay Parameters (PHL, PLH, P) (iii) Calculation of Noise Margin (NMH, NML) (iv) Calculation of Avg. Power (v) Effect of Noise Margin on Variation of Vdd and Temperature 2. FPGA Design Flow using Xilinx ISE 10.1 (i) VHDL Programming on Full Adder, Multiplexer, Decoder, Seven Segment Display, Counter, PRBS Generator, Accumulator (ii) Behavioral Simulation, Synthesis, Post Place & Rout Simulation, Test bench (iii) Calculation of Power (iv) Configure FPGA and testing. Chip Debugging using Chipscope Pro. 3. Intro to CADENCE TOOL.

Mode of Payment: Register yourself by filling the Application form and send it to the below mentioned address on or before 22nd Dec 2011. Payment should be done in CASH (in the office of ENTC Dept, to Mr. Sujit Jena) at the time of commencement of course or before. For further details please contact: Sushant Kumar Pattnaik : 9437082906 (sushanta.pattnaik@silicon.ac.in) Debasish Nayak : 9778997975 (dnayak@silicon.ac.in) Aradhana Raju : 9438082747 (aradhana.raju@silicon.ac.in) Website : http://www.silicon.ac.in

Mailing Address: Coordinator, VLSI Design Dept. of ENTC Silicon Institute of Technology, Patia Bhubaneswar-751 024, INDIA.

Note

VLSI CAD Tools to be used:

Tanner tools, Xilinx ISE, Tanner, and CADENCE

Please mention on the envelope "APPLICATION FOR TRAINING PROGRAM ON VLSI Design