LATEST VLSI IEEE PROJECTS

1. An Efficient Implementation of Floating Point Multiplier (IEEE-2011) 2. A Distributed Canny Edge Detector And Its Implementation on FPGA(IEEE-2011) 3. A blind digital watermarking algorithm based on wavelet transform(IEEE-2011) 4. Design and Simulation of UART Serial Communication Module Based on VHDL(IEEE-2011) 5. Design and VLSI Implementation of high-performance Face-Detection Engine for Mobile Applications(IEEE-2011) 6. Design and Implementation of Area-optimized AES based on FPGA(IEEE-2011) 7. Design of High Speed Configurable Booth Multiplier(IEEE-2011) 8. Digital Watermarking Using Bidimensional Empirical Mode Decomposition(IEEE2011) 9. Face Detection And Recognition Method Based On SKIN COLOR And DEPTH INFORMATION(IEEE-2011) 10. High Speed FPGA Design of Complex Multiplier Using Vedic Mathematics(IEEE2011) 11. A New Reversible Design of BCD Adder(IEEE-2011) 12. Design and Implementation of high speed Digital FIR FILTER Based On High Speed Multipliers And Adders On FPGA(IEEE-2011) 13. Feature Extraction of Digital Aerial Images by FPGA based Implementation Of Edge Detection Algorithms(IEEE-2011) 14. An Efficient Architecture Design for VGA Monitor Controller (IEEE-2011) 15. An Implementation of a 2D FIR FILTER Using the Signed-Digit Number System(IEEE-2011) 16. Design and Characterization of Parallel Prefix Adders using FPGAs(IEEE-2011) 17. FPGA based FFT Algorithm Implementation in WiMAX Communications System(IEEE-2011) 18. FPGA Design of AES Core Architecture for Portable Hard Disk(IEEE-2011) ADR HR SERVICES, PLOT NO 216, B BLOCK AMEER ESTATES, BESIDE ICICI BANK SR NAGAR, HYDERABAD. CONTACT 040-66442255,56,57, EMAIL: academics@adrgroup.in

19. FPGA Implementation of RS232 to Universal serial bus converter(IEEE-2011) 20. Image Encryption Based On AES Key Expansion(IEEE-2011) 21. Curve Fitting Algorithm FPGA implementation (IEEE-2011) 22. Design of Serial Communication Interface Based on FPGA (IEEE-2011) 23. Design and Implementation of an FPGA-based Real-Time Face Recognition System (IEEE-2011) 24. Design and FPGA Implementation of Weighted Majority logic Decoders (IEEE2011) 25. A Pipeline VLSI Architecture For HIGH-SPEED Computation Of The 1-D Discrete Wavelet Transforms.(IEEE-2011) 26. Design and FPGA Implementation Of Modified Distributive Arithmetic Based DWT-IDWT Processor for Image Compression(IEEE-2011) 27. 16- Bit RISC Processor Design For Convolution Application. (IEEE-2011) 28. A Flexible Hardware Implementation of SHA-1 And SHA-2 Hash Functions. (IEEE-2011) 29. Efficient Iterative Techniques For Soft Decision Decoding of reed-solomon Codes. (IEEE-2011) 30. Efficient Pattern Matching Algorithm For Memory Architecture. (IEEE-2011) 31. Efficient Codec Designs For Crosstalk Avoidance Codes Based On Numeral Systems. (IEEE-2011) 32. Lossless Implementation Of Daubechies 8-TAP Wavelet Transform. (IEEE2011) 33. Performance Analysis Of Integer Wavelet Transform For Image Compression. (IEEE-2011)

ADR HR SERVICES, PLOT NO 216, B BLOCK AMEER ESTATES, BESIDE ICICI BANK SR NAGAR, HYDERABAD. CONTACT 040-66442255,56,57, EMAIL: academics@adrgroup.in

34. A Light Weight High-Performance Fault Detection Scheme for The Advanced Encryption Standard Using Composite Fields. (IEEE-2011) 35. Building An AMBA AHB Compliant Memory Controller. (IEEE-2011) 36. Direct Digital Frequency Synthesizer Using Nonuniform Piecewise-Linear Approximation. (IEEE-2011) 37. High-Accuracy Fixed-width Modified Booth Multipliers For Lossy Applications. (IEEE-2011) 38. An Fpga-Based Architecture For Linear And Morphological Image Filtering. (IEEE-2011) 39. Design Of SHA-1 Algorithm Based on FPGA. (IEEE-2011) 40. Fpga Based Real-Time Adaptive Fuzzy Logic Controller. (IEEE-2011) 41. Image Edge Detection Based On FPGA. (IEEE-2011) 42. VLSI Architecture for Genetic Algorithm and Simulated Annealing. (IEEE2011) 43. Design And Implementation of CORDIC Algorithm. (IEEE-2011) 44. Design And Implementation of PSO (Particle Swarm Optimization). (IEEE2011) 45. Design and implementation of SPIHT Algorithm For Image Compression. (IEEE-2011)

ADR HR SERVICES, PLOT NO 216, B BLOCK AMEER ESTATES, BESIDE ICICI BANK SR NAGAR, HYDERABAD. CONTACT 040-66442255,56,57, EMAIL: academics@adrgroup.in