DESIGN OF DIRECTION FINDER and PULSE PROCESSOR BOARD

A project report submitted in partial fulfillment of the requirements for the degree MASTER OF TECHNOLOGY with specialization DIGITAL SYSTEMS AND SIGNAL PROCESSING

by
JAGADEESH BABU D (1220410112) Under the Guidance of Mr. SRINIVAS Project manager, Radix Microsystems And Mr. ALLURI SREENIVAS Associate Professor in

ECE DEPARTMENT

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING GITAM INSTITUTE OF TECHNOLOGY GITAM UNIVERSITY VISAKHAPATNAM 530 003 (2010-2012)

CERTIFICATE

This is to certify that the project report entitled DESIGN OF DIRECTION FINDER and PULSE PROCESSOR BOARD USING FPGA is the bonafied record of project work carried out by JAGADEESH BABU D bearing the Regd. No.1220410112, submitted in the partial fulfillment of the requirements for the second year, first semester of the degree of Master of Technology in Digital Systems and Signal Processing during the academic year 2011-2012.

Mr. ALLURI SREENIVAS Associate Professor

Dr. V Malleswara Rao Head of the Department Department of ECE

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ABSTRACT

The main aim of the project is to provide the minimal functions necessary to provide an Ethernet interface with the least resources used. For this a virtex-4 FPGA is used as it offers exclusively in high performance flip-chip BGA packages that are optimally designed for improved signal integrity and jitter. The purpose of the Ethernet Lite MAC is that it supports the IEEE Std. 802.3 Media Independent Interface (MII) to industry standard Physical Layer (PHY) devices and communicates to a processor via a Processor Local Bus (PLB) interface. The design provides a 10 Megabits per second (Mbps) and 100 Mbps (also known as Fast Ethernet) Interface. The protocol of Ethernet is that the data is encapsulated in frames. The fields in the frame are transmitted from left to right. The bits within the frame are transmitted from left to right (from least significant bit to most significant bit unless specified otherwise).

References [1] Richard C. Seals,G. F. Whapshott Programmable Logic PLDs and FPGAs . [2] www.xilinx.com.

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CONTENTS

ABSTRACT 1. INTRODUCTION 1.1 Ethernet/IEEE 802.3 Comparison 1.2 Ethernet and IEEE 802.3 Frame Formats 1.3 100-Mbps Ethernet 1.4 Gigabit Ethernet 1.5 Gigabit Ethernet Specification 1.6 Migrating to Gigabit Ethernet 2. ETHERNET OVERVIEW 2.1 INTRODUCTION
2.2 SPECIFICATIONS 2.3 FUNCTIONAL DESCRIPTION 2.3.1 POWER PC 405 PROCESSOR 2.3.2 TIMER RESOURCES 2.3.3 EXTERNAL RESOURCE CONTROLLERS

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FUNCTIONAL OVERVIEW 3.1 VOLTAGE REGULATORS (TPS54610) 3.2 OPTO ISOLATORS (6N140) 3.3 RELAY DRIVERS (PS7206) 3.4 PLATFORM FLASH (XCF32P)
3.5 LINEAR FLASH (MT28F320J3RG-11ET) 3.6 DDR SDRAM (HYB25D26516OBT) 3.7 SYSACE CONTROLLER (XCCACE) 3.8 ETHERNET TRANSCEIVERS (M88E1111)
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3.9 CPLD (XC95144XL)

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