RAGHUVEER AUSOORI

E-mail raghuveer.ausoori@gmail.com Cell(732) 421 2462 243 Buena Vista Avenue Sunnyvale CA - 94086, United States

SUMMARY OF SKILL SET

Self-motivated and quick learning Hardware Engineer with three years of related work experience in logic design using both Verilog and VHDL, skilled in certain aspects of ASIC design with particular expertise in DFT design. Demonstrated ability for hard work with an U.S. provisional patent on a DFT algorithm to improve testability of the circuit and reduce the test vector size. Experienced software developer with particular expertise in C, C++, PERL and Shell.

RELATED WORK EXPERIENCE

Stanford Linear Accelerator Center, Menlo Park, CA June 2010 Present Electronics Engineer Develop custom FPGA rmware in VHDL to be used in DAQ systems for research projects. Synthesize, map, burn and debug the design in the Xilinx Virtex FPGA. Maintain the software that communicates with the rmware Heavy Photon Project Programmed the rmware to support 5 custom ASIC chips Congured the ASICs through the rmware using I2C protocol Controlled the clocking and triggering of the chips using user settings Interfaced with ADC to convert the incoming samples from the chips Transmitted the converted data to the software using PGP2 protocol KpixCon Project Redesigned the existing rmware to support 32 custom ASICs simultaneously Communicated with the software through a 1Gig Fiber Optic Ethernet channel using the UDP Protocol Improved data transfer speeds by 10X with the new rmware Added new features to the existing software such as reading in the default settings from an XML le Spectral Design and Test, Inc., NJ April 2009 March 2010 CAD Programmer Develop the Entropy tool that inserts test points and partial-scan ip-ops into the chip design, thereby making it easy to test in a lesser amount of time

Developed the prototype Entropy tool in C language as part of my MS Thesis Involved in moving the Entropy tool to C++ language with support for advanced features Used TetraMax to prove that the test vectors generated after the insertion of test hardware by the entropy tool is lesser than the test vectors required for a circuit with no test hardware

Virage Logic Corporation, Hampton, NJ July 2008 - January 2009 Co-op Engineer Develop a ow to verify power management circuitry and test the new characterization modeling ow Power Flow Verication Project Proved that a memory circuit with the power management circuitry is functional according to the specication using Verilog Modeled the memory circuit to create different behaviors detectable at the external outputs when the power management is activated and deactivated Used Verilog to create an automated ow to augment the existing design ow Characterization Modeling Project Involved in developing a design tool that creates a circuit model for characterizing memories of various sizes. Optimized a complex memory circuit into concise model circuit that can be simulated in minimal time without the loss of accuracy

WINLAB, Rutgers University,North Brunswick, NJ Intern

Jan 2007 - Aug 2007

Designed the 802.11 MAC Layer for the transmitter of a cognitive radio platform Designed the architecture of the hardware and implemented the design using VHDL Validated and tested the design using ModelSim

EDUCATION
Rutgers University, New Brunswick, NJ Master of Science, Computer Engineering, Oct 2009 Anna University, Chennai, TN, India Bachelor of Engineering, Electronics & Instrumentation Engg. (EIE), May 2006 GPA: 4.0/4.0 GPA: 3.5/4.0

PUBLICATIONS/PATENTS
M.S. Thesis: "Information Theoretic and Spectral Methods of Test Point, Partial-Scan, and Full-Scan Flip-Flop Insertion to Improve Integrated Circuit Testability", a new Design-for-Testability (DFT) algorithm to simultaneously insert full scan ip-ops, partial scan ip-ops and test points into sequential circuit to improve the circuit testability to nearly 100% stuck-at fault coverage and reduce test application time and test volume. U.S. Provisional Patent application number 61/109245 led on October 29, 2008 for the above-mentioned work at Rutgers University

HONORS
Awarded Teaching Assistantship for Data Structures and Algorithms in Spring 2009 and for Introductory VLSI Design in Fall 2007 by the ECE Department of Rutgers University Received the Academic Excellence award from Anna University for ranking #1 in the Electronics and Instrumentation Engineering Department during Fall 2003 Received Community Shield in India for continuous excellence in academia in the year 2006

SKILLS
Verilog, VHDL, Cadence design suite (NC-Verilog, Virtuoso Symbol & Layout Editor, Spectre), Synopsys design suite (VCS, Design Vision), Synplify, ModelSim, Xilinx ISE, ChipScope, TetraMAX, C, C++, PERL, Shell

DESIGN PROJECTS
Bluetooth System-on-Chip Developed a Bluetooth System-on-Chip for cashless and cardless billing applications Designed the 32-bit non-pipelined microprocessor with DFT hardware using Verilog Synthesized and simulated the design using the Synopsys Design suite and VCS simulator Tested the design for stuck-at fault coverage using Wavelet Automatic Test Pattern Generator Full custom layout of the datapath and memory was developed using Cadence layout tools Used the Silicon Ensemble tool for the automatic layout and routing of random logic blocks Performed Analog simulation of extracted circuits using Spectre for nal timing check Full Scan and Boundary Scan Hardware with JTAG controller were inserted to increase the fault coverage Test Point Insertion in Non-Scan BIST Modied the ISCAS '89 benchmark s5378 to insert BIST hardware Parsed the circuit using the RUTMOD circuit parser and modied the design using the C language Random patterns were generated using an LFSR and signature analysis was done using a MISR Simulated the circuit with the HOPE fault simulator Test points were inserted based on the undetected fault list to increase the fault coverage