Professional Documents
Culture Documents
GR-DVL9500 NTSC/PAL
December 1999
INDEX
SECTION 1 EXPLANATION OF NEW TECHNOLOGIES ADOPTED FOR GR-DVL9500 SERIES
1.1 CONCEPTION TO DEVELOP GR-DVL9500 SERIES .......................................................1-1 1.2 OUTLINE OF DOUBLE-SPEED VIDEO RECORDING (SHOOTING)................................1-2 1.2.1 Double-speed recording in brief .....................................................................................1-2 1.2.2 Outline of double-speed video recording and playback of double-speed recorded video......................................................................1-2 1.3 PS CCD.............................................................................................................................1-4 1.3.1 Principle of CCD operation in double-speed shooting ....................................................1-4 1.3.2 Readout area and recording picture in double-speed shooting ......................................1-6 1.4 VIDEO SIGNAL OF DOUBLE-SPEED SHOOTING (RECORDING) ..................................1-6 1.4.1 Video signal of double-speed shooting (1) .....................................................................1-6 1.4.2 Video signal of double-speed shooting (2) .....................................................................1-6 1.4.3 Video signal in slow playback.........................................................................................1-7
INDEX-1
2.7 FM (IC4302) ......................................................................................................................2-24 2.7.1 FM (IC4302) pin assignment..........................................................................................2-24 2.7.2 FM (IC4302) block diagram............................................................................................2-25 2.7.3 FM (IC4302) pin functions..............................................................................................2-26 2.8 DVIO (IC3202) ...................................................................................................................2-28 2.8.1 DVIO (IC3202) pin assignment and block diagram ........................................................2-28 2.8.2 DVIO (IC3202) pin functions ..........................................................................................2-29 2.9 PLL (IC3201) .....................................................................................................................2-33 2.9.1 PLL circuit description....................................................................................................2-33 2.9.2 PLL (IC3201) pin assignment.........................................................................................2-34 2.9.3 PLL (IC3201) block diagram ..........................................................................................2-34 2.9.4 PLL (IC3201) pin functions.............................................................................................2-35 2.10 SHUFFLE MEMORY (IC3002).........................................................................................2-36 2.10.1 Shuffle memory (IC3002) pin assignment ....................................................................2-36 2.10.2 Shuffle memory (IC3002) pin functions ........................................................................2-37 2.11 COMPRESS/AUDIO/SHUFFLE (CAS) (IC3001)..............................................................2-39 2.11.1 CAS (IC3001) pin assignment and block diagram ........................................................2-39 2.11.2 CAS (IC3001) pin functions..........................................................................................2-40 2.12 ECC/DCI/ATF (EDA) (IC3003) .........................................................................................2-43 2.12.1 EDA (IC3003) pin assignment and block diagram ........................................................2-43 2.12.2 EDA (IC3003) pin functions..........................................................................................2-44 2.13 DYNAMIC DRAM (DRAM) (IC3004) ................................................................................2-48 2.13.1 DRAM (IC3004) pin assignment...................................................................................2-48 2.13.2 DRAM (IC3004) block diagram ....................................................................................2-48 2.13.3 DRAM (IC3004) pin functions ......................................................................................2-49 2.14 VITERBI A/D (IC3005) .....................................................................................................2-51 2.14.1 VITERBI A/D (IC3005) pin assignment and block diagram...........................................2-51 2.14.2 VITERBI A/D (IC3005) pin functions ............................................................................2-51 2.15 PRE/REC (IC3502)..........................................................................................................2-52 2.15.1 PRE/REC (IC3502) pin assignment and block diagram ...............................................2-52 2.15.2 PRE/REC (IC3502) pin functions .................................................................................2-53 2.16 PB EQUALIZER (IC3501)................................................................................................2-55 2.16.1 PB_EQ (IC3501) pin assignment and block diagram ...................................................2-55 2.16.2 PB_EQ (IC3501) pin functions .....................................................................................2-56 2.16.3 PB EQ circuit ...............................................................................................................2-58 2.17 EVR DA CONV. (IC3503).................................................................................................2-59 2.17.1 DAC (IC3503) pin assignment .....................................................................................2-59 2.17.2 DAC (IC3503) block diagram .......................................................................................2-59 2.17.3 DAC (IC3503) pin functions .........................................................................................2-60
INDEX-2
2.18 ENV D/A CONV. (IC1201)................................................................................................2-61 2.18.1 ENV D/A CONV. (IC1201) pin assignment ...................................................................2-61 2.18.2 ENV D/A CONV. (IC1201) block diagram.....................................................................2-61 2.18.3 ENV D/A CONV. (IC1201) pin functions .......................................................................2-62 2.19 DIGITAL INTERFACE (IC8001) .......................................................................................2-63 2.19.1 Digital IF (IC8001) pin assignment and block diagram .................................................2-63 2.19.2 Digital IF (IC8001) pin functions ...................................................................................2-64 2.20 MSD CPU (IC1401) .........................................................................................................2-68 2.20.1 MSD CPU (IC1401) pin assignment.............................................................................2-68 2.20.2 MSD CPU (IC1401) pin functions.................................................................................2-69 2.21 SYSCON CPU (1001)......................................................................................................2-73 2.21.1 SYSCON CPU (1001) pin assignment .........................................................................2-73 2.21.2 SYSCON CPU (IC1001) pin functions..........................................................................2-74 2.22 MDA (IC1601)..................................................................................................................2-78 2.22.1 MDA (IC1601) pin assignment .....................................................................................2-78 2.22.2 MDA (IC1601) block diagram .......................................................................................2-79 2.22.3 MDA (IC1601) pin functions .........................................................................................2-80 2.23 ON SCREEN (OSD) (IC1002)..........................................................................................2-82 2.23.1 OSD (IC1002) pin assignment .....................................................................................2-82 2.23.2 OSD (IC1002) block diagram .......................................................................................2-82 2.23.3 OSD (IC1002) pin functions .........................................................................................2-83 2.24 FOCUS & ZOOM DRIVER (IC4851) ................................................................................2-84 2.24.1 Focus & Zoom driver (IC4851) pin assignment and block diagram ..............................2-84 2.24.2 Focus & Zoom driver (IC4851) pin functions ................................................................2-85 2.25 VIDEO OOUTPUT DRIVER (IC3701) ..............................................................................2-86 2.25.1 VIDEO OOUTPUT DRIVER (IC3701) pin assignment and block diagram....................2-86 2.25.2 VIDEO OOUTPUT DRIVER (IC3701) pin functions .....................................................2-87 2.26 VF LCD DRIVER (IC7401)...............................................................................................2-88 2.26.1 VF LCD DRIVER (IC7401) pin assignment and block diagram ....................................2-88 2.26.2 VF LCD DRIVER (IC7401) pin functions .....................................................................2-89 2.27 LCD MONITOR DRIVER (IC7301)...................................................................................2-91 2.27.1 LCD MONITOR DRIVER (IC7301) pin assignment ......................................................2-91 2.27.2 LCD MONITOR DRIVER (IC7301) block diagram........................................................2-92 2.27.3 LCD MONITOR DRIVER (IC7301) pin functions .........................................................2-93 2.28 AUDIO AMP (IC2201)......................................................................................................2-95 2.28.1 AUDIO AMP (IC2201) pin assignment .........................................................................2-95 2.28.2 AUDIO AMP (IC2201) block diagram ...........................................................................2-96 2.28.3 AUDIO AMP (IC2201) pin functions .............................................................................2-97 2.29 16BIT A/D, D/A CONV. (IC2101)......................................................................................2-98 2.29.1 16BIT A/D, D/A CONV. (IC2101) pin assignment and block diagram ...........................2-99 2.29.2 16BIT A/D, D/A CONV. (IC2101) pin functions .............................................................2-99
INDEX-3
2.30 REGULATOR CTL (IC6101) ............................................................................................2-100 2.30.1 REGULATOR CTL (IC6101) pin assignment................................................................2-100 2.30.2 REGULATOR CTL (IC6101) pin functions ...................................................................2-101
INDEX-4
1-1
1.2
1.2.1 Double-speed recording in brief High-speed shooting (video recording) exceeding 60 frames per second has been utilized for industrial and scientific purposes such as observation and analysis of high speed phenomena, on-the-spot broadcasting of sports, etc. Video cameras used for the aforementioned purposes are capable of ultra high speed shooting such as from 180 frames per second to one hundred million frames per second. Since such the equipment is very expensive because special pickup device and special recording device are used in it, it hasn't been popularized as video apparatus for general use. The GR-DVL9500 series are a new camcorder with an attractive function added, which enables the user easily to check his swing form at golf, to analyze natural phenomenon such as milk crown when a drop of milk splashes, to observe action of animal, bird, etc. such as flutter of wings, all of them cannot be observed by the naked eye. Regarding the CCD that is the major pickup device of the video camera, that of the GR-DVL9500 series sequentially scans signals of two-dimensionally arranged photodiodes and outputs them as video signal as shown in Fig. 1-2-1. Although a high-speed video camera can be realized by raising the scan frequency, there are many problems to develop a high-speed video camera by such the means, that is to say, signal frequency must be raised with rise of scan frequency, signal processing circuit of the camera needs large-scale improvement to deal with high frequency band as well as high band recording system to record such high frequency signals.
Undesired charge area (111 lines)
Photodiode
V1 V2 V3
222lines
CH1
1.2.2 Outline of double-speed video recording and playback of double-speed recorded video Fig. 1-2-3 illustrates the overall configuration of the double-speed video recording and double-speed recorded video playback system. This system is mainly composed of the camera section, special effector section and recording/playback processing section (1) The PS-CCD in which the undesired charge drain is incorporated is adopted as the pickup device of the camera section. In the double-speed recording mode, approximately half of the CCD area is scanned in half a period (1/120 second) of the standard time to output video signal while unnecessary charges are discharged through the undesired charge drain. (2) After that, image data of two fields (sub fields) that are respectively obtained by scanning half the CCD area are combined by the special effector section to be the upper half and lower half of a picture of one field. The field rate of the picture processed by the special effector section is 60 Hz that is the same as the standard recording mode, therefore, the image data is recorded on video tape by the recording/playback section in the same manner as the standard recording.
1-2
(3) In playback, double-speed recorded video can be played back in the slow playback mode or slow zoom playback mode. There is a point to be attended to, that is signals recorded on the DV format. When such the signal is played back in the slow motion mode, the tape runs for 10 tracks and then the tape travel is once suspended from playback by the servo operation, and playback is resumed for the next 10 tracks, because video signals recorded on the DV format are constructed in the form of ten tracks per one frame. Namely, playback of DV formatted video tape is constructed by repetition of 10-tracks playback under the servo control. The GR-DVL9500 sreies realizes the slowmotion playback by means of such the servo control. (For preventing video tape from deterioration, the GR-DVL9500 series limits continuous slow-motion playback time to 120 seconds at maximum.) (4) If double-speed recorded video is played back in the slow-motion mode (1/10 speed of the standard) by this function, motion of image is 1/10 as slow as the real motion. However, the user can enjoy very smooth slow motion in the slow playback mode because each field is renewed every 1/60 second.
1/10-speed slow playback
Camera section
111 Lines
VIDEO 1 VIDEO 2
REC/PB section
PLAY
PS CCD
222 Lines 111 Lines
CDS/AGC ADC
Y/C AUTO
FMC (EIS)
REC
VTR
HD/VD/FRVD
VD/VD2
HD/VD/FRVD
VF_BLK
TG
13.5M/27M
SSG
VF
VF masking processing
Masking VF/Blanking
1/120 sec
1-3
1.3
PS CCD
The principle of the PS CCD for the GR-DVL9500 are illustrated in Fig. 1-3-1. This PS CCD is characterized by two points of the following. (1) Two horizontal transfer CCD's are incorporated inside. (2) An undesired charge drain is installed under the second horizontal transfer CCD.
V1 V2 V3 V1: Vertical register transfer clock V2: Vertical register transfer clock V3: Vertical register transfer clock H1: Horizontal register transfer clock H2: Horizontal register transfer clock HOB: Drain gate drive clock
CH1 CH2
Photodiode
Fig. 1-3-1 Illustration of principle of PS CCD (1) In the standard shooting (video recording) mode, high potential is applied to V3 through the vertical blanking period in order to read charges in the vertical transfer CCD out of photodiodes of the pickup device. After that, charges are vertically transferred to the horizontal CCD by two lines every H, namely, charges are read out by a sequential charge readout system. Differently from the conventional four-phase driven vertical two-pixels mixed readout CCD, this CCD does not read pixel charges mixedly between the photodiode and vertical transfer CCD but reads signals of all photodiodes individually at shutter speed of 1/60 second in the standard shooting mode. As well as the GR-DVL9000 video camera, the whole complementary color pixels independent readout system is adopted for processing signals of the CCD in order to realize high resolution color video. 1.3.1 Principle of CCD operation in double-speed shooting In the double-speed shooting mode, two vertically separate signals are input in a period of 1 field. Generally, transfer rate of the horizontal transfer CCD is pointed out as a problem in high-speed shooting. In the GR-DVL9500 series, data read out of the CCD is partially discharged into the undesired charge drain installed under the second horizontal transfer CCD, therefore, high-speed shooting is realized without change of the transfer rate of the horizontal transfer CCD. Pixels to be actually recorded are those of 111 lines of odd fields and 111 lines of even fields, namely pixels of 222 lines are recorded in total. Fig. 1-3-2 illustrates a CCD drive sequence in double-speed shooting, however, the illustration refers to 16 lines only for a convenience of explanation. (1) Charges of photodiodes are transferred to the horizontal transfer CCD by (b) vertical transfer 1 and (c) vertical transfer 2. (2) In the process of (d) vertical transfer 3, 4, horizontal transfer pulse is input and data signal is output in the standard shooting mode, however, in the high-speed shooting mode charges of the lines 1 to 4 are regarded as undesired signals. Therefore, signals of the lines 1 and 2 are discharged out of the undesired charge drain under the horizontal transfer CCD in the process of (d) vertical transfer 3, 4.
1-4
(3) In the standard shooting mode, horizontal transfer pulse is input and data signal is output in the process of (d) vertical transfer 3, 4, however, in the high-speed shooting mode charges of the lines 1 to 4 are regarded as undesired signals. Therefore, signals of the lines 1 and 2 are discharged out of the undesired charge drain under the horizontal transfer CCD in the process of (d) vertical transfer 3, 4. (4) In the same manner, charges of the line 5 and line 6 are transferred in the process of (e) vertical transfer 5, 6. (5) In the process of (f) horizontal transfer 1, charges for 1 H are horizontally transferred and signals for 1H are output from the CCD. (6) As a result of repetition of the above-mentioned operation, charges of readout area are output and undesired charges are disposed through the undesired charge drain.
line 16 line 15 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 line 6 line 5 line 4 line 3 line 2 line 1 line 16 line 15 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 line 6 line 5 line 4 line 3 line 2 line 1
Readout area
line 16 line 15 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 line 6 line 5 line 4 line 3 line 2 line 1
line 16 line 15 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 line 6 line 5 line 4 line 3
line 16 line 15 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 line 6 line 5
line 16 line 15 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7
line 6 line 5
line 1 line 2
line 3 line 4
1.3.2 Readout area and recording picture in double-speed shooting In practical operation, charges just a half of the readout area cannot be read out because it takes a certain time to drain undesired charge as mentioned in the preceding paragraphs (1) to (3). For the GR-DVL9500 sereies charges of total 222 lines are specified to be valid, namely, 111 lines are valid for the first half of the readout area and another 111 lines are valid for the second half of the readout area. Time needed to drain undesired charge is for 15 lines (H) respectively.
1.4
1.4.1 Video signal of double-speed shooting (1) In the double-speed shooting mode, a picture that is actually recorded comprises of a couple of vertically halved pictures as shown in Fig. 1-3-3. Therefore, if video recorded by the GR-DVL9500 series are played back by another DVC or it is output in the EE mode, every picture (frame) is sandwiched by two frames that are 1/60 seconds ahead of and behind the playback picture respectively. In the slow-motion playback (at 1/10 speed of the standard), the upper-half picture and lower-half picture are alternately played back for five fields respectively in the center part of the VF screen.
Picture output on the VF screen is blanked by the lower half. (A) Recorded picture (B) Picture appearing on the VF screen In the slow-motion (1/10 speed) playback, the upper-half picture and lower-half picture are alternately played back for 5 fields respectively in the center of the VF screen. (C) Picture played back by DVC other than GR-DVL9500 series (D) Picture played back by GR-DVL9500 series
Fig. 1-4-1 Video signal of double-speed shooting (1) 1.4.2 Video signal of double-speed shooting (2) Fig. 1-4-2 shows video signals in one vertical synchronizing period in both the standard playback and double-speed playback modes. In the double-speed shooting (recording), undesired charges are discharged to the undesired charge drain through the vertical transfer CCD at a high speed.
1-6
(a)
(b)
(c) (a)
(b)
(c)
1/20
Fig. 1-4-2 Video signal of double-speed shooting (2) 1.4.3 Video signal in slow playback When video recorded in the double-speed shooting mode is played back in the slow-motion playback mode, pictures (fields) are sorted, edited and controlled for the vertical positioning by the DSP and FMC IC, because each playback picture is composed of two different pictures of the upper-half and lower-half. As shown in Fig. 1-4-3, video signals recorded in the upper half (A) of the first field period are output on the monitor screen for 1/60 second by 5 times (5/60 second), and then signals of the lower-half (B) are output on the screen for 10/60 second. In other words, video (a frame) recorded for 1/60 second is played back for 1/6 second in the slow playback mode.
Field No. 1 5 6 10
A 1/60
A 1/60
B 1/60
B 1/60
Transfer system Optical size Effective pixels Total Horizontal register clock Chip size Unit cell size Optical black Dummy bits Color filter
Interline transfer CCD 1/3 inch size format NTSC 724(H) 494(V) approx.360k pixels *PAL 724(H) 582(V) approx.420k pixels NTSC 758(H) 504(V) approx.380k pixels *PAL 758(H) 592(V) approx.450k pixels 13.5MHz (DVC reference clock) 6.40mm (H) 5.05mm (V) NTSC 6.75m m (H) 7.40m m (V) *PAL 6.85m m (H) 6.25m m (V) Horizontal Front 6 / Back 28 Vertical Front 8 / Back 2 Horizontal 16 Vertical 5 W,G,Cy,Ye complementary filter
8 6 12pin H 28
Fig. 2-1-1 Optical black assignment 2.1.1 CCD pin assignment and block diagram
Cgg2
Cgg1
VHOLD
VOUT2
VOUT1
GND
11
10
Cy Wh Vertical-CCD Ye Gr Cy Wh
Ye Gr Cy Wh Ye Gr
Ye Gr Cy Wh Ye Gr
HIG1
1
HIS
V1
V2
V3
12
13
14
15
16
17
18
19
20
21
22
* Photo Sensor
SUB
H1
Vdd
RG
H2
VL
HHG1
HHG2
POG
VOG
HOB
2-2
2.1.3 3-Phase Drive Vertical CCD The vertical CCD performs reading and transmission independently without mixing all pixels in 1 field. First, the accumulated charge is read to the vertical CCD V3 and V2 by the read pulse SG (SG is superimposed with V2). Then, vertical transmission is performed twice in the 1 horizontal blanking period using the 3phase drive pulses V1, V2, and V3.
V-CCD V1 V3 V2 V1 V3 V2 V1 V3 SENSOR V1 V3 V2 V1 V3 V2 V1 V3 V2
SIGNAL CHARGE
Fig. 2-1-3 3-Phase drive vertical CCD 2.1.4 Transmission to Horizontal CCD from Vertical CCD It is necessary to prevent the signal charge of the next 1 line from being transmitted to the horizontal CCD until the transmission of the signal charge of the first line between the horizontal CCDs is completed. VHOLD is used as the buffer and VOG is used for reading from the buffer.
1st HCCD-1
V2
VHOLD VOG
H1 H2
HHG1
SIGNAL CHARGE
2.1.5 Transmission between Horizontal CCDs The first line signal charge is transmitted to the second horizontal CCD by transmission between horizontal CCDs. A gate (HHG2) for transmission between horizontal CCDs is provided for this purpose. To ensure both transmission efficiency between the horizontal CCDs and charge handled by the first horizontal CCD, the first horizontal CCD is divided into two. Transmission gates (HHG1) are also assigned between these two CCDs. The divided signal is mixed again in the final stage of the first horizontal CCD. The signal charge of the first line is transmitted to the channel below the HHG1 from the vertical CCD and moved to the channel below the next HHG2. When HHG2 becomes low bias, the signal charge is transmitted to the second horizontal CCD. After the signal charge of one line has been transmitted, the transmission of the signal charge of the second line starts. The signal charge of the second line is first transmitted to the channel below HHG1, split into two there, and transmitted to the first horizontal CCD-1 and first horizontal CCD-2.
V-CCD
1st HCCD-1 VOUT1 Compound Channel 1st HCCD-2 VOUT2 2nd HCCD
HHG1
HHG2
HHG1
H1
H2
H2
1st HCCD-2
HHG2
H2
H1
H1
2nd HCCD
H1 H2
2nd HCCD
H2 H1
H1 H2
HHG1
H1 H2
HHG2
H1 H2
HHG1
H1
H2
H2
1st HCCD-2
HHG2
H2
H1
2nd HCCD
H1 H2 Channel Stop
Fig. 2-1-7 Transmission of the second line signal charge 2.1.6 2-channel Output Horizontal CCD Outputs signals of two vertical lines simultaneously with the 2-stage horizontal register. As a result, signals are output from two output terminals (Vout 1, Vout 2) for the odd and even fields simultaneously in the 1/60 (*1/50) second period. Interlacing is performed by the frame memory control (FMC) performed later. 2.1.7 Pilot Signal Generator A reference signal called the pilot signal is output to channel A or channel B of the output of this CCD in the 1H period before the horizontal front OB. Then 2-channel pilot signal levels are compared at the stage before the Y/C circuit to correct the inconsistency caused by the difference of the paths between the channels. The pilot signal and output timing are generated by the pilot signal source bias HIS, pilot signal injection clock HIG1, and pilot signal output stage transmission clock POG.
2-5
VD
BLK
520
525 1 2 3 4 5
260
265
270
275
280
SG
V1 V2
493
1 3 5 7 1 3
493
1 3 5 7 1 3
Fig. 2-1-8 Drive timing chart (Vertical Sync) 2) Drive Timing Chart (Horizontal Sync)
HD/SYNC
1 86
BLK
858 1 112 128
CLK
1 21 1 1 7 1 1 21 21 1 14 1 1 18 1 1 8 1 1 1 1 28 1 5 1 1 16 41 22 1 21 1 7 1 7 36 30 21 1 1 21 21 1 13 1 1 21 8 14 1 1 21 21 1 1 21 21 1 7 14 1 1 1 21 14
V1 V2 V3 VHOLD VOG H1 H2
1 1
1 1 25
32
HHG1
HHG2
14
28
134
28
145
285
10
15
20
2.2
This IC is CCD head amplifier for digital camera. It features CDS (correlation double sampling), AGC, Sampling/Hold for A/D input, Blanking, Reference voltage for A/D and Output driver for A/D converter. 2.2.1 CDS AGC (IC5101/IC5102) pin assignment and block diagram CCDLEVEL AGCCONT
14
VRT BLK SW POWER SAVE CONT VRB DRV VRB
ICONT
GND1
24
23
22
21
20
19
18
17
16
BUF
VCC1
SHD
SHP
DIN
15
13
SH1
DC SHIFT
OB SW AGC CLP
CAM SH OFFSET
VRT DRV
DRV
10
11
12
VCC3
PBLK
PS
DRVOUT
Fig. 2-2-1 CDS AGC (IC5101/IC5102) pin assignment and block diagram
2-7
OFFSET
CLPOB
GND2
GND3
VRB
XRS
VRT
NC
AGCCLP
CLPDM
VCC2
PIN
2-8
2.3
T. G (IC5002)
This IC generates pulses to drive the PS CCD and timing pulses necessary for video signal process circuits. The main clock (27MHz) made by crystal X5001 and the 1/2 divided clock (13.5MHz) are sent to the SSG in DSP IC4301. The SSG makes HD, VD and FLD then send back to the TG. The pulses for the CCD are generated based on HD, VD, FLD and 13.5MHz. The shutter speed control information is supplied from the CAMERA CPU IC 4401 through the serial bus. Also the sampling and clamp pulses for CDS/AGC IC5101/IC5102, and the A/D converter clock (13.5MHz) for ACD IC4201/IC4202 are generated at here. 2.3.1 TG (IC5002) pin assignment
MODE2 TEST4 50 MODE STBY CLD2
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Vdd1 OSCI OSCO PS ED0 ED1 ED2 SMD1 SMD2 XSG XV2 XSUB Vss H1 H2 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
WEN
Vdd1
CKO
CLD
FLD
HDI
Vss
Vss
CKI
VDI
CL
ID PBLK XCPOB XCPDM RM Vdd1 Vss PSH2 PSH1 TEST3 XRST TEST1 NP XRS XSHD XSHP
Vdd1
Vss
VDD2
XV1
XVHOLD
XV3
Vss
RG
XHHG2A
XHHG2B
XHHG1B
2-9
XHHG1A
XPOG
XHIG1
XVOG
XHOB
2-10
2-11
2.4
V. DRIVER (IC4101)
The V.DRIVER is supplied with Vertical register transmission pulses (V1,V2,V3,VHOLD,VOG), Signal charge gate pulse (SG), Horizontal register transmission pulses (HHG1,HHG2) and Pilot signal control pulses (HIG,POG) from the TG IC5002. These pulses are converted to 2-state or 3-state levels in such a way as to drive the CCD. The signal charge gate pulse (SG) is overlapped onto the vertical register transmission pulses (V2). Also this IC has the amplifier for substrate voltage. 2.4.1 V. DRIVER (IC4101) pin assignment
SUBDC VSUB XSG XV2 TI1 HIG1 POG TI2 XSUB XVHOLD VM VHH VM VL VO2 HIGO POGO SUB VHH VM VL VHOLDO 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34
33 32 31 30 29 28 27 26 25 24 23
VDD XV1 XV3 XVOG STBY XHOB XHHG2-1 XHHG2-2 XHHG1-2 XHHG1-1 VL
12 13 14 15 16 17 18 19 20 21 22
43
X3.2
44
SUBDC
42 41 39 40 38 37 36
V02
HIGO
POGO
SUB
XVHOLD
35
11
VHOLD0
XV1
32
12
V01
XV3
31
13
V03
XVOG
30
14
VOG0
28 29 26 27 25 24
1/2VDD
18
HOB0
19
HHG02
20 23 15 10 3 17 21 1 8 2 9 16 22 34
HHG01 VL VL VL VL
VDD
33
VM
VM
VM
VM
VHH
VHH
VM
VH
VH
2.5
ADC (IC4201/IC4202)
This IC is a 10-bit, 20-MSPS A-D (analog-to-digital) converter. 2.5.1 ADC (IC4201/IC4202) pin assignment
NC NC NC DRVDD AVSS NC AVDD NC NC AIN VREF NC D0 D1 D2 D3 D4 NC NC D5 D6 D7 D8 D9 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37
36 35 34 33 32 31 30 29 28 27 26 25
NC NC OTR DRVSS
45 DRVDD
Fig. 2-5-1 ADC (IC4201/IC4202) pin assignment 2.5.2 ADC (IC4201/IC4202) block diagram
28 CLAMPIN 27 CLAMP 42 AVDD
22 CLK
NC
13 14 15 16 17 18 19 20 21 22 23 24
24 STBY 32 MODE SHA AIN 39 REFTS 29 REFBS 35 REFTF 30 REFBF 34 VREF 38 REFSENS 26 AVSS 44
A/D D/A A/D D/A A/D D/A A/D D/A
SHA
GAIN
SHA
GAIN
SHA
GAIN
SHA
GAIN
A/D
23 3-STATE
CORRECTION LOGIC
OUTPUT BUFFER
1V
DRVSS 45
16 12 8 5 1
OTR D9 D5 D4 D0
Digital output MSB Not used Not used DRVss digital GND
Not used
Clock input 13.5MHz L: normal operation Stand by H:power down mode/L:normal operation Not used REFSENSE reference select H:fix CLAMP L:no clamp fix CLAMPIN clamp reference input :not used Top reference voltage 2.35V Top reference decoupling 2.35V Not used MODE not used Not used Bottom reference decoupling 1.35V Bottom reference voltage 1.35V Not used Not used Analog input Not used Avdd analog supply Not used Analog GND DRVdd digital driver supply Not used
2.6
DSP (IC4301)
This just one package IC performs digital signal processing for PS-CCD system. Its mainly performances of each blocks are followings. 1) PRE-BLOCK Pre-block locates the front of DSP system, and the 2-channel 10 bits AD-converted input data are processed 2ch-tracking and OB clamping as necessary for the Y/C-block. The 2ch-tracking compare the 2-channel tracking pulses (pilot signals) added on the CCD output signal, and output the difference information of between channels to the (-com (Camera CPU). The (-com calculates a revised value for the B-channel signal level, and sends back here. After corrected the difference of between channels, the OB level of the horizontal rear part is calculated. This OB data is used for clamp the next field signal. Also this data is sent to the (-com for reference of high luminance adjustment. 2) Y/C COLOR PROCESS The color processes are color separation, color false suppression, white balance, chroma matrix, CNR and reverse of negative/positive, and finally converts to the DVC format then outputs to the next FMC. The output form of A and B channels are dot-sequential data as B?Y upper 4-bits, B?Y lower 4-bits, R?Y upper 4-bits, R?Y lower 4-bits. 3) Y/C LUMINANCE PROCESS The luminance processes are luminance generation, moire collection, (?/ knee collection, gain/setup and reverse of negative/positive, and finally outputs to the next FMC as an 8-bits data each A and B channels. 4) FMC The camera video signal 12-bits (luminance 8-bits / color 4-bits) ( 2-channels from Y/C or the playback video signal 12-bits (luminance 8-bits / color 4-bits) from the DVC-VTR are supplied, and performed digital effect with control reading and writing to/from the frame memory. In case recording mode, the camera signal that is 2-channels frame data is converted to 1-channel field data at the line number conversion then output to the DVC deck section. 5) SSG This part performs sync signal generation for the video camera. The horizontal sync (HD), vertical sync (VD), complex sync and horizontal/vertical reference signal for the DVC deck section (INH/INV) are generated by dividing the reference clock (27MHz, 13.5MHz), which are supplied from the TG IC5002. When VTR is playback mode, the SSG synchronizes with horizontal sync (PBHS) and vertical sync (PBVS) those are supplied from DVC deck section, then outputs the reference signals to the deck and FMC part. 6) AUTO This part calculates for the auto focus and iris control, then send this data to the camera CPU through the BUS I/F part. Also the iris drive pulse is generated here and output from 151 pin of the DSP IC as the IRIS PWM. 7) BUS I/F The BUS I/F is interface between the each block in the DSP and the camera CPU. The transmission and receive to/from the camera CPU through the MPX 16-bits bus. In case of DV still image transfer to the PC using the JLIP terminal, the DV image data that captured with the frame memory is read out by the FMC. Then it is sent to the camera CPU through the BUS I/F. At the camera CPU the data is converted for the RS-232C (TX) then output to the JLIP terminal. 8) SHUTTER SOUND The shutter sound for the snapshot mode is generated here. This sound outputs from the 129-pin as analog signal.
2-17
Y/C
SSG
BUS I/F
SHUTTER SOUND
AUTO
IRIS/FOCUS
120 136 157 143 170 171 172 158 173 186 187 201 202 217 203 188 218 204 174 219 189 205 159 190 206 220 160 175 191 207 221 176 208 162 222 233 234 163 192 178 193 209 223 179 177 194 161 210 224 195 147 211 225 152 168 239 238 182 230 232
I/F3V GND FMIE FMWR FMWAE FMRAE FMWAD FMRAD FMLWE FMUWE FMRE WCLK RCLK CLK18 SSPP VD2 TOUT NC NC NC BD3 BD2 BD1 BD0 FRP INH INV TEST PBHS PBVS CSYNC CLK270 CLK1350 VTR45 VTR135 GND I/F2V FCVO_0 FCVO_1 FCVO_2 FCVO_3 FCVO_4 FCVO_5 FCVO_6 FCVO_7 FCVO_8 FCVO_9 FCVO_10 FCVO_11 FCVO_12 FCVO_13 FCVO_14 FCVO_15 2V GND QCTEST MINTEST CLKSEL NC VF_BLK
RESET DFLT TVMD TNW STBY FSET OMT KASRST AFBEND BEND PWM I/F3V GND 2V GND IOCNT NC NC SCANTEST TDO TRST TCK TMS TDI I/F3V GND NC NC DAC_GND DAC_GND DAC_GND DAC_GND DAC_GND DAC_GND DAC_GND DAC_GND Analog_out COMP IREF VREF DAC_3V
2-18
PBIN11 PBIN10 PBIN9 PBIN8 PBIN7 PBIN6 PBIN5 PBIN4 PBIN3 PBIN2 PBIN1 PBIN0
100 115 119 118 117 116 134 132 135 133 151 41 25 237 236 150 76 95 149 148 167 166 165 164 184 200 110 131 96 97 111 114 127 130 144 145 129 128 112 113 215 146 155 231 183 199 216 229 228 214 240 213 227 197 198 181 226 212 196 180
(LSB) GND HD output VD output Field distinction output Test terminal Clock input 27MHz Clock input 13.5MHz Not used 3V supply 3V supply GND GND (MSB)
(LSB) Not used Not used Address latch enable input Write enable input Read enable input Reset input DSP_RST_2 Not used Not used Test terminal SSG stand by Reset input DSP_RST_3 EIS data read out timing Not used (H: fix) AF data read out timing WB data read out timing IRIS control PWM output 3V supply GND 2V supply GND Not used (H: fix) Not used Not used for Boundaly scan test for Boundaly scan test Reset input DSP_RST_1 for Boundaly scan test for Boundaly scan test for Boundaly scan test 3V supply GND Not used
GND
Not used
PBY7 PBY6 PBY5 PBY4 PBY3 PB luminance signal input from deck section from DVIO IC3202 PBY2 PBY1 PBY0 PBC3 PBC2 PBC1 PB chroma signal input from deck section from DVIO IC3202 PBC0 VTR section memory reference signal output Not used Not used (L: fix) Not used (L: fix) Not used (L: fix) GND 2V supply YSI7 YSI6 YSI5 YSI4 YSI3 luminance signal output to deck section to DVIO IC3202 YSI2 YSI1 YSI0 CSI7 CSI6 CSI5 CSI4 CSI3 chroma signal output to deck section to DVIO IC3202 CSI2 CSI1 CSI0 2V supply
Data signal in/out of DVC bus (for Static image data) from/to CAS IC3001
Not used Test terminal Not used Sector start signal input of DVC bus from CAS IC3001 Reference clock output 18MHz from DVIO IC3202 Read clock Write clock Read enable Upper write enable Lower write enable Read address Write address Read address enable Write address enable Write address reset mode enable Input enable GND 3V supply Not used FMY7A FMY6A FMY5A FMY4A FMY3A Ach luminance signal input from frame mamory from IC4302 FMY2A FMY1A FMY0A GND FMY7B Bch luminance signal input from frame mamory from IC4302 FMY6B
2.7
FM (IC4302)
This IC is a field memory having a storage capacity of 222,720 words 24 bits. 2.7.1 FM (IC4302) pin assignment
RADE/RX RCLK NRE DO0 DO1 DO2 DO3 DO4 DO5 Vss DO6 DO7 DO8 DO9 DO10 DO11 Vcc Vcc DO12 DO13 DO14 DO15 DO16 DO17 Vss DO18 DO19 DO20 DO21 DO22 DO23 WXINC WR/TR WADE/RX WXAD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36
RXAD RR RXINC Vss D/F DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN8 DIN9 DIN10 DIN11 WAIT Vss DIN12 DIN13 DIN14 DIN15 DIN16 DIN17 DIN18 DIN19 DIN20 DIN21 DIN22 DIN23 WCLK NLWE NUWE IE
D/F 66 READ REGISTER 3 NRE 19 - 24 DO12 - 17 26 - 31 DO18 - 23 12 D OUT BUFFER U-BANK (760 X 290 X 12) X-DECODER MEMORY CELL ARRAY FIFO MODE CONTROL 37 NUWE 36 IE 12 WRITE BUFFER 40 - 51 DIN23 - 12 READ REGISTER 4 - 9 DQ0 - 5 (DO0 - 5) 11 - 16 DQ6 - 11 (DO6 - 11) 12 12 READ REGISTER
MODE CONTROL
2-25
X-DECODER WRITE BUFFER MEMORY CELL ARRAY REFRESH CONTROL U-BANK (760 X 290 X 12) X-DECODER 12 D OUT BUFFER 53 WAIT READ REGISTER
RAS (DIN0) 65
CAS (DIN1) 64
NLWE 38
NUWE 37
A0 - A9 54 - 63
54 - 65 DIN11 - 0 12 36 IE 37 NUWE
RAS (DIN0) 65
CAS (DIN1) 64
VBB Generator
4 - 9 DO0 - 5 11 - 16 DO6 - 11
3 NRE
2-26
2-27
2.8
DVIO (IC3202)
During recording, 4:2:2 video data (Y: 8 bits /Cr, Cb: 8bits 13.5 MHz) from the camera is converted to the 4:1:1 (*4:2:0) (Y/C: 8 bits 18 MHz) and output to the shuffle memory. During playback, the 4:1:1 (*4:2:0) DVC data is converted to the 4:2:2 internal data and sent to the analog video output. In the playback digital mode, the 4:1:1 data is sent to the camera (YMCA). At this time, the color difference signal is sent by the method which divides the data into upper 4 bits and lower 4 bits. The analog output has four DACs-Y, C, Cr, and Cb while a synchronization block has been added for the Y signal. A color encoder and burst function are also incorporated for the C signal. 2.8.1 DVIO (IC3202) pin assignment and block diagram
TEST1 TEST0 VDD2V VDD3V VSS DUMMY7 DUMMY6 DUMMY5 DUMMY4 DUMMY3 DUMMY2 DUMMY1 DUMMY0 INV INH YSI7 YSI6 YSI5 YSI4 YSI3 YSI2 YSI1 YSI0 VDD2V VDD32 VSS CSI7 CSI6 CSI5 CSI4 CSI3 CSI2 CSI1 CSI0 CAMCLK REFCLK PBY7 PBY6 PBY5 PBY4 PBY3 PBY2 PBY1 PBY0 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST8 TEST9 SCAN VSS VDD3V VDD2V INF TRST TMS TCK TDI TDO VSS SHORTCUT VMASK PWROFF YADJ CPSYNC YIN YADVREFH YADVBSI AVSS YADVREFM YADVREFL AVDD AVSS CIN CADVREFH CADVBSI AVSS CADVREFM CADVREFL AVDD AVSS ADVSS ADVDD ADVSS ADVDD
Signal Selector
4:2:2 4:1:1
Clock Conv.
4:2:2 4:1:1
PLL
FRPGEN
1/20
Y DAC
C DAC
Cr DAC
Cb DAC
PC 1/2
88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
VDD2V VDD32 VSS PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PBVS PBHS DSF7 DSF6 DSF5 DSF4 DSF3 DSF2 DSF1 DSF0 VDD2V VDD23 VSS CLK18M1 CLK450K CLK18M2 CLK188M CASVD CASHD FRP SDIO SCLK STP LCDCK VSS VDD2V RST APCRST MCVS VSS XOUT XIN VDD3V
YDAVREF YDABIAS YOUT AVDD AVSS CDAVREF CDABIAS COUT ADVDD ADVSS CRDAVREF CRDABIAS CROUT AVDD AVSS CBDAVREF CBDABIAS CBOUT ADVDD ADVSS PWDNADDA POFF27 POFF18 POFFCG FILSW27 FILSW18 EVFHD VBLK CGFD VSS CLK27IN CLK27OUT CLK18IN CLK18OUT VDD3V VDD2V CLKCGIN CLKCGOUT VSS PC27C PC27H PC18C PCCG CLKCG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
2.9
PLL (IC3201)
2.9.1 PLL circuit description The reference clock of the DVC circuit 18 MHz is generated by the VCO inside the PLL IC3201. During playback and camera picture recording, the switch in the PLL IC is connected to the Pin 33 input. At this time, the 18 MHz clock is locked to the 27 MHz of the crystal oscillator X1401. During DV input recording, the switch is set to the 1394 REC side, and the 18 MHz clock is synchronized with the frame pulse of the DV input (reception) signal from the digital interface. The PC (Phase Comparator) is located inside the MSD IC1401. This 18 MHz clock is sent to the shuffle memory as CLK18M1 from Pin 62 and output from Pin 64 to the CAS, EDA, and digital IF as the CLK18M2. The frequency-divided 450 KHz is sent to the EDA PC as the CLK450K from Pin 63, to become the reference of the recording clock VCO.
DVIO
X1401 XIN 46
IC3202 PLL
REF PLAY CAMERA REC
1/6
IC3201
27MHz CLK18IN 33
1/4
4.5MHz
PC
42
PC18C
33
18MHz
VCO
1394 REC
25
62/64
CLK18M1/M2 35 CLK540K
1/20
63
58
FRP
MSD
62
IC1401
DIF
INF 145
REF
49
MCVS
63
PC
95
VPLL
Fig. 2-9-1 PLL circuit block diagram IC3201 mode switching settings The mode of the IC3201 18 MHz PLL is switched by the settings of Pins 29 and 30, while the mode of the audio FS frequency PLL is switched by the settings of Pins 39 and 40.
CONTROL INPUT PB/CAMERA REC (Pin 33) 1394 REC (Pin 35) Power Save Pin 29 H L L Pin 30 L H L FSCLK (Pin46) CONTROL INPUT 12.3M (48K) 11.3M (44.1K) 8.2M (32K) Pin 40 H L H Pin 39 L L H
36 35 34 33 32 31 30 29 28 27 26 25
18AMP1IN 18BFIN 18BFOUT 18AMP2IN 18AMP2OUT 18VCC 18SELO 18SEL1 18OSCIN 18OSCOUT 18GND 18CLK
Fig. 2-9-2 PLL (IC3201) pin assignment 2.9.3 PLL (IC3201) block diagram
27CLK 27GND CGSEL CGBFIN CGBFOUT CGAMPIN CGAMPOUT CGGND CGf0ADJ CGVCC CGCLK 18GND
13 14 15 16 17 18 19 20 21 22 23 24
Not used
GND for 27MHz VCXO Not used (L: fixed) Not used VCC for 27MHz VCXO Not used GND for 27MHz VCXO Not used (L: fixed)
Not used
GND for CGVCO Not used (L: fixed) VCC for CGVCO Not used GND for 18MHz VCO 18MHz VCO clock output GND for 18MHz VCO 18MHz VCO OSC out 18MHz VCO OSC in 18MHz VCO operation mode select 18MHz VCO operation mode select VCC for 18MHz VCO 18MHz VCO control amp. Output 18MHz VCO control amp. Input Not used 18MHz VCO control buffer input 18MHz VCO control amp. Input 18MHz VCO control amp. Output Not used FSVCO operation mode select FSVCO operation mode select FSVCO control buffer input FSVCO control buffer output VCC for FSVCO VCO oscillation frequency adjustment VCC for FSVCO FSVCO clock output GND for FSVCO Not used
A2 A3 A4 NC A5 A6 NC A7 A8 VSS VSS VSS NC VDD1 VDD1 VDD1 NC CE VDD2 VDD2 SOC NC RS DOCTL OE
22 11 2 14 23 12 27 3 13 4 5 6 28 24 25 26 35 15 16 34 7 36 17 8 18
87 66 1 10 19 65 20 21 64 33 97 96 95 67 59 58 63 72 71 62 70 83 92 61 54
NC NC A1 A0 DOI8 NC DOI7 DOI6 NC DOI5 VSS VSS VSS VDD2 VDD2 DIO8 NC DIO7 DIO6 NC DIO5 A17 A16 NC VDD2
73 84 93 60 74 85 55 94 86 77 76 75 53 69 57 56 88 98 52 89 78 51 99 90 79
A15 A14 A13 NC A12 A11 NC A10 A9 VDD1 VDD1 VDD1 NC VSS VSS VSS WS SIC NC WE CS NC TCK TMS TDI
NC NC VSS DIOS DOI4 NC DOI3 DOI2 NC DOI1 VDD2 VDD2 NC VSS VSS DIO4 NC DIO3 DIO2 NC DIO1 TDO TRST NC NC
37 38 32 9 31 39 30 29 40 42 41 46 45 43 44 68 47 80 81 48 82 91 100 49 50
2-36
Pin Name A2 A3 A4 NC A5 A6 NC A7 A8 VSS VSS VSS NC VDD1 VDD1 VDD1 NC CE VDD2 VDD2 SOC NC RS DOCTL OE NC NC VSS DIOS DO14 NC DO13 DO12 NC DO11 VDD2 VDD2 NC VSS VSS DIO4 NC DIO3 DIO2 NC DIO1 TDO TRST NC NC
In/Out In In In In In In In In In In In In In In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out Out In -
REF. Shuffle memory address (18 MHz, 18 bit) from CAS IC3001 Not used Shuffle memory address (18 MHz, 18 bit) from CAS IC3001 Not used Shuffle memory address (18 MHz, 18 bit) from CAS IC3001 GND Not used Power supply (+3 V) Not used Shuffle memory chip enable from CAS IC3001 Power supply Clock input (18 MHz) from CLK OSC IC Not used Shuffle memory read strobe rom CAS IC3001 Shuffle memory data output control Output enable (L: fixed) Not used Not used GND Shuffle memory data I/O select from CAS IC3001 Shuffle memory data (8 bit) from/to CAS IC3001 Not used Shuffle memory data (8 bit) from/to CAS IC3001 Not used Shuffle memory data (8 bit) from/to CAS IC3001 Power supply (+3 V) Not used GND Shuffle memory data (8 bit) from/to CAS IC3001 Not used Shuffle memory data (8 bit) from/to CAS IC3001 Not used Shuffle memory data (8 bit) from/to CAS IC3001 Boundary scan test data output Boundary scan test reset input Not used
Pin Name TDI TMS TCK NC CS WE NC SIC WS VSS VSS VSS NC VDD1 VDD1 VDD1 A9 A10 NC A11 A12 NC A13 A14 A15 VDD2 NC A16 A17 DIO5 NC DIO6 DIO7 NC DIO8 VDD2 VDD2 VSS VSS VSS DOI5 NC DOI6 DOI7 NC DOI8 A0 A1 NC NC
REF. Boundary scan test data input Boundary scan test mode select input Boundary scan test clock input Not used Chip select (H: fixed) Write enable from SHUFFLE Not used Clock input (18 MHz) Shuffle memory control write strobe GND Not used Power supply (+3 V) Shuffle memory address (18 MHz, 18 bit) from CAS IC3001 Not used Shuffle memory address (18 MHz, 18 bit) from CAS IC3001 Not used Shuffle memory address (18 MHz, 18 bit) from CAS IC3001 Not used Not used Shuffle memory address (18 MHz, 18 bit) from CAS IC3001 Shuffle memory data (8 bit) from/to CAS IC3001 Not used Shuffle memory data (8 bit) from/to CAS IC3001 Not used Shuffle memory data (8 bit) from/to CAS IC3001 Power supply (+3 V) GND Shuffle memory data (8 bit) from/to CAS IC3001 Not used Shuffle memory data (8 bit) from/to CAS IC3001 Not used Shuffle memory data (8 bit) from/to CAS IC3001 Shuffle memory address (18 MHz, 18 bit) from CAS IC3001 Not used
2.11
This IC carries out digital signal processing of the video and audio signals on conforming to the DV format. Its comes equipped with the usual LSI functions such as COMPRESS, SHUFFLING, and AUDIO PROCESS. During recording, it controls the address read/write enable of the SHUFFLE MEMORY to shuffle the video signals. After that, it carries out, on the video data, adaptive two-dimensional discrete cosine transform (DCT), re-digitization, and variable length coding (VLC), and saves the data in the synchronization block, and outputs the data to the DVC bus. At the same time, it also performs 1 frame completion shuffling on audio signals, and outputs the data to the DVC bus after saving in the synchronization block. During playback, it performs the reverse process of recording. It extracts video synchronization block data and audio synchronization block data on the DVC bus, and decodes video data and audio data from the extracted data.
IC8001 IC3001 IC3003
D-IF
CAS
SSP DV BUS: BD0-3,SMP
EDA
SSP: Sector(1-track) Start/Stop Pulse SMP: DV BUS Start Mark Pulse
Fig. 2-11-1 DV-BUS connection 2.11.1 CAS (IC3001) pin assignment and block diagram
VSS FRP DIBCK DIMCK DOBCK DOMCK DOLRCK DODAT VSS XI XO VDDE3 VDDE3 VDDI2 AIDAT RECMUT VSS DIDAT DILRCK LKFRP SCK SDA STP CLK24 RST SHM225 HSP VSP DFD7 DFD6 DFD5 DFD4 VSS DFD3 DFD2 DFD1 DFD0 VDDE2 VDDE2 VDDI2 CLK18 VSS SMADD17 SMADD16 SMADD15 SMADD14 SMADD13 SMADD12 SMADD11 VSS 104 97 103 96 87 76 102 86 95 75 64 63 74 94 101 73 84 93 100 72 83 92 99 91 98 89 88 90 78 79 77 65 67 66 68 57 53 55 54 42 46 45 44 43 34 36 35 25 23 24 7 14 6 13 22 33 32 12 21 5 41 31 20 11 4 30 10 19 3 29 18 9 2 8 1
m-com I/F
DV BUS I/F
Shuffle Address
VSS TDI TMS TCK TRST TDO PWMO FS0 FS1 VSS VCOI VCOO VDDE3 VDDI2 VSS TINT0 TINT1 TINT2 TINT3 TINT4 TINT5 TINT6 TINT7 SSP VSS
SMADD10 SMADD9 SMADD8 SMADD7 SMADD6 SMADD5 SMADD4 VSS SMADD3 SMADD2 SMADD1 SMADD0 VDDE2 VDDI2 SMCE SMRS VSS SMWE SMWS SMDIOS SMP BD3 BD2 BD1 BD0
81 82 80 70 69 71 61 59 60 62 58 51 49 50 47 37 39 38 40 28 26 27 15 17 16
2-40
2-41
2-42
ALE VDDI2M VSSI VDDI3 CS RST CYLFG CYLPG PTST0 PTST1 PTST2 PTST3 SCANM SCANI SCANO VDDI VSSI TRST TMS TDI TCK TDO VDDI3 SSP VSSO VDDO2B BD0 BD1 BD2 BD3 SMP VDDI2B
125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156
SPCTL
SRAM
SUBCODE
CKCTL
PC
ECC/DCI Viterbi
78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47
NC VITON TRICK MEMP REFCLK CKPHASE VCOCTL ADSTB VDDO3 VSSO ADDAT6 ADDAT5 ADDAT4 ADDAT3 ADDAT2 ADDAT1 ADDAT0 VDDI3 VSSI HSE VDDO2 VDDO3 RECCLK EQHLD VSSO PBCLK PBDAT VDDI3 DVCC3 AVCC3 ATFI VTOP
VSSI CLK450 CLK18 VDDI2 VSSO VDDO3R LCAS UCAS OE A8 A7 A6 A5 A4 A3 A2 A1 A0 RAS WE VSSO VDDO3R VSSI VDDI DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 VDDO3R VSSO AGND AGND DGND VBTM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
2-44
2-45
2-46
2-47
2.13
This IC is a CMOS (Complementary Metal Oxide Semiconductor) DRAM having a storage capacity of 256 words 16 bits. 2.13.1 DRAM (IC3004) pin assignment
DQ15 DQ14 DQ13 DQ12 DQ11 50 DQ10 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD VDD DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 VSS VSS 51
64
63
62
61
60
59
58
57
56
55
54
53
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
52
VDD
NC
A0
A1
A2
A3
NC
NC
NC
NC
A4
A5
A6
A7
Fig. 2-13-1 DRAM (IC3004) pin assignment 2.13.2 DRAM (IC3004) block diagram
RAS UCAS LCAS
16 34 35
CLOCK GENERATOR
VSS
A8
15
WE
A0 A8 A0 - A8
18 -21, 28 -32
I/O SELECTOR
WORD DRIVER
A0 - A8
ROW DECODER
MEMORY CELL
SENSE AMP
V SS V DD
26, 56 23, 57
OE
2-49
2-50
1 2
REF
20 19 18 17 16 15 14 13 12
TIMING
D0 D1 D2 D3 GND VDD D4 D5 D6 D7
3 4 5 6
T/H ADC OUTPUT STAGING
7 8 9 10
11
Fig. 2-14-1 VITERBI A/D (IC3005) pin assignment and block diagram 2.14.2 VITERBI A/D (IC3005) pin functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name PWRDWN VREFOUT VREFIN GND VD AIN/ AIN VD GND ENCODE D7 D6 D5 D4 VDD GND D3 D2 D1 D0 In/Out In Out In In In In In In Out Out Out Out Out Out Out Not used Digital signal output to EDA IC3003 (after the analog to digital converted) Power supply for digital output GND Digital signal output to EDA IC3003 (after the analog to digital converted) REF. Power down function select (H: Power down mode) Inside reference voltage output (+1.25V typ) Reference voltage input for ADC (+1.25V typ) GND Power supply for analog circuit Analog signal input for ADC Analog signal input for ADC Power supply for analog circuit GND Encode clock input for ADC
PBSW2
VCC3V
HA2FB
HA2IN
RCUR
RECR
RCTL
HID3
HID2
HID1
RECI
48
47
46
45
44
43
42
41
40
39
38
37
36
35
STAB PBEN MMC INSRH EQHLD ENVDET ENVOUT TRICKH ATFOUT ENVCTL HAOUT VCC3V PBOUT AGCIN GND AGCOUT
49 50 51 52 53
GND
33
PBH
32 31 30 29 28
PBH2 RA2OUT VCC5V RA1OUT PBH1 GND MON1IN VCC3V HA1IN PBSW1 HA1ACFB HA1FB HA1DET VCC5V RA3OUT PBH3
RA1
54 55 56 57 58 59 60 61 62 63 64 AGC DET AGC AMP 3rd AMP LPF 27
ENV DET
MONITOR
26 25 24
HSW HA1
VREF
23 22 21 20 19
18 17
10
11
12
13
14
15
16
VCC3V
HA3IN
RECR1
RECR2
HA3ACFB
HA3DET
VCC3V
HSE
EVR
HA3FB
GND
PBSW3
AGCDET
AGCCTL
2-52
MON3IN
GND
2-53
2-54
DLADJ
GND7
GND6
VCC7
ERR2
ERR1
50
64
63
62
61
60
59
58
57
56
55
54
53
52
51
TFIL_OUT
1+D_IN
49
VCC6
PB_H
1 2 3 4 5
SDET2 GND5 SDET1 VCC5 PC_OUT AMP_IN AMP_OUT VCO_IN PHASEADJ MON3 CK_PHASE VCC4 AD_CLK PB_CLK GND4 PB_DAT
PC ERROR DET
VCC1 ATFC ATF_GAIN ATFI_OUT REFDET REFCLK TRICK_H TRICK_L BETA ALFA MON1
6 7 8 9 10 11 12 13 14
38 37 36 35 LATCH OUTPUT 34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
RECCLK
VCC2
VCC8
GND2
VCOCTL
2-55
AMP_OUT
VCO_IN
MON2
GND3
VCC3
DET1
DET2
DET3
DET4
32
2-56
2-57
2.16.3 PB EQ circuit The playback enveropes input from the PREAMP is subjected to optimum waveform equalization suitable for decoding at the PRE-EQ and AUTO-EQ. After that it is added with 1+D characteristics, and output to the VITERBI A/D converter as 1+DOUT. The 1+DOUT signal is an analog waveform with tertiary value (1, 0, -1). It is converted to 7-bits digital signal by the A/D converter, and sent to the VITERBI circuit. The digitized tertiary information is corrected by the VITERBI detection method and converted into the binary (0, 1) playback data. The 1+DOUT signal is re-input into the IC3501, and output as the PB DATA after tertiary detection and binary conversion by the fixed threshold value method in the DATA DET circuit, to become the playback data when the VITERBI is OFF. However in this unit, as VITERBI is always ON for both SP and LP, this applies only when VITERBI is forcibly turned OFF using the service support software. The playback clock is constantly phase-compared with the playback data in the PLL circuit, and output synchronized with the playback data. One is output to the A/D converter as the AD CLK, and the other is sent to the EDA as the PB CLK. As the sampling point is also changed during A/D conversion by this AD CLK, there is a need for sampling to be carried out at the correct position for the VITERBI detection circuit to operate correctly. Therefore the phase correction information from the VITERBI circuit is output as the CK PHASE, and the PS (phase shift) of the PLL circuit carries out fine adjustments of the phase. The adjustment values are input from the EVR IC3503 based on the data written in the EEPROM. In the adjustments, the service support software adjusts the values to the standard values by VCO Center adjustment first, after which the error rates are sequentially adjusted to the minimum values according to the order in which the other adjustment points were specified in the PB EQ adjustment.
Delay ADJ PB EQ IC3501 From: PREAMP AGC IN 1+D OUT
IC3005
PRE-EQ
LPF
TFIL
1+D
A/D CONV.
VITERBI
A-EQ
AD CLK
a ADJ b ADJ
Error Timing ADJ Slice Level ADJ DATA DET LATCH PB DATA PB CLK
PC
LPF
CK PHASE
2-58
31
32
30
1 2 3 4 5 6 7 8
29
28
VDD
AO12
AO13
AO14
VCC
AO15
AO16
Fig. 2-17-1 DAC (IC3503) pin assignment 2.17.2 DAC (IC3503) block diagram
DI CLK
AO17
24
DO
CHANNEL DECODER 8 24 1 24
25
LD
8bit RESISTOR
8bit RESISTOR
24
8bit RESISTOR
30 AO1
31 AO2
23 AO24
2-60
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
Fig. 2-18-1 ENV D/A CONV. (IC1201) pin assignment 2.18.2 ENV D/A CONV. (IC1201) block diagram
DI CLK
14
DO
ADDRESS DECODER 8 12 1 12
15
LD
D0 8bit LATCH
D7 1
D0 12 8bit LATCH
D7
18 AO1
13 AO12
2-61
2-62
2.19
The digital interface of this unit corresponds to the input/output of the DV terminal (IEEE 1394). The digital interface IC8001 is mounted on one chip with the usual LINK IC and PHY IC. The structure is the same as the previous model, however with the use of the second generation DVC signal processing LSI incorporated from this unit, it eliminates the need for matching the DV BUS data using the gate array as done in the previous model, and the DVS BUS data can be input/output to and from the digital IF IC directly. The MSD IC serves as the host microprocessor. 2.19.1 Digital IF (IC8001) pin assignment and block diagram
SSP VCC CLK18 VCCB(2/3) ADB6/SMPB ADB7/DBB3 ADB8/DBB2 ADB9/DBB1 ADB10/DBB0 GND ADB11/SMPA AD12/DBA3 AD13/DBA2 AD14/DBA1 AD15/DBA0 VCCB(2/3) VCC VCCB(2/3) BCLK /DC ALE NC /LCNTD GND AD0 AD1 AD2 AD3 GND AD4 AD5 AD6 AD7 VCCA(2/3) AD8 AD9 GND ADB5 ADB4 ADB3 ADB2 VCC ADB1 ADB0 ADEN BKRDY GND UPPEN CYCLD CYCLS CLK25 VCC /RST FRP VFRP TEST0 GND TEST1 SI/TEST2 SO SCK VCC /SEN TMS TCK /TRST GND TDI TDO /LISO LLREQ VCC 21 10 1 22 11 2 36 23 12 3 50 37 24 13 4 51 38 25 5 14 6 15 26 39 52 7 16 27 40 53 8 17 28 41 9 18
m- c o m I/F
ATF ARF
LINK
PHY
AD10 AD11 GND AD12 AD13 AD14 AD15 VCCA(2/3) VCC /INTP CYCLEIN NTZIHZ NTOUT GND NTCLK RANEZ LCNA LPWRDN VCC GND DVSS C/LKON LPS CNA TESTM1 TESTM2 /RESET /ISD AVCC PWRDN PLLFLT PLLVDD PLLGND PLLGND XI XO
LD3 LD2 LD1 LD0 LCTL1 LCTL0 LSYSCLK VCC GND DGND DVCC PC0 PC1 PC2 LREQ CTL0 CTL1 D0 D1 SYSCLK DVCC DGND AGND AGND TPBIAS AGND AGND AVCC AVCC CPS R1 R0 TPBTPB+ TPATPA+
127 136 104 117 128 137 92 105 118 129 138 93 106 119 130 139 131 140 120 107 94 141 132 121 108 95 142 133 122 109 143 134 123 144 135 124
2-64
2-65
2-66
2-67
2.20
E_SENS S_SENS AVREF AVCC VCC2 VSS AGC_RST BCLK DC R/W ALE RD BLW BHW DO0 DO1/A16 DO2/A17 DO3/A18 DO4/A19 DO5/A20 DO6/A21 DO7/A22 DO8/A23 DO9/A24 D10/A25 D11/A26 D12/A27 D13/A28 D14/A29 D15/A30 VSS VCC2
125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156
2-68
VSS HLDA HOLD RESET MODO MOD1 VCC VSS VPP ADC_DEM0 ADC_DEM1 ADC_PWD0 ADC_PWD1 DIC_STP1 DIC_STP2 TRG_OUT P97 VSS OSCVCC XIN XOUT OSCVSS VSS VCC AH_CTL2 AH_CTL1 SLOW TALLY_LED P104 P105 P106 P107 P110 P111 P112 P113 P114 P115 P116 P117 VCC VSS VCC CAM0 CAM1 CAM2 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
DEW_SENS AV/H_DET ANO4 ANO5 ANO6 BCID1 BCID2 BCID3 AN10 AN11 AN12 AVSS P87/ADTRG P86/TC5 P85/TB5 P84/TA5 P77/TB4 P76/TA4 P75/TB3 P74/TA3 P73/TB2 P72/TA2 VCC VSS TAPE_LED FRP MIC_SCK MIC_SDA MIC_CTL A_PLL V_PLL CAP_REF DRUM_REF NMI MSELECT P_DET S_DET P55/INT3 DIF_INT VSS VCC SYS_OUT SYS_IN SYS_CLK MREADY DIC_OUT
DIC_IN DIC_CLK DIF_RST MDA_OUT MDA_IN MDA_CLK MDA_CS RXD TXD CAP_BRK LD_ON DIC_RST VCC VSS PWMD MCVS FRP SSP S_REEL T_REEL SPA HID TSR CAP_FG DRUM_FG VSS VCC RF_STAB RF_FAST RF_TRICK REEL_LED REC_SAFE
2-69
2-70
2-71
2-72
OPEN_SW CLOSE_SW AD0 AD1 AD2 AD3 VDD VSS AD4 AD5 AD6 AD7 AD8 AD9 AD10 PWR_CTL M16_RDY AD11 AD12 AD13 AD14 AD15 MODE0 MODE1 MODE2 M16_CS WB_IR_DET F/Z_CS VDD OSCI OSCO VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
2-73
VF_LD FLDFMC RST GATE_PULSE V_MUTE JLIP_INT VD OMT EXTINDET MENU_P_A BEND RTC_INT AFBEND SLOW LCD_LD OSD_CS EEPROM_CS VDD TIMER_OUT STORDBE_CHG M_P_ON STBY_TG REMOTE S_DT_IN S_DT_OUT S_CLK VF_CTL OSD_DATA OSD_CLK RXD TXD AUDIO_CS 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 RE HWE LWE DAC_CS RTC_CS MENU_SET_SW BUZZER M16_RST STO_FOLL AVDD VRefH MONI_RVS PHOTO_MODE KEY_C STOROBE_AD CAM_DAC_CS TG_CS F_PTR_AD Z_PTR_AD HALL_AD IR_AD ZOOM_SW KEY_B KEY_A BATT_CHK VRefL AVSS VSS VDD AFZ_CLK AFZ_DATA RESERVE4
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
A_MUTE AFADER FADE_H LCD_CS S_SPK_ON SMUTE S_OPEN S_CLOSE IRIS_O/C VDD(VPP) V_P_ON MO_BK_ON M_LR M_U/D F/Z_RST DSP_RST_3 DSP_RST_2 DSP_RST_1 MENU_P_B VF_SW MONITOR_SW CAS_SW EJECT_SW DIAL_PLAY DIAL_OFF DIAL_AUTO DIAL_MANU DIAL_PROGRE DIAL_5S VSS VDD CALE
2-74
2-75
2-76
2-77
2.22
MDA (IC1601)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
TEST1 DETECT START D.OSC D.PCV D.PCI D.ECR D.EC NC GND2 D4 D3 D2 D1 D0 DOUT DIN CS CLK NC
C.VH C.WH C.HWC.HW+ C.HVC.HV+ C.HUC.HU+ C.FGSOUT C.FGOUT C.FGC.FG+ VCC C.VS C.PCV C.PCI C.ECR C.EC C.RCC C.BRK
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
2-78
UPPER/LOWER DIVISION
D.UIN
D.VIN
D.WH D.W
D.WIN D.COM
IC1602
D.OSC
OSC
START TIMING
D.GND
DRUM.M
D.FG-
BRAKE
D . P G-
DRUM_REF REG_5V
DRUM_FG DRUM_PG
D.FGSOUT D.PGSOUT
POWER SAVE
CTL LOGIC
L.REV L.GND
LOAD.M
PW_SAVE
L.FIN
L.RIN
D.FGD.FG+ CAP_PWR
REG_5V DRUM_FG
C.FR
HALL
C.HU+ C.HU-
HALL
C.HV+ C.HV-
C.WH C.W
HALL
C.HW+ C.HW-
IC1603 CAP.M
C.RCC
RIPPLE CANCEL
C.EC C.VS C.MODE C.VM C.MODE
C.GND
CAP.M
CAP_REF REG_5V
CAP_ERR
DC/DC
C.TL C.BRK
CAP_BRK
2-80
2-81
2.23
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
Fig. 2-23-1 OSD (IC1002) pin assignment 2.23.2 OSD (IC1002) block diagram
9 DATA SBT2 CS 3 1 2
DATA INPUT SHIFT RESISTOR INSTRUCTION DECODER
TEST
CONTROL SIGNAL
VDD 10 G N D 4 PCL
CKO
6
HORIZONTAL SIZE COUNTER HORIZONTAL SIZE COUNTER HORIZONTAL ADDRESS COUNTER
OSCO
OSC DISPLAY POSITION VERTICAL ADDRESS RESISTOR CHARACTER GENERATOR ROM 12 X 18bit X 256word VERTICAL SIZE COUNTER SYNC. PROTECT VERTICAL POSITION COUNTER VERTICAL ADDRESS COUNTER OUTPUT CONTORLLER
OSCI
H D 20
DATA SELECTOR
VIDEO RAM
2-83
2.24
This IC drives and controls the FOCUS and ZOOM pulse motors. It is composed of the serial data decoder, drive pulse generator, and current setting and output driver. The serial data is input from the SYSCON CPU, after which first the initial data is sent when the power is turned on, and initial settings are performed. Next, standard data such as pulse width, number of pulses, rotation direction (CW/CCW), and current settings are synchronized with the VD, and input sequentially to drive the motor. 2.24.1 Focus & Zoom driver (IC4851) pin assignment and block diagram
PGND EXP3 EXTa Vm1 A1 FBa A2 Vm2 B1 FBb B2 EXTb VD LATCH SDATA SCLK OSCin OSCout RESET
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 1/N OSC SERIAL DECODER PULSE GENERATER H BRIDGE a 2ch H BRIDGE b 2ch H BRIDGE a 1ch H BRIDGE b 1ch
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
EXP2 EXP1 EXP0 C1 FBc C2 Vm4 D1 FBd D2 Vm3 Vdd Vref FILd FILc FILb FILa Cosc LGND
C U R R E N T S E Ta EVR2 EVR1
C U R R E N T S E Tb EVR1 EVR2
Fig. 2-24-1 Focus & Zoom driver (IC4851) pin assignment and block diagram
2-84
2-85
YIN1
ATT -12dB
LPF
20
CLAMPREF
GCACTL1
BPF
ATT -12dB
19
CIN1
YIN2
PWR SAVE
18
GCACTL2
CLAMP
CLAMP
ATT -12dB
17
CIN2/INSEL
CHARA
5
LOGIC
CLAMP
16
VCC2
BLANK
6
COMP
15
VCC1
WIDE
7
6dB +12dB 75 W BUF
14
COUT
GND
8
220k W
13
SDCOUT
YOUT
9
75 W BUF +12dB
12
VOUT
YSAG
10
11
VSAG
Fig. 2-25-1 VIDEO OOUTPUT DRIVER (IC3701) pin assignment and block diagram
2-86
2-87
VCO_ADJ
SYNC_IN
16
15
14
13
12
11
10
PD
VCO ADJ
PLL
VDD2 CLR HST HCK2 HCK1 HD FLD_OUT FLD_IN T1 VST1 VCK2 VCK1 EN VD1 VD2 VSS2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SERIAL BAS I/F
BUF PALSW
PWRST
EXT_G
EXT_R
EXT_B
VD_IN
GND1
TRAP
VDD1
VSS1
CKO
RPD
CKI
64 63
T0 PICT Y_IN GND3 F_ADJ C_IN ST_UP V_REG VXO_I VXO_O APC BK_LIM C_OUT R-Y_IN B-Y_IN VCC1
V SEP
DL1
TRAP
CLAMP
62 61
HCNT H-PULSE
60 59 58
REG
BPF
GAMMA
g-1
57 56
COLOR HUE PS
55 54 53
VTST
SUBBRIGHT
R-BRT
52 51 50 49
POL SW WIDE
DEMOD
BUF
BUF
33
34
35
36
37
38
39
40
41
42
43
44
46
47 VCC_2
B_OUT
G_OUT
R_OUT
DATA
RGT
T2
T3
T4
45
Fig. 2-26-1 VF LCD DRIVER (IC7401) pin assignment and block diagram
2-88
SIG_CENTER
GND2
LOAD
SCLK
FB_G
FB_R
FB_B
48
2-89
2-90
2.27
This IC that integrates the RGB recorder, RGB driver, timing generator for driving LCD panel into one chip drives the color LCD monitor. Although this IC is conformable to composite video signal, Y/C signal and Y/color difference signal as video input to it, Y/color difference signal is used as video input to this IC of the DVL7. The input system and TV system (NTSC/PAL) can be respectively switched by setup of serial data to be input to the pin 51 of this IC. 2.27.1 LCD MONITOR DRIVER (IC7301) pin assignment
YCLAMP QHSEL RMONI BMONI
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
APC VXOO VXOI CHROMA BCHCLAMP VCC1 VREF GCHCLAMP RCHCLAMP YS COM BCHDC VCC2 GCHDC RCHDC BOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
49
LOAD
R-YIN
TRAP
STUP
DATA
B-YIN
SCLK
HMC
GND
ACC
RST
YIN
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
COMPIN CSYNC HSYNC COMDC FOADJQH QH VSS AW VDD STV3 AFC CPV1 CPV2 STV1 STV2 VCC3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 CPH2
DEV
CPH2
CPH1
OSDB
OSDG
GOUT
OSDR
ROUT
2-91
CPH1
VD
HD
STH3
STH2
STH1
GND
32
2-92
2-93
2-94
2.28
This IC serves as an analog signal input/output interface (Audio I/O) that the input amplifier, wind noise filter circuit to eliminate blast sound, ALC circuit, 30-kHz LPF, line amplifier, stereo headphone amplifier, BTL monaural speaker amplifier are integrated into one chip. Since this IC incorporates the serial control decoder circuit inside, internal operation mode of this IC is set up by serial data control. 2.28.1 AUDIO AMP (IC2201) pin assignment
SP OUT_2 SP OUT_1 HP OUT_R HP OUT _L MUTE OUT LINE OUT_R LINE OUT_L EXT MIC IN_R EXT MIC IN_L MIC SEL INT MIC IN_R INT MIC IN_L SP VCC SP ON/OFF SP GND BEEP IN MIX OUT MUTE GENC MUTE CTRL BIAS VREFC AGND1 RGND2 AVCC 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37
36 35 34 33 32 31 30 29 28 27 26 25
EXT NFB_L INT NFB_L EXT NFB_R INT NFB_R WINDC IN_L WINDC1_L WINDC2_L WINDC IN_R WINDC1_R WINDC2_R FADE CTRL FRDE DELAY
Fig. 2-28-1
CS CLK DATA IN DGND DVCC PB IN_R PB IN_L REC OUT_R REC OUT_L REC NFB_R REC NFB_L ALC FILTER
13 14 15 16 17 18 19 20 21 22 23 24
2-95
Fig. 2-28-2
2-96
Table 2-29-1 Relation between clock and sampling rate When the CMODE terminal is set at "H" level, 384 fs or 512 fs can be input as a master clock. Input clock is automatically detected and it is internally divided into 256 fs and the rest. EM1 terminals has effect on input data. The de-emphasis filter is disabled when the DEM0 is set at 1 and DEM1 is set at 0 (DEM0 = 1, DEM1 = 0).
DEM1 0 0 1 1 DEM0 0 1 0 1 Mode 44.1kHz OFF 48kHz 32kHz
2-98
2.29.1 16BIT A/D, D/A CONV. (IC2101) pin assignment and block diagram
CMODE AOUTR AOUTL VCOM DGND
13 12
AGND
DEM0
DEM1
SDTI
15
8x Interpolator 8X Interpolator
24
23
22
21
20
19
18
17
16
14
Clock Divider
Common Voltage
LPF
DS Modulator DS Modulator
LPF
Decimation Filter
10
11
VCMR
VCML
MCLK
VRDA
VRAD
LRCK
SCLK
VD
VA
VB
PWAD
Fig. 2-29-1 16BIT A/D, D/A CONV. (IC2101) pin assignment and block diagram 2.29.2 16BIT A/D, D/A CONV. (IC2101) pin functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name VRDA VRAD AINR VCMR VCML AINL PWAD PWDA MCLK LRCK SCLK SDTO DGND VD SDTI CMODE DEM1 DEM0 AOUTL AOUTR VCOM AGND VB VA In/Out In In In Out Out In In In In In In Out In In In In Out Out Out REF. Reference voltage input for DAC, VA Refernce voltage input for ADC, VA Rch analog input Rch common voltage output Lch common voltage output Lch analog input ADC power down mode (L: Power down) DAC poewr down mode (L: Power down) Master clock input I/O channel clock input Audio serial data clock Audio serial data output GND (for digital) Power supply (for digital) Audio serial data input Master clock select (H: 384fs or 512fs , L: 256fs) Deemphasis frequency select Deemhpasis frequency select Lch analog output Rch analog output Common voltage output GND (for analog) Sub straight Power supply (for analog)
PWDA
SDTO
AINR
AINL
2.30
This IC serves as a six-channel switching regulator controller, and it internally incorporates the triangular wave generator, reference voltage regulator, error amplifier, PWM comparator, totem pole driver, various protection circuits into one chip. For channel control, all channels are turned off if the STB terminal is set at "L" level, and only the channel 3 is turned off if the STB3 terminal is set at "L" level. 2.30.1 REGULATOR CTL (IC6101) pin assignment
GND456 GND123
CAPH4
CAPH3
GATE4
CAPL4
CAPL3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
CAPL5 CAPH5 BIAS5 OUT6 CAPL6 CAPH6 BIAS6 DTC2 SCP6 NON6 INV6 FB6 COMP SCP5 NON5 INV5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
CAPL2
BIAS4
BIAS3
Vcc56
Vcc24
OUT5
OUT4
OUT3
OUT2
CAPH2 BIAS2 OUT1 CAPL1 CAPH1 Vcc13 BIAS1 SCP1 INV1 FB1 GATE1 INV2 FB2 SCP2 SCP3 INV3
SCP4
INV4
FB5
FB4
SCP
DUTY
VREF
2-100
SOFT
DTC3
STB3
GND
STB
FB3
RT
CT
Vcc
2-101
2-102