Intel Atom Processor Z6xx Series

Datasheet
For the Intel Atom Processor Z670 on 45-nm Process Technology April 2011 Revision 001

Document Number: 325310-001

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The Intel Atom Processor Z670 component may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. For Enhanced Intel SpeedStep Technology : See the Processor Spec Finder at http://ark.intel.com or contact your Intel representative for more information Intel, Intel Atom and the Intel logo are trademarks of Intel Corporation in the U. S. and other countries. *Other names and brands may be claimed as the property of others. Copyright 2011 Intel Corporation. All rights reserved.

Datasheet

Contents
1 Introduction ................................................................................................... 6 1.1 1.2 Processor Features ...................................................................................6 Interfaces ...............................................................................................7 1.2.1 System Memory Support .............................................................7 1.2.2 1.2.3 1.2.4 1.2.5 1.3 1.4 2 2.1 Display Controller .......................................................................7 cDMI .........................................................................................7 cDVO ........................................................................................8 LVDS ........................................................................................8

Terminology ............................................................................................8 Reference Documents...............................................................................9 Signal Description .................................................................................. 11 2.1.1 System Memory Interface .......................................................... 11 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.1.7 cDMI Interface ......................................................................... 13 cDVO Interface ......................................................................... 13 LVDS Display Port Interface ....................................................... 14 LGI/LGIe (Legacy) Signals ......................................................... 15 Debug and Miscellaneous Signals................................................ 16 Power Signals .......................................................................... 17

Signal Descriptions ....................................................................................... 11

Power Management ...................................................................................... 18 3.1 Processor Core Low Power Features ......................................................... 18 3.1.1 Cx State Definitions .................................................................. 20 Power and Ground Balls .......................................................................... 22 Decoupling Guidelines ............................................................................ 22 Voltage Rail Decoupling .......................................................................... 22 Voltage Identification (VID) ..................................................................... 23 4.4.1 VID Enable .............................................................................. 23 4.4.2 4.5 4.6 VID Table ................................................................................ 24 Absolute Maximum Ratings ..................................................................... 25 DC Specifications ................................................................................... 26 Temperature Monitoring ......................................................................... 32 Intel Thermal Monitor ........................................................................... 32 5.2.1 Digital Thermal Sensor .............................................................. 34 5.2.2 5.2.3 5.2.4 Out of Specification Detection .................................................... 35 Catastrophic Thermal Protection ................................................. 35 PROCHOT# Signal Pin ............................................................... 35
3

Electrical Specifications ................................................................................ 22 4.1 4.2 4.3 4.4

Thermal Specifications and Design Considerations ....................................... 31 5.1 5.2

Datasheet

Package Mechanical Specifications and Pin Information ............................... 37 6.1 6.2 Package Mechanical Specifications ........................................................... 37 Processor Pinout Assignment ................................................................... 39

Figures
Figure 3-1. Thread Low Power States .................................................................. 19 Figure 3-2. Package Low Power States ................................................................ 19 Figure 6-1. Package Mechanical Drawing ............................................................. 38

Tables
Table 2-1. Signal Types ..................................................................................... 11 Table 2-2. Buffer Types ..................................................................................... 11 Table 2-3. System Memory Interface Signals ....................................................... 11 Table 2-4. cDMI Interface Signal ........................................................................ 13 Table 2-5. cDVO Interface Signals ...................................................................... 13 Table 2-6. LVDS Display Port Interface Signals ..................................................... 14 Table 2-7. LGI/LGIe Legacy Signals .................................................................... 15 Table 2-8. Debug and Miscellaneous Signals ........................................................ 16 Table 2-9. Power Signals ................................................................................... 17 Table 4-1. VIDEN Encoding ................................................................................ 23 Table 4-2. VID Table ......................................................................................... 24 Table 4-3. Absolute Maximum Ratings ................................................................. 25 Table 4-4. Voltage and Current Specifications ...................................................... 26 Table 4-5. Differential Clock DC Specifications ...................................................... 28 Table 4-6. AGTL+, CMOS, and CMOS Open Drain Signal Group DC Specifications ..... 28 Table 4-7. CMOS1.8 Signal Group DC Specifications.............................................. 29 Table 4-8. LVDS Signal Group DC Specifications ................................................... 29 Table 5-1. Thermal Design Power Specifications ................................................... 31 Table 5-2. Support for PROCHOT#/THERMTRIP# in Active and Idle States ............... 34 Table 6-1. Processor Pinout (Top ViewColumns 2131) ....................................... 40 Table 6-2. Processor Pinout (Top ViewColumns 1120) ....................................... 41 Table 6-3. Processor Pinout (Top ViewColumns 110) ........................................ 42 Table 6-4. PinoutOrdered by Signal Name ......................................................... 43

Datasheet

Revision History
Document Number 325314 Revision Number 001 Initial release. Description Revision Date April 2011

Datasheet

Introduction

Introduction
The datasheet describes the architecture, features, buffers, signal descriptions, power management, pin states, operating parameters, and specifications for the Intel Atom Processor Z670 (Core Processor and North Complex). Intel Atom Processor Z670 is the next generation low power IA-32 processor that is based on the new re-partitioning architecture targeted for tablets and sleek netbooks. The main components of Intel Atom Processor Z670 are: an IAcompatible processor core derived from the Intel Atom processor, a single-channel 32-bit DDR2 memory controller, a 3-D graphics engine, video decode engines, a 2-D display controller, a cDMI interface link to the Intel SM35 Express Chipset, and an LVDS interface to support a primary display interface link. An additional cDVO interface is used for pixel data to the Intel SM35 Express Chipset. Throughout this document, the Intel Atom Processor Z670 is referred as the processor and Intel SM35 Express Chipset is referred to as the chipset.

1.1

Processor Features
The following list provides some of the key features on this processor: Supports Intel Hyper-Threading Technology 2-wide instruction decode and in-order execution 512 KB, 8 way L2 cache Support for IA 32-bit architecture FCMB3 packaging technology Thermal management support using TM1 and TM2 On die Digital Thermal Sensor (DTS) for thermal management support using Intel Thermal Monitor 1 (TM1) and Intel Thermal Monitor 2 (TM2)

Advanced power management features including Enhanced Intel SpeedStep Technology Supports C0/C1(e)/C2(e)/C4(e) power states Intel Deep Power Down Technology (C6)

Datasheet

Introduction

1.2
1.2.1

Interfaces
System Memory Support
One channel of DDR2 memory 32-bit data bus Memory DDR2 transfer rates of 800 MT/s Supports 1 Gb, and 2 Gb devices Supports total memory size of 1 GB, and 2 GB Provides aggressive power management to reduce power consumption when idle Provides proactive page closing policies to close unused pages

1.2.2

Display Controller
Seven display planes: Display Plane A, Display Plane B, Display C/sprite, Overlay, Cursor A, Cursor B, and VGA Display Pipe A: Supports LVDS display interface Display Pipe B: Supports HDMI via chipset Maximum resolution (LVDS display): 1366 x 768 @ 18 bpp and 60 fps Supports 18 bpp Supports Non-Power of 2 Tiling Output pixel width: 24-bit RGB Supports NV12 video data format Supports 3 x 3 panel fitter Dynamic Power Saving Technology (DPST) 3.0 Support 16 x 256 byte tile size Supports overlay Supports global constant alpha blending

1.2.3

cDMI
Peak raw BW of cDMI link per direction = 400 MT/s using a quad-pumped 8-bit transmit and an 8-bit receive data bus Supports low power management schemes Supports CMOS interface

Datasheet

Introduction

1.2.4

cDVO
Peak raw BW of 800MT/s Supports low power management schemes Supports AGTL+ interface

1.2.5

LVDS
Maximum resolution (internal display) of: 1366 x 768 @ 18 bpp and 60 fps Dot clock range from 2083 MHz Four differential signal pairs: Three data pairs (up to 581 Mbps on each data link) and one clock pair Supports 18 bpp packed and 18 bpp loosely packed pixel formats Supports 24 bpp with a limited number of validated panels.

1.3

Terminology
Acronym ACPI AGTL+ CKE CMOS cDMI cDVO DDR2 DQ DQS DTS FSB GPIO GTL HPLL IERR iFSB LFM LGI Description Advanced Configuration and Power Interface Assisted Gunning Transceiver Logic Plus Clock enable Complementary metal-oxide semiconductor CMOS Direct Media Interface CMOS Digital Video Output Second-generation Double Data Rate SDRAM memory technology Memory data Memory data strobe Digital thermal sensor Front side bus General purpose input/output Gunning Transceiver Logic Host phase lock loop Internal error Internal front side bus Low Frequency Mode Legacy interface

Datasheet

Introduction

Acronym LVDS MSR NCTF

Description Low Voltage Differential Signaling, a high speed, low power data transmission standard used for display connections to LCD panels Model-specific register Non-Critical to Function. NCTF locations are typically redundant ground or non-critical reserved, so the loss of solder joint continuity at end of life conditions will not affect the overall product functionality. Non-maskable interrupt Processor unicore which processor memory controller, Power Management Unit and internal FSB Logic On Die Termination Platform Controller Hub Power Management Integrated Circuit Power Management Unit Resistor compensation System clock Self-Refresh Test access point Thermal control circuit Thermal Design Power Thermal Monitor 1 Thermal Monitor 2 Voltage regulator

NMI North Complex ODT PCH PMIC PMU RCOMP SCK SR TAP TCC TDP TM1 TM2 VR

1.4

Reference Documents
Document
Intel Atom Processor Z6xx Series Specification Update For the Intel Atom Processor Z670 on 45-nm Process Technology Intel SM35 Express Chipset Datasheet Intel SM35 Express Chipset Specification Update AP-485, Intel Processor Identification and the CPUID Instruction

Location/ Comments
325309-001 325308-001 325307-001 http://www.intel.com/ Assets/PDF/appnote/2 41618.pdf

Datasheet

Introduction

Document
Intel 64 and IA-32 Architectures Software Developer's Manuals Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A-M Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide Volume 3B: System Programming Guide NOTES: 1.

Location/ Comments

http://www.intel.com /products/processor/ manuals/index.htm

Contact your Intel representative for the latest revision and document number of this document.

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Datasheet

Signal Descriptions

Signal Descriptions
This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. The following notations are used to describe the signal type.

Table 2-1. Signal Types

Notations I O I/O Input Pin Output Pin Bi-directional Input/Output Pin Signal Type

Table 2-2. Buffer Types

Buffer Type Interface Description Assisted Gunning Transceiver Logic Plus: CMOS open drain interface signals that require termination. Refer to the AGTL+ I/O Specification for complete details.

AGTL+

cDVO, cDMI

CMOS, CMOS_OD cDMI, cDVO, LGI, LGIE 1.05-V CMOS buffer or CMOS open drain. Analog LVDS CMOS1.8 All LVDS DDR2 Analog reference or output: This may be used as a threshold voltage or for buffer compensation. Low-voltage differential signal output buffers 1.8-V CMOS buffer: These buffers can be configured as Stub Series Termination Logic.

2.1

Signal Description
This section provides a detailed description of Processor signals. The signals are arranged in functional groups according to their associated interface.

2.1.1

System Memory Interface

Table 2-3. System Memory Interface Signals

Signal SM_CK0 SM_CK0# Direction Type O CMOS1.8 O CMOS1.8 Description Differential DDR clock Complementary differential DDR clock.

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Signal Descriptions

Signal SM_SREN# SM_CKE[1:0]

Direction Type I CMOS1.8 O CMOS1.8 O CMOS1.8 O CMOS1.8 O CMOS1.8 O CMOS1.8 O CMOS1.8 O CMOS1.8 O CMOS1.8 I/O CMOS1.8 I/O CMOS1.8 O CMOS1.8 I CMOS1.8 O CMOS1.8 I Analog

Description Self-refresh enable: Signal from the chipset asserted after processor places DDR in self-refresh. Clock enable: SM_CKE is used for power control of the DRAM devices. There is one SM_CKE per rank. Chip select: These signals determine whether a command is valid in a given cycle for the devices connected to it. There is one chip select signal for each rank. Row address strobe: This signal is used with SM_CAS# and SM_WE# (along with SM_CS#) to define commands. Column address strobe: This signal is used with SM_WE#, SM_RAS#, and SM_CS# to define commands. Write enable: This signal is used with SM_CAS#, SM_RAS#, and SM_CS# to define commands. On Die Termination: Active Termination Control. Bank select: These signals define which banks are being addressed within each Rank. Multiplexed address: SM_MA signals provide multiplexed row and column address to memory. Data lines: SM_DQ signals interface to the DRAM data bus. Data strobes: These signals are used during writes and are centered with respect to data. During reads, these signals are driven by memory devices and are edge aligned with data. Data mask: One bit per byte indicating which bytes should be written. Receive enable in: This input enables the SM_DQS input buffers during reads. Receive enable out: Part of the feedback used to enable the DQS input buffers during reads. RCOMP: Connected to high-precision resistor on the motherboard. Used to dynamically calibrate the driver strengths.

SM_CS[1:0]#

SM_RAS# SM_CAS# SM_WE# SM_ODT[1:0] SM_BS[2:0] SM_MA[14:0] SM_DQ[31:0]

SM_DQS[3:0]

SM_DM[3:0] SM_RCVENIN SM_RCVENOUT SM_RCOMP

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Signal Descriptions

2.1.2

cDMI Interface

Table 2-4. cDMI Interface Signal

Signal Direction Type I Analog O CMOS O CMOS O CMOS O CMOS I CMOS I CMOS I CMOS I CMOS I Analog I Analog Description CDMI_RCOMP: Connected to high-precision resistors on the motherboard. Used for compensating cDMI pull-up/pulldown impedances. Data output: quad-pump (strobed) data bus from Processor to PCH. Data control character data control character output: Quad-Pump (strobed) indication that CDMI_TX[7:0] contains a control character instead of data. Line wakeup for output: When asserted, the PCH will power-up its receivers on CDMI_TX[7:0] and CDMI_TXCHAR#, and CDMI_TXSTB[0]. Data strobe output: Strobes for CDMI_TX[7:0] and CDMI_TXCHAR#. Data input: Quad-Pump (strobed) data bus from PCH to Intel Atom Processor Z670. Data control character input: Quad-pump (strobed) indication that CDMI_RX[7:0] contains a control character instead of data. Line wakeup for input: Power enable from PCH. Used to enable Receivers on CDMI_RX[7:0], CDMI_RXCHAR#, and CDMI_RXSTB_ODD#. Data strobe input: Strobes for CDMI_RX[7:0] and CDMI_RXCHAR#. Strobe Signals' Reference Voltage for DMI: Externally set by means of a passive voltage divider. Voltage should be 1/2 VCCP when configured for CMOS. Non-Strobe Signals' Reference Voltage for DMI: Externally set by means of a passive voltage divider. Voltage should be 1/2 VCCP when configured for CMOS.

CDMI_RCOMP[1:0]

CDMI_TX[7:0]

CDMI_TXCHAR#

CDMI_TXDPWR# CDMI_TXSTB_ODD#, CDMI_TXSTB_EVEN# CDMI_RX[7:0]

CDMI_RXCHAR#

CDMI_RXDPWR# CDMI_RXSTB_ODD#, CDMI_RXSTB_EVEN# CDMI_GVREF

CDMI_CVREF

2.1.3

cDVO Interface

Table 2-5. cDVO Interface Signals

Signal Direction Type I Analog O AGTL+ Description CDVO_RCOMP: Connected to high-precision resistors on the motherboard. Used for compensating pull-up/pulldown impedances. Data output: Quad-pump (strobed) data bus from Intel Atom Processor Z670 to PCH. 13

CDVO_RCOMP[1:0]

CDVO_TX[5:0]

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Signal Descriptions

Signal CDVO_STALL#

Direction Type I AGTL+ O AGTL+ O AGTL+ I AGTL+ I Analog I Analog

Description Stall: Allows PCH to throttle the sending of display data. Line wakeup for output: When asserted, the PCH will power-up its receivers on CDVO_TX[5:0] and CDVO_TXSTB_ODD#. Data strobe output: Strobes for CDVO_TX[5:0]. Vertical blank: Indication from PCH indicating the start of the vertical blank period. Strobe signals' reference voltage for CDVO: Externally set by means of a passive voltage divider. Voltage should be 2/3 VCCP when configured for GTL. Non-Strobe Signals' Reference Voltage for CDVO: Externally set by means of a passive voltage divider. Voltage should be 2/3 VCCP when configured for GTL.

CDVO_TXDPWR# CDVO_TXSTB_ODD#, CDVO_TXSTB_EVEN# CDVO_VBLANK#

CDVO_GVREF

CDVO_CVREF

2.1.4

LVDS Display Port Interface

Table 2-6. LVDS Display Port Interface Signals

Signal LA_DATAN[3:0] LA_DATAP[3:0] LA_CLKN LA_CLKP LA_IBG LA_VBG Direction Type O LVDS O LVDS O LVDS O LVDS I Analog I Analog Description Differential Data Output (Negative) Differential Data Output (Positive) Differential Clock Output (Negative) Differential Clock Output (Positive) External Voltage Ref BG: Connected to high-precision resistor on motherboard to VSS. External Voltage Ref BG: Requires external 1.25 V 2% supply.

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Signal Descriptions

2.1.5

LGI/LGIe (Legacy) Signals

Table 2-7. LGI/LGIe Legacy Signals

Signal Direction Type O CMOS Description Voltage ID: Connects to PMIC. Indicates a desired voltage for either VCC or VNN depending on the VIDEN[] pins. Resolution of 12.5 mV. Voltage ID enable: Connects to PMIC. Indicates which voltage is being specified on the VID pins: VIDEN[1:0] O CMOS 00 01 10 11 = = = = VID is invalid VID = VCC VID = VNN RSVD

VID[6:0]

THERMTRIP#

O CMOS_OD

Catastrophic Thermal Trip: The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 120 C. This condition is signaled to the system by the THERMTRIP# (Thermal Trip) pin. Processor hot: As an output, PROCHOT# (processor hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled. The TCC will remain active until the system de-asserts PROCHOT#. Voltage sense: Connects to PMIC. Voltage Regulator must connect feedback lines for VCC, VSS, and VNN to these pins on the package. BSEL1: Selects external reference clock for DDR2, cDMI, and cDVO frequencies. 1= 0= Reserved 100 MHz, for cDVO/DDR2-800MT/s.

PROCHOT#

I/O O: CMOS_OD I: CMOS

VSSSENSE, VCCSENSE, VNNSENSE

O Analog

BSEL1

O CMOS

IERR

O CMOS

IERR: Internal error indication (debug). Positively asserted. Asserted when the processor has had an internal error and may have unexpectedly stopped executing. Assertion of IERR is usually accompanied by a SHUTDOWN transaction internal to Processor which may result in assertion of NMI to the processor. The processor will keep IERR asserted until the POWERMODE[] pins take Processor to reset or Processor receives a reset message over cDMI. Voltage reference for BPM[3:0]#: 2/3 VCCP by means of an external voltage divider: 1k to VCCP, 2 K to VSS. Voltage reference: 2/3 VCCP by means of external voltage divider: 1 K to VCCP, 2 K to VSS.

GTLREF0 GTLREF1

I Analog I Analog

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Signal Descriptions

Signal

Direction Type I CMOS I CMOS

Description Power mode: The chipset is expected to sequence Processor through various states using the POWERMODE[] pins to facilitate cold reset, and warm reset. Reference clock: Differential 100 MHz.

PWRMODE[2:0]

BCLK_P/N

2.1.6

Debug and Miscellaneous Signals

Table 2-8. Debug and Miscellaneous Signals

Signal BPM[3:0]# Direction Type I/O AGTL+ I/O AGTL+ Description Break/perf monitor: Various debug input and output functions. Probe mode ready: The processors response to a PRDY# assertion. This signal indicates that the processor is in probe mode. Input is unused. Probe mode request: Assertion is a request for the processor to enter probe mode. Processor will respond with PRDY# assertion once it has entered. PREQ# can be enabled to cause the processor to break from C4 and C6. Internal 51 pull up, so no external pull-up required. Processor JTAG test clock: This signal provides the clock input for the processor Test Bus (also known as the Test Access Port). Requires an external 51 resistor to Vss. Processor JTAG test data input: This signal transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. Requires an external 51 resistor to VCCP. Processor JTAG test data output: This signal transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. Requires an external 51 resistor to VCCP. Processor JTAG test mode select: A JTAG specification support signal used by debug tools. Requires an external 51 resistor to VCCP. Processor JTAG test reset: Asynchronously resets the Test Access Port (TAP) logic. TRST# must be driven asserted (low) during processor power on reset. TRST# I CMOS Processor has an internal 51 pull-up to VCCP, unlike the Pentium M processor, the Intel Core2 processor, and the Intel Atom Z5xx processor. The Processor pull-up matches the Intel Pentium 4 processor and the IEEE specification. These pins should be treated as no connection (NC).

PRDY#

PREQ#

I/O AGTL+

TCK

I CMOS

TDI

I CMOS

TDO

O OD

TMS

I CMOS

RSVD

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Signal Descriptions

2.1.7

Power Signals

Table 2-9. Power Signals

Signal VCC VNN VCCP Type PWR PWR PWR Description Processor core supply voltage: Power supply is required for processor cycles. North Complex logic and graphics supply voltage. cDMI, cDVO, LGI, LGIe, JTAG, RCOMP, and power gating supply voltage. Needed for most bus accesses. Cannot be connected to VCCPAOAC during Standby or Self-Refresh states. DDR DLL and logic supply voltage: Required for memory bus accesses. Requires a separate rail with noise isolation. JTAG, C6 SRAM supply voltage: Needs to be on in Active or Standby. LVDS band gap supply voltage: Needed for LVDS display. HPLL Analog PLL and thermal sensor supply voltage. LVDS analog supply voltage: Needed for LVDS display. Requires a separate rail with noise isolation. LVDS I/O supply voltage: Needed for LVDS display. DDR2 self-refresh supply voltage: Powered during Active, Standby, and Self-Refresh states. DDR2 I/O supply voltage Required for memory bus accesses. Cannot be connected to VCC180SR during Standby or Self-Refresh states. I/O supply voltage. Ground pin

VCCPDDR VCCPAOAC LVD_VBG VCCA VCCA180 VCCD180 VCC180SR

PWR PWR PWR PWR PWR PWR PWR

VCC180 VMM VSS

PWR PWR

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Power Management

Power Management
Processor supports fine grain power management by having several partitions of voltage islands created through on-die power switches. The Intel Smart Power Technology (Intel SPT) software determines the most power efficient state for the platform at any given point in time and then provides guidance to turn ON or OFF different voltage islands on processor. For the scenario where Intel SPT has directed the processor to go into an Intel SIT idle mode, the processor waits for all partitions with shared voltage to reach a safe point and then turns them off.

3.1

Processor Core Low Power Features

When the processor core is idle, low-power idle states (C-states) are used to save power. More power savings actions are taken for numerically higher C-states. However, higher C-states have longer exit and entry latencies. Figure 3-1 shows the thread low power states. Figure 3-2 shows the package low power states. Note: STPCLK#, DPSLP#, and DPRSTP are internal signals only.

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Power Management

Figure 3-1. Thread Low Power States

Stop Grant
STPCLK# asserted STPCLK# de-asserted STPCLK# de-asserted STPCLK# asserted

C1/ MWAIT

STPCLK# de-asserted STPCLK# asserted

Core state break

C1/Auto Halt

HLT instruction

MWAIT(C1)

Halt break

C0
Core State break P_LVL4 or P_LVL6 MWAIT(C4/C6)

P_LVL2 or MWAIT(C2) Core state break

C2

C4 /C6

halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted) STPCLK# assertion and de-assertion have no effect if a core is in C2 or C4. P_LVL6 read is issued once the L2 cache is reduced to zero.

Figure 3-2. Package Low Power States

STPCLK# asserted SLP# asserted DPSLP# asserted DPRSTP# asserted

Normal
STPCLK# de-asserted

Stop Grant
SLP# de-asserted Snoop occurs

Sleep

DPSLP# de-asserted

Deep Sleep
DPRSTP# de-asserted

Deeper Sleep

Snoop serviced

Stop Grant Snoop

Deeper Sleep includes the C4 and C6 states Sleep and Deep Sleep are not states directly supported by the processor, but rather sub-states of Silverthornes C4/C6

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Power Management

3.1.1

Cx State Definitions
C0 StateFull On This is the only state that runs software. All clocks are running and the processor core is active. The processor can service snoops and maintain cache coherency in this state. All power management for interfaces, clock gating, are controlled at the unit level. C1 StateAuto-Halt The first level of power reduction occurs when the core processor executes an Auto-Halt instruction. This stops the execution of the instruction stream and greatly reduces the core processors power consumption. The core processor can service snoops and maintain cache coherency in this state. The Processor North Complex logic does not distinguish C1 from C0 explicitly. C2 StateStop Grant The next level of power reduction occurs when the core processor is placed into the Stop Grant state. The core processor can service snoops and maintain cache coherency in this state. The North Complex only supports receiving a single Stop Grant. Entry into the C2 state will occur after the core processor requests C2 (or deeper). C2 state will be exited, entering the C0 state, when a break event is detected. Processor must ensure that the DLLs are awake and the memory will be out of selfrefresh at this point. C1E and C2E States C1E and C2E states are transparent to the north complex logic. The C1E state is the same as the C1 state, in that the core processor emits a HALT cycle when entering the state. There are no other visible actions from the core processor. The C2E state is the same as the C2 state, in that the core processor emits a Stop Grant cycle when entering the state. There are no other visible actions from the core processor. C4 StateDeeper Sleep In this state, the core processor shuts down its PLL and cannot handle snoop requests. The core processor voltage regulator is also told to reduce the processors voltage. During the C4 state, the North Complex will continue to handle traffic to memory so long as this traffic does not require a snoop (i.e., no coherent traffic requests are serviced). The C4 state is entered by receiving a C4 request from the core processor/OS. The exit from C4 occurs when the North Complex detects a snoopable event or a break event, which would cause it to wake up the core processor and initiate the C0 sequence.

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Power Management

C4E The C4E state is essentially the same as the C4 state except that the core processor will transition to the Low Frequency Mode (LFM) frequency and voltage upon entry and exit of this state.

C6Deep Power Down Prior to entering the C6 state, the core processor will flush its cache and save its core context to a special on-die SRAM on a different power plane. Once the C6 entry sequence has completed, the core processor's voltage can be completely shut off. The key difference for the North Complex logic between the C4 state and the C6 state is that since the core processor's cache is empty, there is no need to perform snoops on the internal FSB. This means that bus master events (which would cause a popup from the C4 state to the C2 state) can be allowed to flow unimpeded during the C6 state. However, the core processor must still be returned to the C0 state to service interrupts. A residency counter is read by the core processor to enable an intelligent promotion/demotion based on energy awareness of transitions and history of residencies/transitions.

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Electrical Specifications

Electrical Specifications
This chapter contains signal group descriptions, absolute maximum ratings, voltage identification and power sequencing. This chapter also includes DC specifications.

4.1

Power and Ground Balls

The processor has Vcc and Vss (ground) inputs for on-chip power distribution. All power balls must be connected to their respective processor power planes, while all Vss balls must be connected to the system ground plane. Use of multiple power and ground planes is recommended to reduce I*R drop. The Vcc balls must be supplied with the voltage determined by the processor Voltage Identification (VID) signals.

4.2

Decoupling Guidelines
Due to large number of transistors and high internal clock speeds, the processor is capable of generating large current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values, if bulk decoupling is not adequate. Larger bulk storage (CBULK), such as electrolytic capacitors, supply current during longer lasting changes in current demand (for example, coming out of an idle condition). Similarly, capacitors act as a storage well for current when entering an idle condition from a running condition. To keep voltages within specification, output decoupling must be properly designed.

Caution: Design the board to ensure that the voltage provided to the processor remains within the specification. Failure to do so can result in timing violations or reduced lifetime of the processor.

4.3

Voltage Rail Decoupling

The voltage regulator solution needs to provide: Bulk capacitance with low effective series resistance (ESR). A low path impedance from the regulator to the processor. Bulk decoupling to compensate for large current swings generated during poweron, or low-power idle state entry/exit.

The power delivery solution must ensure that the voltage and current specifications are met, as defined in Table 4-4.

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4.4

Voltage Identification (VID)

The VCC and VNN voltage inputs use two encoding pins (VIDEN[1:0]) to enable the VID pin inputs and seven voltage identification pins (VID[6:0]) to select the power supply voltage. The VID/VIDEN pins for the processor are CMOS outputs driven by the processor VID circuitry. Table 4-2 specifies the voltage level corresponding to the state of VID[6:0]. A 1 in this refers to a high-voltage level and a 0 refers to a low-voltage level. For more details about PMIC design to support the processor power supply requirements, refer to the vendors specification.

4.4.1

VID Enable
Both VCC and VNN are variable in Intel Atom Processor Z670. Processor implements a new VID mechanism that minimizes the number of required pins. The VID for VNN and VCC are multiplexed on to the same set of pins and a separate 2-bit enable/ID is defined to specify what the driven VID corresponds to. One of the combinations is used to notify that the VID is invalid. This is used when the processor is in C6/Standby to tri-state the VID pins to save power.

Table 4-1. VIDEN Encoding

VIDEN[1:0] 00b 01b 10b 11b Description VID is invalid VID for VCC VID for VNN Reserved

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Electrical Specifications

4.4.2
Note:

VID Table

1. Processor will not support the entire range of the voltages listed in the VID table (grayed out). 2. VID codes below 0.3 V are not supported for VCC. Table 4-2. VID Table
VID[6:0] 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 24 VCC /VNN
1.5000V 1.4875V 1.4750V 1.4625V 1.4500V 1.4375V 1.4250V 1.4125V 1.4000V 1.3875V 1.3750V 1.3625V 1.3500V 1.3375V 1.3250V 1.3125V 1.3000V 1.2875V 1.2750V 1.2625V 1.2500V 1.2375V 1.2250V 1.2125V 1.2000V 1.1875V 1.1750V 1.1625V

VID[6:0] 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh

VCC /VNN
1.1000V 1.0875V 1.0750V 1.0625V 1.0500V 1.0375V 1.0250V 1.0125V 1.0000V 0.9875V 0.9750V 0.9625V 0.9500V 0.9375V 0.9250V 0.9125V 0.9000V 0.8875V 0.8750V 0.8625V 0.8500V 0.8375V 0.8250V 0.8125V 0.8000V 0.7875V 0.7750V 0.7625V

VID[6:0] 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh

VCC /VNN
0.7000V 0.6875V 0.6750V 0.6625V 0.6500V 0.6375V 0.6250V 0.6125V 0.6000V 0.5875V 0.5750V 0.5625V 0.5500V 0.5375V 0.5250V 0.5125V 0.5000V 0.4875V 0.4750V 0.4625V 0.4500V 0.4375V 0.4250V 0.4125V 0.4000V 0.3875V 0.3750V 0.3625V

VID[6:0] 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh

VCC /VNN
0.3000V 0.2875V 0.2750V 0.2625V 0.2500V 0.2375V 0.2250V 0.2125V 0.2000V 0.1875V 0.1750V 0.1625V 0.1500V 0.1375V 0.1250V 0.1125V 0.1000V 0.0875V 0.0750V 0.0625V 0.0500V 0.0375V 0.0250V 0.0125V 0.0000V 0.0000V 0.0000V 0.0000V

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Electrical Specifications

VID[6:0] 1Ch 1Dh 1Eh 1Fh

VCC /VNN
1.1500V 1.1375V 1.1250V 1.1125V

VID[6:0] 3Ch 3Dh 3Eh 3Fh

VCC /VNN
0.7500V 0.7375V 0.7250V 0.7125V

VID[6:0] 5Ch 5Dh 5Eh 5Fh

VCC /VNN
0.3500V 0.3375V 0.3250V 0.3125V

VID[6:0] 7Ch 7Dh 7Eh 7Fh

VCC /VNN
0.0000V 0.0000V 0.0000V 0.0000V

4.5

Absolute Maximum Ratings

Table 4-3 specifies absolute maximum and minimum ratings. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits. At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time, then when returned to conditions within the functional operating condition limits, it will either not function or its reliability will be severely degraded. Although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields.

Table 4-3. Absolute Maximum Ratings

Symbol VCC VNN VCCP/VCCQ VCCPDDR VCCPAOAC VMM LVD_VBG VCCA VCCA180 Parameter Processor core supply voltage North Complex logic and GFX supply voltage cDMI, cDVO, LGI, LGIe 1.05-V DDR2 DLL and logic supply voltage 1.05-V JTAG, C6 SRAM 1.2-V I/O supply voltage 1.25-V LVDS band gap supply voltage 1.5-V HPLL analog PLL and thermal sensor supply voltage 1.8-V LVDS analog supply voltage Minimum -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.1 -0.3 -0.3 Maximum 1.1 0.95 1.1 1.1 1.1 1.25 1.28 1.575 1.9 Unit V V V V V V V V V Note

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Electrical Specifications

Symbol VCCD180 VCC180SR VCC180 TJ TSUSTAINED

STORAGE

Parameter 1.8-V LVDS I/O supply voltage 1.8-V DDR2 self-refresh supply voltage 1.8-V DDR2 I/O supply voltage Operational junction temperature The ambient storage temperature limit (in shipping media) for a sustained period of time. The maximum device storage relative humidity for a sustained period of time.

Minimum -0.3 -0.4 -0.4 0 -5 C

Maximum 1.9 1.9 1.9 90 40 C

Unit V V V C

Note

1,2 4

RHSUSTAINED
STORAGE

60% @ 24 C

4,5

TIMESUSTAINE A prolonged or extended period of time; typically associated with D STORAGE customer shelf life. NOTE: 1.

Months

2. 3.

4. 5.

As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitors automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.2 for more details. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications. The storage temperature is applicable to storage conditions only. Storage within these limits will not affect the long-term reliability of the device. For functional operation, refer to the processor case temperature specifications. The JEDEC, J-JSTD-020 moisture level rating and associated handling practices apply to all moisture sensitive devices removed from the moisture barrier bag. Nominal temperature and humidity conditions and durations are given and tested within the constraints imposed by TSUSTAINED and customer shelf life in applicable Intel box and bags.

4.6

DC Specifications
Symbol Parameter Min. Typ. Max. Unit Notes
1,2

Table 4-4. Voltage and Current Specifications

VCCHFM VCCLFM VCCBOOT VNNBOOT VNN VCCP VCCQ VCCPDDR

VCC @ Highest Frequency Mode VCC @ Lowest Frequency Mode Default VCC for initial power on

AVID 0.7

VCCLFM VNN

1.15 AVID

V V V V

3 3 4 4 3 4

VNN supply voltage VCCP supply voltage VCCQ supply voltage VCCPDDR supply voltage

0.75 0.9975 0.9975 1.029 1.05 1.05 1.05

0.95 1.1025 1.1025 1.071

V V V V

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Electrical Specifications

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes
1,2

VCCPAOAC VMM LVD_VBG VCCA VCCA180 VCCD180 VCC180SR VCC180

VCCPAOAC supply voltage VMM supply voltage LVDS band gap reference voltage VCCA supply voltage VCCA180 supply voltage VCCD180 supply voltage VCC180SR supply voltage VCC180 supply voltage Processor Number Z670 Core Frequency HFM: 1.5 GHz LFM: 0.6 GHz

0.9975 1.14 1.225 1.47 1.746 1.71 1.71 1.71

1.05 1.20 1.25 1.5 1.8 1.8 1.8 1.8

1.1025 1.26 1.275 1.53 1.854 1.89 1.89 1.89 2.50 1.60 0.121 0.015 0.150 0.030 0.010 0.150 0.050 0.010 0.400

V V V V V V V V A A A A A A A A A A A A

IVCC

6,7 7 7 7 7 7 7 7 7,8,9 7 7

IVNN IVCCP IVCCQ IVCCPDDR IVCCPAOAC IVMM IVCCA IVCCA180 IVCCD180 IVCC180SR IVCC180 NOTES: 1. 2. 3.

VNN supply current VCCP supply current VCCQ supply current VCCPDDR supply current VCCPAOAC supply current VMM supply current VCCA supply current VCCA180 supply current VCCD180 supply current VCC180SR supply current VCC180 supply current

4. 5. 6. 7.

Maximum specifications are based on measurements done with currently existing workloads and test conditions. These numbers are subject to change. Specified at TJ = 90C. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State). Typical AVID range is 0.70V to 1.15V for VCC and 0.75V to 0.95V for VNN. This specification corresponds to what value gets driven by the processor. It is possible for firmware to override these values. Voltage specification of 2% includes AC and DC variations. The sum of AC noise and DC variations should not exceed 1.05V 2%. Specified at the nominal VCC. Peak Sustained Current is defined as the maximum sustainable current measured as an RMS value over 1s. 27

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Electrical Specifications

8. 9.

This is the sum of current on both rails. Specification based on LVDS panel configuration of 1024x600 resolution, 60Hz refresh rate, and 18bpp color depth.

Table 4-5. Differential Clock DC Specifications

Symbol Differential Clock (BCLK) VIH VIL VCROSS Input high voltage Input low voltage Crossing voltage Range of crossing points Differential output swing Input leakage current Pad capacitance 0.3 300 -5 1.2 1.45 1.15 -0.3 0.55 140 +5 2.0 V V V mV mV A pF Parameter Min. Typ. Max. Unit Notes

VCROSS
VSWING ILI CPAD

Table 4-6. AGTL+, CMOS, and CMOS Open Drain Signal Group DC Specifications
Symbol GTLREF CMREF RCOMP RODT VIH (GTL) VIL (GTL) VIH (CMOS) VIL (CMOS) VOH RTT (GTL) RTT (CMOS) RON (GTL) RON (CMOS) RON (CMOS_C) ILI CPAD Parameter GTL reference voltage CMOS reference voltage Compensation resistor Termination resistor Input high voltage GTL signal Input low voltage GTL signal Input high voltage CMOS signal Input low voltage CMOS signal Output high voltage Termination resistance Termination resistance GTL buffer on resistance CMOS buffer on resistance CMOS common clock buffer on resistance Input leakage current Pad capacitance Min. 27.73 GTLREF + 0.10 -0.10 CMREF + 0.10 -0.10 VCCP 0.10 46 46 21 42 42 1.6 Typ. 2/3 VCCP 1/2 VCCP 27.5 55 VCCP 0 VCCP 0 VCCP 55 55 25 50 50 2.1 Max. 27.78 VCCP + 0.10 GTLREF 0.10 VCCP + 0.10 CMREF 0.10 VCCP 61 61 29 55 58 100 2.55 Unit V V V V V V V A pF 10 11 3, 6 2, 4 3, 6 2, 4 6 7 11 5 12 12 8 9 Notes

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Electrical Specifications

NOTES: 1. 2. 3. 4. 5. 6. 7. Unless otherwise noted, all specifications in this table apply to all processor frequencies. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. VIH and VOH may experience excursions above VCCP. However, input signal drivers must comply with the signal quality specifications. RON is the pull-down driver resistance. Refer to processor I/O Buffer Models for I/V characteristics. Measured at 0.33*VCCP. GTLREF and CMREF should be generated from VCCP with a 1% tolerance resistor divider. The VCCP referred to in these specifications is the instantaneous VCCP. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at 0.33*VCCP. RTT is connected to VCCP on die. Refer to processor I/O buffer models for I/V characteristics. Specified with on die RTT and RON are turned off. VIN between 0 and VCCP. CPAD includes die capacitance only. No package parasitics are included. This is the external resistor on the component pins. On die termination resistance for CMOS is measured at 0.5*VCCP. RON for CMOS pull-down driver resistance. Refer to processor I/O Buffer Models for I/V characteristics. Measured at 0.5*VCCP.

8. 9. 10. 11. 12.

Table 4-7. CMOS1.8 Signal Group DC Specifications

Symbol VIH VIL VOH VOL NOTES: 1. 2. 3. 4. Unless otherwise noted, all specifications in this table apply to all processor frequencies. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. VIH and VOH may experience excursions above VCCP. However, input signal drivers must comply with the signal quality specifications. Parameter Input high voltage Input low voltage Output high voltage Output low voltage Min. (VCC180/2) + 0.125 -0.4 (VCC180/2) + 0.25 Typ. Max. 1.9 (VCC180/2) - 0.125 (VCC180/2) - 0.25 Unit V V V V Notes

Table 4-8. LVDS Signal Group DC Specifications

Symbol VOS VOS VOD Parameter Offset voltage Change in offset voltage Differential output voltage Min. 1.125 250 Typ. 1.25 350 Max. 1.375 50 450 Unit V mV mV Notes

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Electrical Specifications

Symbol VOD ISC ISCC IL

Parameter Change in differential output voltage Short-circuit current Short-circuit comment current Leakage current Dynamic offset Overshoot Ringback

Min. -380 50 50

Typ. 150 70 70

Max. 50 12 24 380 150 90 90

Unit mV mA mA A mV mV mV

Notes

NOTE: Unless otherwise noted, all specifications in this table apply to all processor frequencies.

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Thermal Specifications and Design Considerations

Thermal Specifications and Design Considerations

The processor requires a thermal solution to maintain temperatures within operating limits as set forth in Table 4-3. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system. Maintaining the proper thermal environment is the key to reliable, long-term system operation. A complete thermal solution includes both component and system level thermal management features. Note: Trading thermal solutions also involves trading performance. To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum junction temperature (TJ) specifications at the corresponding Thermal Design Power (TDP) value listed in Table 5-1. Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. The maximum junction temperature is defined by an activation of the processor Intel Thermal Monitor. Refer to Section 5.2 for more details. Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the TDP indicated in Table 5-1. The Intel Thermal Monitor feature is designed to help protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained period of time. For more details on the usage of this feature, refer to Section 5.2. In all cases, the Intel Thermal Monitor feature must be enabled for the processor to remain within specification.

Table 5-1. Thermal Design Power Specifications

Symbol Processor Number Core Frequency 1.5 GHz and HFM VCC 0.6 GHZ and LFM VCC Parameter Junction Temperature HD Streaming Scenario Power NOTES: 1. 2. The TDP specification should be used to design the processor thermal solution. The TDP is not the maximum theoretical power the processor can generate. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications. 31 Min 0 Thermal Design Power 3.0 Typ 1.02 Max 90 Unit Notes

TDP Symbol Tj

Z670

W Unit C W

1,2 Notes

3,4

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Thermal Specifications and Design Considerations

3.

4.

Scenario Power examines a common use case and may be more indicative of a more common power usage level as compared with the TDP. Measurement configuration assumes: LCD brightness 100nits, LCD 1024x800 10.1, USB touch panel, I2C sensors, SDIO WiFi on, 2GB DDR2, 73% PMIC efficiency, 93% discrete VR efficiency, Flash* v10.2. 720p, YouTube*.

5.1

Temperature Monitoring
The processor incorporates two methods of monitoring die temperature: By Intel Thermal Monitor By Digital Thermal Sensor (DTS)

The Intel Thermal Monitor (detailed in Section 5.2) must be used to determine when the maximum specified processor junction temperature has been reached.

5.2

Intel Thermal Monitor

The Intel Thermal Monitor helps control the processor temperature by activating the TCC (Thermal Control Circuit) when the processor silicon reaches its maximum operating temperature. The temperature at which the Intel Thermal Monitor activates the TCC is not user configurable. Bus traffic is snooped in the normal manner and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active. With a properly designed and characterized thermal solution, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be minor and hence not detectable. An under- designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the TCC is active continuously. The Intel Thermal Monitor controls the processor temperature by modulating (starting and stopping) the processor core clocks or by initiating an Enhanced Intel SpeedStep Technology transition when the processor silicon reaches its maximum operating temperature. The Intel Thermal Monitor uses two modes to activate the TCC: automatic mode and on-demand mode. If both modes are activated, automatic mode takes precedence. There are two automatic modes called the Intel Thermal Monitor 1 (TM1) and the Intel Thermal Monitor 2 (TM2). These modes are selected by writing values to the MSRs of the processor. After the automatic mode is enabled, the TCC will activate only when the internal die temperature reaches the maximum allowed value for operation. The Intel Thermal Monitor automatic mode must be enabled through IA-32 Firmware for the processor to be operating within specifications. Intel recommends that the TM1 mode and the TM2 mode be enabled on the processor.

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Thermal Specifications and Design Considerations

When the TM1 mode is enabled and a high temperature situation exists, the clocks will be modulated by alternately turning the clocks off and on at a 50 percent duty cycle. Cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase. Once the temperature has returned to a non-critical level, modulation ceases and TCC goes inactive. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near the trip point. The duty cycle is factory configured and cannot be modified. Also, automatic mode does not require any additional hardware, software drivers, or interrupt handling routines. Processor performance will be decreased by the same amount as the duty cycle when the TCC is active. When the TM2 mode is enabled and a high temperature situation exists, the processor will perform an Enhanced Intel SpeedStep Technology transition to the LFM. When the processor temperature drops below the critical level, the processor will make an Enhanced Intel SpeedStep Technology transition to the last requested operating point. The Intel Thermal Monitor automatic mode and Enhanced Intel SpeedStep Technology must be enabled through IA-32 Firmware for the processor to be operating within specifications. Intel recommends that TM1 and TM2 be enabled on the processors. TM1 and TM2 can co-exist within the processor. If both TM1 and TM2 bits are enabled in the auto-throttle MSR, TM2 will take precedence over TM1. However, if Force TM1 over TM2 is enabled in MSRs using IA-32 Firmware and TM2 is not sufficient to cool the processor below the maximum operating temperature, then TM1 will also activate to help cool down the processor. If a processor load-based Enhanced Intel SpeedStep Technology transition (through MSR write) is initiated when a TM2 period is active, there are two possible results: If the processor load-based Enhanced Intel SpeedStep Technology transition target frequency is higher than the TM2 transition based target frequency, the processor load-based transition will be deferred until the TM2 event has been completed. If the processor load-based Enhanced Intel SpeedStep Technology transition target frequency is lower than the TM2 transition based target frequency, the processor will transition to the processor load-based Enhanced Intel SpeedStep Technology target frequency point.

The TCC may also be activated using on-demand mode. If bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1, the TCC will be activated immediately independent of the processor temperature. When using on-demand mode to activate the TCC, the duty cycle of the clock modulation is programmable using bits 3:1 of the same ACPI Intel Thermal Monitor control register. In automatic mode, the duty cycle is fixed at 50% on, 50% off. However in on-demand mode, the duty cycle can be programmed from 12.5% on/87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-demand mode may be used at the same time automatic mode is enabled; however, if the system tries to enable the TCC using on-demand mode at the same time automatic mode is enabled and a high temperature condition exists, automatic mode will take precedence.

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Thermal Specifications and Design Considerations

An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point. Bus snooping and interrupt latching are also active while the TCC is active. Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also includes one ACPI register, one performance counter register, three MSRs, and one I/O pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or de-assertion of PROCHOT#. PROCHOT# will not be asserted when the processor is in the Sleep, Deep Sleep, and Deeper Sleep low power states (see Figure 3-2). If the platform thermal solution is not able to maintain the processor junction temperature within the maximum specification, the system must initiate an orderly shutdown to prevent damage. If the processor enters one of the above low power states with PROCHOT# already asserted, then PROCHOT# will remain asserted until the processor exits the low power state and the processor junction temperature drops below the thermal trip point. If the Intel Thermal Monitor automatic mode is disabled, the processor will operate out of specification. Regardless of enabling the automatic or on-demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a potentially catastrophic temperature. At this point the THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. Table 5-2. Support for PROCHOT#/THERMTRIP# in Active and Idle States
PROCHOT# (Bidirectional) System State Core State Core C0 C1/C1E S0 C2/C2E C4/C4E C6 Supported Supported Supported Ignored Ignored Input North Complex Optional Optional Optional Optional Optional Core Active Active Active Inactive Inactive Output North Complex Active Active Active Active Active THERMTRIP# North Complex Active Active Active Active Active

Core Active Active Active Not Guaranteed Inactive

5.2.1

Digital Thermal Sensor

The processor also contains an on die Digital Thermal Sensor (DTS) that is read using an MSR (no I/O interface). The processor has a unique digital thermal sensor thats temperature is accessible using the processor MSRs. The DTS is the preferred method of reading the processor die temperature since it can be located much closer to the hottest portions of the die and can thus more accurately track the die temperature and potential activation of processor core clock modulation using the Thermal Monitor. The DTS is only valid while the processor is in the normal operating state (the Normal package level low power state).

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Thermal Specifications and Design Considerations

Unlike traditional thermal devices, the DTS outputs a temperature relative to the maximum supported operating temperature of the processor (TJ_max). It is the responsibility of software to convert the relative temperature to an absolute temperature. The temperature returned by the DTS will always be at or below TJ_max. Catastrophic temperature conditions are detectable using an Out of Specification status bit. This bit is also part of the DTS MSR. When this bit is set, the processor is operating out of specification and immediate shutdown of the system should occur. The processor operation and code execution is not ensured once the activation of the Out of Specification status bit is set. The DTS-relative temperature readout corresponds to the Intel Thermal Monitor (TM1/TM2) trigger point. When the DTS indicates maximum processor core temperature has been reached, the TM1 or TM2 hardware thermal control mechanism will activate. The system designer is required to use the DTS to ensure proper operation of the processor within its temperature operating specifications. Changes to the temperature can be detected using two programmable thresholds located in the processor MSRs. These thresholds have the capability of generating interrupts using the core's local APIC. Refer to the Intel 64 and IA-32 Architectures Software Developer's Manuals for specific register and programming details.

5.2.2

Out of Specification Detection

Overheat detection is performed by monitoring the processor temperature and temperature gradient. This feature is intended for graceful shut down before the THERMTRIP# is activated. If the processors TM1 or TM2 are triggered and the temperature remains high, an Out Of Specification status and sticky bit are latched in the status MSR register and generates thermal interrupt.

5.2.3

Catastrophic Thermal Protection

The processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. Even with the activation of THERMTRIP#, which halts all processor internal clocks and activity, leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor. If the external thermal sensor detects a potentially catastrophic processor temperature, or if the THERMTRIP# signal is asserted by the processor, the VCC supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor. THERMTRIP# functionality is not ensured if the PWRGOOD signal is not asserted.

5.2.4

PROCHOT# Signal Pin

An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature has reached its maximum operating temperature. If TM1 or TM2 is enabled, then the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of

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Thermal Specifications and Design Considerations

PROCHOT#. Refer to the Intel 64 and IA-32 Architectures Software Developer's Manuals. The processor implements a bi-directional PROCHOT# capability to allow system designs to protect various components from overheating situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC using PROCHOT# can provide a means for thermal protection of system components. Only a single PROCHOT# pin exists at a package level of the processor. When the core's thermal sensor trips, the PROCHOT# signal is driven by the processor package. If only TM1 is enabled, PROCHOT# will be asserted and only the core that is above TCC temperature trip point will have its core clocks modulated. If TM2 is enabled and the core is above TCC temperature trip point, it will enter the lowest programmed TM2 performance state. It is important to note that Intel recommends that both TM1 and TM2 be enabled. When PROCHOT# is driven by an external agent, if only TM1 is enabled on the core, then the processor core will have the clocks modulated. If TM2 is enabled, then the processor core will enter the lowest programmed TM2 performance state. It should be noted that Force TM1 on TM2, enabled using IA-32 Firmware, does not have any effect on external PROCHOT#. If PROCHOT# is driven by an external agent when TM1, TM2, and Force TM1 on TM2 are all enabled, then the processor will still apply only TM2. PROCHOT# may be used for thermal protection of voltage regulators (VR). System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low) and activating the TCC, the VR will cool down as a result of reduced processor power consumption. Bi-directional PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR and rely on bi-directional PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP. With a properly designed and characterized thermal solution, it is anticipated that bi-directional PROCHOT# would only be asserted for very short periods of time when running the most power-intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss.

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Package Mechanical Specifications and Pin Information

Package Mechanical Specifications and Pin Information

This chapter describes the package specifications and pinout assignments.

6.1

Package Mechanical Specifications

The processor will be available in a 518 pin FCMB3 package. The package dimensions are shown in Figure 6-1.

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Package Mechanical Specifications and Pin Information

Figure 6-1. Package Mechanical Drawing

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Package Mechanical Specifications and Pin Information

6.2

Processor Pinout Assignment

Table 6-1, Table 6-2 and Table 6-3 are graphic representations of the processor pinout assignments. Table 6-4 lists the pinout by signal name.

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Package Mechanical Specifications and Pin Information

Table 6-1. Processor Pinout (Top ViewColumns 2131)

31 AL AK VSS 30 VSS CDVO_TXDP WR# VSS VSS LA_CLKN VSS VSS LA_VBG RSVD TP3 TP5 TP4 TP6 TP2 TP7 TP8 TP9 VNN VSS VNN VNN VNN VCC180 VCC180 SM_DQ1 SM_DQ3 SM_DQS1 SM_DQ2 SM_DM0 SM_DQ5 SSM_DQ4 SM_DQ6 SM_DQ7 VSS 31 SM_DQ9 30 VSS VSS SM_MA4 VSS SM_DQ8 SM_DQ11 29 28 SM_DQ10 SM_DM1 27 SM_MA12 VSS SM_DQ0 VSS VSS VSS SM_BS1 SM_MA2 VCC180 VSS SM_BS0 VSS SM_DQS0 SM_MA10 26 25 SM_DQ12 SM_MA3 VCC180 VNN VCC180 VCC180 SM_BS2 VCC180 VSS VCC180 VSS SM_MA7 VSS SM_DQ14 SM_DQ13 24 SM_DQ15 23 22 VSS SM_MA8 SM_MA0 VSS SM_RCVENO SM_RCVENI UT N SM_MA1 21 VCC180 VSS VCCPDDR VCCPDDR VSS TP10 VNNSENSE VNN VSS VNN VNN VCC180 VNN VSS VSS VNN VNN TP1 VSS VSS THRMDC VSS VNN VNN VNN VSS VNN VNN VNN VSS VNN VSS VSS VSS VCCPAOAC RSVD8 THRMDA VNN VNN VCC VSS VNN VSS VNN VNN VCC VSS VCC VSS RSVD9 VSS VCC VSS VCC VSS VSS LA_DATAP3 VCCP VCCD180 VSS LA_DATAN1 LA_DATAN3 29 CDVO_TX3 28 CDVO_TX2 CDVO_TX4 LA_DATAP1 27 CDVO_TXST B_ODD# 26 25 24 23 22 21 AL AK AJ AH AG AF VSS VCCP VSS VSS AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A CDVO_CVRE CDMI_RXCH CDMI_RXSTB CDMI_RX6 F AR# _EVEN# CDVO_TXST CDVO_RCO CDVO_VBLA CDMI_RXSTB CDVO_TX0 B_EVEN# MP0 NK# _ODD# VSS CDVO_STAL CDVO_TX5 L# VSS VCCD180 VSS VCCA180 VCCA180 VSS VSS VSS CDVO_TX1 CDVO_RCO MP1 VSS VCCQ_2 VSS VCCP VSS

AJ LA_DATAP0 LA_DATAN0 AH AG LA_CLKP

AF LA_DATAN2 LA_DATAP2 AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A LA_IBG RSVD

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Table 6-2. Processor Pinout (Top ViewColumns 1120)

20 AL AK AJ CDMI_RX7 19 CDMI_RX4 CDMI_RX3 VSS VSS 18 CDMI_RX1 17 CDMI_CVREF CDMI_RX0 VSS CDMI_RX2 CDMI_TXCHA R# VSS VNN VSS VCCP VSS VNN VSS VSS VCCP VSS VCCP VSS VCCP VSS CDMI_GVREF VSS 16 15 CDMI_TXDPW R# 14 CDMI_TX6 CDMI_TX7 VSS CDMI_TX5 VSS VCCP VSS VNN VSS VNN VSS CDMI_TX0 CDMI_TX4 13 12 CDMI_TX3 CDMI_TX2 VSS VCCQ_1 VSS 11 CDMI_TX1 AL AK AJ AH AG AF AE AD AC AB VCC VSS VCC VSS VCC VSS VNN VSS VNN VSS VNN VSS VNN VSS VNN VSS VCC VSS VNN VSS VNN VSS VCC VSS VCC VSS VNN VSS VNN VSS VCC VSS VCC VSS VCC VSS VNN VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS AA Y W V U T R P N M L VSS VSS VSS VSS VSS VSS K J VCC180 VSS VCC180 VSS SM_CK0 VSS VSS SM_RCOMP SM_MA9 20 SM_CKE0 19 18 SM_MA6 SM_CKE1 17 VCC180 VSS SM_CK0# VSS VCC180SR VSS SM_SREN# SM_MA5 16 15 SM_MA11 RSVD VCC180 VSS VCCPDDR VCCPDDR VSS VCC180 VSS SM_MA14 VSS SM_DQ25 SM_MA13 14 SM_DQ24 13 VSS VCC180 VSS VCC180 VSS SM_RAS# VSS SM_DQ27 SM_DQ26 12 11 SM_DQS3 SM_WE# VCC180 VSS H G F E D C B A

CDMI_RXDPW AH CDMI_RX5 R# AG VSS AF CDVO_GVREF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A

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Package Mechanical Specifications and Pin Information

Table 6-3. Processor Pinout (Top ViewColumns 110)

10 AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A SM_DM3 10 VSS SM_ODT0 VSS SM_DQ29 SM_DQ28 9 8 SM_DQ31 VCCPDDR VCCPDDR VSS VCC180 VSS SM_ODT1 SM_CS1# VSS SM_DQ17 SM_DQ30 7 SM_DQ16 6 5 VSS SM_DQ19 SM_DM2 SM_DQ18 4 3 VCC180 VSS VCCP VSS SM_CS0# SM_CAS# GTLREF1 VSS VSS SM_DQS2 SM_DQ21 VSS 2 1 VCCP VSS VSS VCCP VCCPAOAC VSS TDO BSEL1 VSS VSS RSVD SM_DQ23 SM_DQ22 SM_DQ20 VSS VNN VSS VNN VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VNN VSS VNN VSS VSS VCCP RSVD RSVD VSS VSS TMS TCK RSVD VSS TDI VNN VCCA VCC VCCA VSS RSVD VSS VSS VSS BCLK_P RSVD RSVD TRST# VCC VSSSENSE VCC VSS VCC VSS VCC VCC VCCSENSE VSS RSVD VCCPAOAC BCLK_N RSVD VCCP VSS IERR VSS VCCP VSS VCCP 9 8 7 PRDY# GTLREF0 VSS RSVD VSS VCCP VSS VNN VCCP VCCPAOAC VCC VSS VCC VCC VSS VCC VCC VCCA VNN VSS THERMTRIP# VIDEN0 VSS VSS VCC VSS VCC VSS VCC VID5 VSS PREQ# VSS 6 5 BPM2# 4 BPM1# BPM3# VSS VID2 RSVD VID3 VSS VSS PWRMODE1 PWRMODE2 VIDEN1 PWRMODE0 VCC RSVD 3 2 VID6 VID4 VSS VID0 RSVD RSVD PROCHOT# VID1 1 VSS AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A CDMI_TXSTB CDMI_RCOM _ODD# P1 CDMI_TXSTB CDMI_RCOM _EVEN# P0 VSS BPM0# VSS

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Package Mechanical Specifications and Pin Information

Table 6-4. PinoutOrdered by Signal Name

Pin Name BCLK_P BCLK_N BPM0# BPM1# BPM2# BPM3# BSEL1 CDMI_CVREF CDMI_RXDPWR# CDMI_TXDPWR# CDMI_GVREF CDMI_RCOMP0 CDMI_RCOMP1 CDMI_RX0 CDMI_RX1 CDMI_RX2 CDMI_RX3 CDMI_RX4 CDMI_RX5 CDMI_RX6 CDMI_RX7 CDMI_RXCHAR# CDMI_RXSTB_ODD# CDMI_RXSTB_EVEN# CDMI_TX0 CDMI_TX1 CDMI_TX2 CDMI_TX3 CDMI_TX4 CDMI_TX5 CDMI_TX6 CDMI_TX7 CDMI_TXCHAR# CDMI_TXSTB_ODD# Pin # M2 N1 AH9 AL4 AL5 AK4 G4 AL17 AH20 AL15 AK16 AK9 AL8 AK17 AL18 AH17 AK19 AL19 AH19 AL21 AK20 AL24 AK22 AL22 AH13 AL11 AK12 AL12 AK13 AH14 AL14 AK14 AH16 AL9 Pin Name CDMI_TXSTB_EVEN# CDVO_CVREF CDVO_TXDPWR# CDVO_GVREF CDVO_RCOMP0 CDVO_RCOMP1 CDVO_STALL# CDVO_TX0 CDVO_TX1 CDVO_TX2 CDVO_TX3 CDVO_TX4 CDVO_TX5 CDVO_TXSTB_ODD# CDVO_TXSTB_EVEN# CDVO_VBLANK# GTLREF0 GTLREF1 IERR LA_CLKN LA_CLKP LA_DATAN0 LA_DATAN1 LA_DATAN2 LA_DATAN3 LA_DATAP0 LA_DATAP1 LA_DATAP2 LA_DATAP3 LA_IBG LA_VBG TP1 TP2 TP4 Pin # AK10 AL25 AK30 AF20 AK24 AH23 AH27 AK27 AH24 AL28 AL29 AK28 AH26 AL27 AK26 AK23 AK7 D4 AH10 AG30 AH31 AJ30 AG28 AF31 AF28 AJ31 AJ28 AF30 AD28 AE31 AD30 W30 W31 AA30 Pin Name TP6 TP8 TP10 TP3 TP5 TP7 TP9 RSVD8 PRDY# PREQ# PROCHOT# PWRMODE0 PWRMODE1 PWRMODE2 SM_ODT1 SM_ODT0 RSVD7 SM_BS0 SM_BS1 SM_BS2 SM_CAS# SM_CK0 SM_CK0# SM_CKE0 SM_CKE1 SM_CS0# SM_CS1# SM_DM0 SM_DM1 SM_DM2 SM_DM3 SM_DQ0 SM_DQ1 SM_DQ10 Pin # Y30 U30 T30 AB31 AA31 V31 T31 Y28 AL7 AK6 AF1 AC1 AE2 AD2 D8 D9 E2 D26 G28 J28 E4 D19 D18 A19 A17 D5 D7 F30 A27 B4 A10 J30 J31 B28

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Package Mechanical Specifications and Pin Information

Pin Name SM_DQ11 SM_DQ12 SM_DQ13 SM_DQ14 SM_DQ15 SM_DQ16 SM_DQ17 SM_DQ18 SM_DQ19 SM_DQ2 SM_DQ20 SM_DQ21 SM_DQ22 SM_DQ23 SM_DQ24 SM_DQ25 SM_DQ26 SM_DQ27 SM_DQ28 SM_DQ29 SM_DQ3 SM_DQ30 SM_DQ31 SM_DQ4 SM_DQ5 SM_DQ6 SM_DQ7 SM_DQ8 SM_DQ9 SM_DQS0 SM_DQS1 SM_DQS2 SM_DQS3 SM_MA0 SM_MA1 44

Pin # A29 B25 A24 B24 A23 A6 B7 A4 B5 G30 C1 B2 D1 D2 A13 B14 A12 B12 A9 B9 H31 A7 B8 D31 E31 C31 B31 B29 A30 B26 G31 B3 B11 D21 A21

Pin Name SM_MA2 SM_MA3 SM_MA4 SM_MA5 SM_MA6 SM_MA7 SM_MA8 SM_MA9 SM_MA10 SM_MA11 SM_MA12 SM_MA13 SM_MA14 SM_RAS# SM_RCOMP SM_RCVENIN SM_RCVENOUT SM_SREN# SM_WE# TCK TDI TDO RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

Pin # F28 D25 D29 A16 B18 D24 D22 A20 A26 B15 D28 A14 D14 D12 B19 B21 B22 B16 D11 H2 F1 H4 D15 G2 L2 L4 K1 M4 M1 P2 P4 U28 W28 AK3 AG1

Pin Name RSVD RSVD RSVD THERMTRIP# TMS TRST# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

Pin # AG2 AG4 AH7 AE4 J2 J1 AA10 AA12 AA14 AA16 AA18 AA2 AA20 AA22 AA4 AA7 AA8 AB1 AB3 U1 U10 U12 U14 U16 U18 U2 U20 U22 U24 U3 U4 U7 U8 W1 W10 Datasheet

Package Mechanical Specifications and Pin Information

Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC180 VCC180 VCC180 VCC180 VCC180 VCC180 VCC180 VCC180 VCC180 VCC180 VCC180 VCC180 VCC180 VCC180 VCC180 VCC180 VCC180 VCC180 VCC180 VCC180 VCC180SR VCCA VCCA Datasheet

Pin # W12 W14 W16 W18 W2 W20 W22 W24 W3 W4 W7 W8 F12 F14 F18 F20 F24 F26 F8 H12 H14 H18 H20 H24 H26 H8 K28 K30 L29 L31 M28 M30 D16 P6 T1

Pin Name VCCA VCCA180 VCCA180 VCCD180 VCCD180 VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCQ_1 VCCQ_2 VCCPAOAC VCCPAOAC VCCPAOAC VCCPAOAC VCCPDDR VCCPDDR VCCPDDR VCCPDDR VCCPDDR VCCPDDR VCCSENSE

Pin # T6 AD24 AF24 AD26 AF26 K7 AC28 AC5 AD10 AD14 AD16 AD20 AD22 AD8 AF10 AF14 AF16 AF22 AF8 F6 H6 M6 AH12 AH22 AB4 AA28 K5 P1 F10 F16 F22 H10 H16 H22 T3

Pin Name VID0 VID1 VID2 VID3 VID4 VID5 VID6 VIDEN0 VIDEN1 RSVD9 VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN

Pin # AH2 AJ1 AH4 AH3 AK2 AH6 AL2 AD4 AD1 AA24 AA26 AD12 AD18 AD6 AF12 AF18 AF6 L26 M25 M29 M31 N10 N12 N14 N16 N18 N20 N22 N24 N26 N28 N30 N8 P25 P28 45

Package Mechanical Specifications and Pin Information

Pin Name VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNN VNNSENSE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 46

Pin # P30 R10 R12 R14 R16 R18 R20 R22 R24 R26 R29 R31 R7 R8 T25 U26 V25 W26 Y25 T29 A2 A31 AA29 AB2 AB29 AC11 AC13 AC15 AC17 AC19 AC21 AC22 AC25 AC3 AC9

Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Pin # AC30 AD29 AD3 AD31 AE11 AE13 AE15 AE17 AE19 AE21 AE23 AE25 AE29 AE5 AE7 AE9 AF29 AF3 AG10 AG14 AG16 AG20 AG22 AG26 AG3 AG5 AG8 AH29 AJ11 AJ12 AJ14 AJ15 AJ17 AJ18 AJ19

Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Pin # AJ2 AJ21 AJ22 AJ24 AJ25 AJ27 AJ29 AJ4 AJ5 AJ7 AJ8 AJ9 AL1 AL30 AL31 B1 C10 C12 C13 C14 C16 C17 C19 C20 C21 C23 C24 C26 C27 C29 C3 C30 C6 C7 C9 Datasheet

Package Mechanical Specifications and Pin Information

Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Datasheet

Pin # D3 E12 E14 E18 E20 E24 E26 E29 E6 E8 F3 G11 G13 G15 G17 G19 G21 G23 G25 G29 G3 G5 G7 G9 H29 J29 J3 J4 K12 K13 K14 K18 K19 K20 K24

Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Pin # K25 K3 K9 M11 M13 M15 M17 M19 M21 M23 M3 M8 M9 N3 N7 P11 P13 P15 P17 P19 P21 P23 P29 P3 P31 P8 P9 R2 R4 T11 T13 T15 T17 T19 T21

Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSSENSE

Pin # T23 T28 T8 T9 V11 V13 V15 V17 V19 V2 V21 V23 V29 V4 V8 V9 W29 Y1 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y3 Y6 Y8 Y9 G1 V6

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