Code No: M0523 /R07

Set No. 1

IV B.Tech. I Semester Regular Examinations, November 2010 ADVANCED COMPUTER ARCHITECTURE (Computer Science & Engineering)
Time: 3 Hours Answer any FIVE Questions All Questions carry equal marks ******* 1. (a) Derive a formula for CPU performance. Explain the parameters that are constituted in the
equation. (b) State Amdahls law, what is the role of Amdahls law in improving performance and how to distribute resources to improve cost performance. Explain with example.

Max Marks: 80

2. (a) How is memory address interpreted? What object is accessed as a function of the address
and the length? (b) How is the type of an operand designated? 3. (a) Write notes on dynamic scheduling. (b) Write the steps involved in handling an instruction with a branch target buffer.

4. (a) What is meant by trace scheduling? Explain with a neat flow chart.
(b) Consider the code fragment A[i]=A[i]+B[i]

T A[i]=0

B[i]=

C[i]= How can this code be effectively scheduled? Explain. (c) How is loop level parallelism is detected and enhanced?

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Code No: M0523 /R07

Set No. 1

5. Describe the concept of virtual memory, fast address translation using translation look aside buffer. 6. (a) What is multiprocessor cache coherence? How is write invalidate protocol implemented? Explain. (b) What is the effect of multiprogramming and OS workload on cache performance? 7. Describe the different levels of RAID in detail. 8. (a) What is a simple network? Describe the software steps for two machines to communicate. (b) What is meant by latency and effective bandwidth? Derive formula.

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Code No: M0523 /R07

Set No. 2

IV B.Tech. I Semester Regular Examinations, November 2010 ADVANCED COMPUTER ARCHITECTURE (Computer Science & Engineering)
Time: 3 Hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ******* 1. (a) What are the key characteristics of embedded computers? What is the task of computer designer (b) What are the trends that designers must be aware of in implementation technology and the use of computers? 2. (a) Mention the different types of addressing modes? Discuss their meaning and usage with examples. (b) Give the category of instruction operators with examples. 3. (a) How is high performance instruction delivery and indirect branches are dealt with prediction return address. (b)Describe the different techniques to overcome data hazards. 4. (a) What is a conditional instruction? Explain in brief. (b) What is a super block? Give an example. How can a super block with only one entrance be constructed? 5. (a) What are the restrictions in placement of a block? (b) What happens on a cache miss? What does cache do on a read and write miss? How does instruction cache and data cache perform during cache miss? 6. (a) Describe write update protocol with an example. (b) Write short notes on relaxed consistency model. 7. (a) How does the CPU address an I/O device that it needs to send or receive data? Show the interface between storage device to the CPU. (b) Define failure. What is the relation between fault, error and failure. 8. (a) Write notes on ethernet. (b) What are the issues in interconnecting networks?

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Code No: M0523 /R07

Set No. 3

IV B.Tech. I Semester Regular Examinations, November 2010 ADVANCED COMPUTER ARCHITECTURE (Computer Science & Engineering)
Time: 3 Hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ******* 1. (a) What are the functional requirements that need to be considered in the design of a new machine? (b) How do you measure the performance of a computer?
2. (a) Classify instruction set architecture. For the code sequence C=A+B, Illustrate how

these classes of instruction set appear? (b) What are the advantages and disadvantages of a register- register, registermemory and memory-memory architectures?
3. Draw the state diagram for a 2 bit prediction scheme. Discuss how this scheme works. 4. Discuss the role of loop unrolling and code scheduling to improve ILP. 5. (a) Derive an equation for miss penality.

(b) Derive the several techniques to reduce the miss rate. i) Larger block size ii) Larger cache iii) Higher associativity iv) Compiler optimizations
6. (a) How are spin locks implemented using coherence?

(b) What are the performance challenges of synchronization?

7. (a) What is the relation between throughput and response time?

(b) Write notes on block interleaved parity and distributed block interleaved parity.
8. (a) What is meant by warm hole routing? What are advantages of wormhole routing?

(b) Describe cube network topology with a diagram.

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Code No: M0523 /R07

Set No. 4

IV B.Tech. I Semester Regular Examinations, November 2010 ADVANCED COMPUTER ARCHITECTURE (Computer Science & Engineering)
Time: 3 Hours Answer any FIVE Questions All Questions carry equal marks *******
1. (a) What are the different trends and factors that affect cost and how it changes over time? (b) What are the different computing environments? 2. (a) How are the instructions encoded into a binary representation for execution by the processor? (b) What are the code optimizations performed by modern compiler? 3. (a) What are the different types of dependences? Explain data, name, control. (b) What are the different data hazards? Mention. Explain. 4. (a) How are dependences in a program found? What are the different ways in finding? (b) The following loop has multiple types of dependences. Find all the true dependences , output dependences and anti dependences, and eliminate the output dependences by renaming. for( i=1; i<=100; i=i+1) { y[i]=x[i] / c; X[i]=x[i] + c; Z[i]=Y[i]+c; Y[i]=c-Y[i]; } 5. (a) Derive the equation for calculating memory stall cycles. (b) Assume we have a computer where the clocks per instruction is 1.0 when all memory accesses hit in the cache. The only data accesses are loads and stores, and these total 50% of the instructions. If the miss penalty is 25 clock cycles and the miss rate is 2%, how much faster would the computer be if all instructions were cache hits? 6. (a) Show diagrammatically the actions to which an individual cache responds in directory based protocol. (b) How do you convert thread level parallelism into instruction level parallelism? 7. What are the different types of storage devices? Discuss the characteristics of all storage devices. 8. What is a cluster? How is it designed? Explain in detail.

Max Marks: 80

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