An RF Power Harvesting System with Input-Tuning

for Long-Range RFID Tags

Alireza Sharif Bakhtiar, M.Sadegh Jalali, and Shahriar Mirabbasi
Department of Electrical and Computer Engineering, University of British Columbia
Vancouver, BC, Canada
{alirezasb, sadegh, shahriar}@ece.ubc.ca

AbstractIn this paper, an RF power harvesting system
with automatic input tuning for long-range RFID tags is
described. The system uses a high quality factor LC-matching
network to boost the voltage of the received RF signal. Then a
new high-efficiency voltage rectifier is used to extract DC
voltage from the signal. In order to maximize the voltage gain of
the matching circuit, a tuning loop automatically adjusts the
center frequency of the input matching network to achieve the
optimum output DC voltage. The loop uses a low-power
up/down counter. The power of the counter is optimized by
minimizing the number of unnecessary internal transitions. A
proof-of-concept system is designed and simulated in a 0.13m
CMOS. It achieves an efficiency of 50% which compares
favourably with that of current state-of-the-art RF power
harvesting systems.
I. Introduction
Wireless power transmission has become increasingly
important over the past few years. The concept of remotely
transferring power to a circuit either instead of or
complimentary to using a battery has become popular in
applications where cost, weight, longevity, and reliability are
important. One of the prominent applications of wireless
power transmission is in passive radio frequency
identification (RFID) tags. In these systems a primary user
(reader) sends a radio frequency (RF) signal with a maximum
transmit power constraint (e.g. 4W for North America [1]) to
the secondary user (tag). A rectifier block in the tag extracts
the power from the received RF signal and provides a DC
supply to its internal circuits. Depending on the type of the
tag, internal circuits can vary from simple digital circuits with
power consumption of a few W to more complex circuits
with sensors and interface blocks consuming a few mW.
A major design challenge in remotely powered systems is
to efficiently extract a DC voltage from the received RF
signal. As the distance between the reader and the tag
increases the received RF power rapidly decreases (refer to
Friis formula in Section III). Therefore, there is a practical
limit on the maximum operating distance between the tag and
the reader. To increase this distance the power consumption
of the tag has to be optimized and/or the efficiency of the
rectifier circuit must be improved. In this paper we propose
an efficient rectifier in combination with a high quality factor
(Q) matching network for extracting the RF power. A tuning
circuit is utilized to tune the matching network over the entire
bandwidth. The remainder of the paper is organized as
follows. Section II describes modeling of the antenna and the
corresponding matching network. Section III presents the
proposed rectifier. Section IV explains the operation of the
tuning loop; Section V presents the simulation results.
Concluding remarks are provided in Section VI.
II. Overview of RF Power Harvesting System
Fig. 1 shows different blocks of a generic RF power
harvesting unit. The tuning circuit of the proposed system is
shown with dashed lines. The tag uses an antenna to receive
the RF signal and transfers this signal to the (on-chip)
rectifier. For maximum power transfer a matching network is
generally used to match the impedance of the antenna to input
impedance of the subsequent stages. In [2], different first-
order matching networks are discussed. In [3], a higher-order
passive network with wideband matching capabilities is
proposed. The latter approach assumes that the input signal is
spread over a wide range of spectrum. Most of these
matching techniques use metal strips and antenna design
techniques to create matching impedances, but in [4] a
matching network with voltage boosting capabilities has been
integrated on chip. In this work, we use an external series
matching inductance with a high Q to boost the voltage as
much as possible prior to applying it to the rectifier. This type
of matching is more suitable for antennas with lower radiative
resistance, and potentially the required external inductance
can be incorporated into the antenna design.
The next block in the RF power harvesting unit is the
rectifier. This block must rectify the RF signal and efficiently
extract a DC voltage to supply power to the circuits on tag.
Dickson-based rectifiers [5] are commonly used for RFID
applications [4, 6 - 8]. One challenge of implementing
Dickson rectifier in CMOS technology is the threshold-
voltage (V
th
) drop on diode-connected transistors. This
voltage drop can be reduced either by including a voltage
source between the drain and gate of diode-connected
transistors to reduce their turn on voltage [6, 7] or in more
advanced technologies by using zero or low-V
th
devices [4,
8]. Both approaches increase the reverse current of transistors
when the transistors must be turned off and thus reduce the
efficiency of the rectifiers. In [3] a V
GS
with reverse polarity
Matching
Network
Antenna
Tuning Loop
Rectifier Supply
Voltage
Figure 1. Block diagram of a generic RF power harvesting
system (the proposed tuning loop is also included)
978-1-4244-5309-2/10/$26.00 2010 IEEE 4085
reduces the reverse current of transistors. In the rectifier
proposed in this paper two symmetrical stages are used to
produce all voltages with zero and 180 phase shifts. These
voltages are used to turn on transistors with |V
GS
| equal to the
maximum voltage swing, and turn them off with a reverse
polarity V
GS
to minimize the reverse current. As will be
explained in Section IV, both NMOS and PMOS transistors
are used in each stage to further decrease the reverse current.
Furthermore, in the proposed system a tuning loop is also
added to automatically adjust the center frequency of the
matching network. To achieve the maximum voltage boosting
from the matching network, the center frequency of the
network is tuned to that of the input RF signal. This
adjustment is done by measuring the output voltage of the
rectifier and changing the capacitance of the matching
network. Circuits in this loop must operate with very low
supply voltage to facilitate the start-up operation, and low
power to reduce the power overhead until the input matching
network is tuned. A low-power counter is designed to hold
the output of the tuning circuit when the loop is turned off to
further reduce the power overhead
III. Modeling and Matching Circuit
The reader radiates the power P
ud
to the tag antenna.
According to Friis formula [9] the power that the tag antenna
can supply to its matched load (P
A
) is;
P
A
= P
ud
0
t
0

(
z
4nr
)
2


(1)
where G
r
and G
t
are the antenna gains of the receiver and the
transmitter respectively, z is the wavelength of the incoming
signal, and r is the distance between the transmitter and the
receiver. The tag antenna can be modeled as a voltage source
in series with a radiative resistance, R
A
. R
A
depends on the
antenna geometry. The amplitude of the voltage source V
A
is
given by I
A
= 8P
A
R
A
. The matching inductance L
match
and
the input capacitance of the chip, C
in
, form an LC-matching
network (Fig. 2). For this LC-network the input impedance
Z
in
at resonance frequency is (ideally) real and is given by,
R
n
=
R
1 +
2
(2)
where = RC
0
is the quality factor of the input impedance
[10], R is the perceived input resistance of the circuit at
resonance that also models series resistances of L
match
and C
in

and the real part of the rectifier input impedance (which
depends on the load current of the rectifier, number of
rectifier stages, and transistors dimensions). C
in
is the
equivalent input capacitance of the rectifier plus the parasitic
capacitances of the pads, ESD protection devices, etc, and

0
is the resonance frequency of the network. For maximum
power transfer, R
in
, i.e., real part of Z
in
at resonance, must be
equal to R
A
. Assuming proper impedance matching between
the antenna and the rectifier, the voltage gain of the matching
circuit which is the ratio of the output voltage amplitude
(input of the rectifier, V
rectifier
) to V
A
can be expressed as,
I
cct]c
I
A
=
1
2
1 +
2
=
1
2
1 + (RC
n

0
)
2
(3)

Figure 2. A simplified model of the antenna and the series matching network
Although according to (3) increasing C
in
(for a given R and

0
) increases voltage gain of the matching network, to keep
the antenna and the input impedance matched, R
A
must be
decreased (refer to (2)). Smaller R
A
produces smaller V
A
for a
given P
A
. It can be shown that for matched
antenna I
cct]c
= 2P
A
R regardless of C
in
. In this design,
we use C
in
which mostly consists of the parasitic capacitances
as a part of the matching network to match R to R
A
. It should
be noted that for very large C
in
, R
in
will be excessively small
and designing an antenna with such a low radiative resistance
to match R
in
becomes difficult. This fact puts a limit on the
maximum value for C
in
.
IV. Rectifier
In this section, the design of the proposed high-efficiency
rectifier stage (as shown in Fig. 3(c)) is described. There are
two major sources of power dissipation in rectifiers that lower
the efficiency. (1) The voltage drop across transistors of the
rectifier, and (2) the reverse current. We refer to both NMOS
and PMOS transistors of the rectifier as rectifier devices.
When the voltage across a rectifier device becomes positive
the current passes through the device and creates a forward
voltage drop across the device. This voltage drop depends on
the device aspect ratio, amount of the forward current, and
the value of its overdrive voltage, |I
uS
| - |I
th
|. When the
polarity of the voltage across a rectifier device changes the
device is expected to turn off and its current drops to zero.
However, in practice the rectifier devices pass some amount
of reverse current when they are off. This reverse current
dissipates power (note that |V
DS
| is not necessarily small when
the rectifier device is off). The proposed rectifier uses two
symmetrical Dickson stages [5] (Fig. 3(a)) connected to
different ends of the antenna, Fig. 3(b). Therefore, all
voltages with 0 and 180 phase shifts are produced. These
voltages are used to turn on rectifier devices with |I
uS
| =
I
cct]c
, where V
rectifier
is the maximum available voltage
swing. To overcome the reverse current problem, a same
amplitude |V
GS
| with the reverse polarity is applied to the
rectifier devices that are supposed to be off. In addition, a
PMOS transistor is added to each rectifier device to avoid
V
GD, NMOS
>> 0 or V
GD, PMOS
<< 0 when V
DS,NMOS
< 0 or V
DS,
PMOS
> 0 respectively and thus to avoid turning on the
transistors in the reverse direction. The bulk terminals of
PMOS transistors are connected to their drains. In this way
due to the body effect V
th
decreases when the transistor is
passing forward current and increases when the transistor is
supposed to be off. To avoid the additional cost of NMOS
transistors with isolated local substrate (triple-well
technology), all NMOS transistors share the same substrate
which is connected to ground. Therefore, V
th
of NMOS
transistors will increase (the increase in latter stages is more
4086
pronounce) which in turn will increase the forward voltage
drop on NMOS transistors of these stages. For generating
relatively large supply voltages this increase in NMOS V
th

becomes problematic. One possible solution is to replace the
NMOS transistors with PMOS transistors whose gates are
connected to the gate of the previous stage PMOS transistor.
However, in this design due to the relatively low target
supply voltage (1V) this approach is not used.
V. Tuning Circuit
As explained in Section II, the matching circuit
maximizes the power transfer at a certain frequency.
However, the matching network only shows the desirable
performance when the center frequency of the matching
network is sufficiently close to that of the incoming RF
signal. Thus, a tuning loop is used to ensure that the center
frequency of the matching network remains close to that of
the RF signal. This tuning loop is essential when using high-
Q matching network, because the center frequency of the
matching network can vary due to the environmental and
process variations. Furthermore, the signal frequency may
change within the range allowed in the protocol. The block
diagram of the tuning loop is shown in Fig. 4. To change the
center frequency a number of PMOS transistors are
connected in parallel to the input (refer to the inset on the top
right of the Fig. 4). V
ctrl
of each PMOS pair is connected to
one of the output bits of the up/down counter shown in
Fig. 5. Given that IN
1
and IN
2
are connected to RF inputs
their voltage level is low. Therefore, when the counter bit is
0, the equal capacitance seen from IN
1
and IN
2
is small (low
V
SG
) and the series resistance is large. When the counter bit
is 1 (i.e., V
DD
), the equivalent capacitance of the PMOS
structure is maximum (large V
SG
) while its resistance is
minimum. Note that series resistance with this capacitor is
not desirable because it lowers the Q and dissipates power.
In every clock cycle the counter turns on/off one of the
PMOS capacitors, and at the same time the supply voltage is
sampled. A Schmitt trigger comparator compares this sample
with the value of the supply voltage half a clock cycle later
and determines whether the change in the input capacitance
has resulted in an increase or decrease in the supply voltage
value. The result is a 0 or 1 signal named UP. UP = 1
means that the supply voltage has increased and UP = 0
means that the supply voltage has decreased. Based on this
knowledge, a finite state machine (FSM) decides whether the
counter should count up or down in the next clock cycle to
keep the output voltage rising, Fig. 6.
The designed counter has eight outputs, (Fig. 5). On every
falling edge of CLK, the counter turns one of the 0 output
bits to 1 if Up/Down control signal (the output of FSM) is
1, and it turns one of the 1 output bits to 0 if the control
signal is 0. Additional logic gates are used to make sure that
only those two flip flops whose values may change will see
the clock transitions, thus the counter avoids many
unnecessary changes in the internal nodes and its dynamic
power dissipation is significantly reduced. The dynamic
power consumption of the counter is almost independent of
the number of output bits and stays approximately the same if
more output bits are added.

Figure 3. (a) Dickson stage (b) two symmetrical stages connected to
different ends of the antenna (c) adding PMOS transistors to reduce reverse
current

Figure 4. The tuning loop



Figure 6. Finite State Machine
Table 1. Loop power consumption
V DD = 1 V DD = 0.4V
Counter 340nW 70nW
Schmitt
trigger
1W 260nW
Loop 1.36 W 340nW



Figure 5. Low-power Up/Down counter
4087
When the tag operation begins, the input network is not
tuned yet; therefore, the rectifier may not provide a large
voltage or current at its output. Thus the loop must be capable
of operating with a small supply voltage and with very low
power consumption. At this point the tuning loop turns on
while the rest of the chip is still off. The loop tunes the input
capacitance for the optimal output voltage. After a few
microseconds that the loop tunes the input capacitance, the
loop can be turned off by stopping the CLK signal and
turning off the bias current of the Schmitt trigger to save
power, meanwhile the counter keeps the optimal value of the
input capacitance. After the tuning, the rest of the chip can be
turned on. The loop can also remain functional while the rest
of the circuit is also working.
VI. Simulations and Results
The rectifier characteristic curves are shown in Fig. 7. The
output voltage of a four-stage rectifier is shown as a function
of input voltage amplitude for different load currents. Then a
50 antenna is connected to the chip (as shown in Fig. 4) via
two series matching inductors and the output of the rectifier is
connected to a 250k load resistor to model power
consumption of the chip. Fig. 8 shows the average output
voltage vs. frequency for three cases: (1) no-loop: the
matching network is fixed and no adaptive tuning is used (2)
loop on: the loop continuously tunes the input capacitance (3)
loop-off: the loop turns off after tuning to save power. As it
can be seen the loop keeps the output voltage high over a
wide frequency rang. Based on the simulations, the tuning
range of the tuning network is 860MHz to 960MHz. The
reason that the loop off graph is lower than the peak of no
loop graph is that the loop fluctuates around the optimum
input capacitance. So the loop is likely to be turned off when
the input capacitance is not optimum. This reduces the
average output voltage. The breakdown of the power
consumption of the loop is shown in Table. 1. As can be seen
the counter does not consume much power especially for low
supply voltages. Performance comparison with previous
works is provided in Table 2.

Figure 7 Rectifiers output voltage vs. input voltage amplitude for different
load currents
Figure 8 Output voltage vs. frequency for 10 W input power, RLoad=250k.
Reference

0
0.5
1
1.5
2
2.5
3
250 350 450 550 650 750 850
O
u
t
p
u
t

V
o
l
t
a
g
e

(
V
)
V in (mV)
10uA
7.5uA
5.5uA
3.25uA
1uA
0
0.2
0.4
0.6
0.8
1
1.2
1.4
840 860 880 900 920 940 960 980
O
u
t
p
u
t

v
o
l
t
a
g
e

(
V
)
Frequency (MHz)
250k loop on
250k loop off
250k no loop
Table 2. Comparison of different stages
[6] [7] [8] [3] This
work
Technology 0.35m 0.30 m 0.18 m
(zero-Vth
option)
0.18 m 0.13 m
Load 80 W 0.4 A,
1.5V
1

14 A,
0.974V
2.50 A,
0.4V
4 A,
1.25V
Efficiency,
input power
36.6%,
250 W
1.2% ,
40 W
33.69 % 16.7 %,
6 W
2

50%
2
,
10W
# of stages 2 6 10 2 4
1. 11% efficiency in -6dBm
2. Loop turned off
[1] EPC
TM
Radio-Frequency Identity Protocols Class-1 Generation-2 UHF RFID
Protocol for Communications at 860-960MHz Version 1.0.9
[2] Barnett, R.E., Jin Liu & Lazar, S. 2009, "A RF to DC Voltage Conversion
Model for Multi-Stage Rectifiers in UHF RFID Transponders", Solid-State
Circuits, IEEE Journal of, vol. 44; 44, no. 2, pp. 354-370.
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[7] Umeda, T., Yoshida, H., Sekine, S., Fujita, Y., Suzuki, T. & Otaka, S. 2006,
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ed.
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VII. Conclusion
In this, a high-Q matching circuit in conjunction with an
automatic tuning circuit is used in a RF power harvesting
system to amplify small input RF signals. A rectifier bridge
is also proposed which can rectify small RF signals while
preventing the reverse currents to improve efficiency. A very
low power tuning counter is also presented. The power
consumption of this counter is considerably reduced by
avoiding unnecessary internal transitions. In simulations,
power efficiency of more that 50% is achieved.
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