SPEAr320 Datasheet

SPEAr320
Embedded MPU with ARM926 core, optimized for factory automation and consumer applications
Features

ARM926EJ-S 333 MHz core High-performance 8-channel DMA Dynamic power-saving features Configurable peripheral functions on 102 shared I/Os. Memory: 32 KB ROM and 8 KB internal SRAM LPDDR-333/DDR2-666 external memory interface SDIO/MMC card interface Serial Flash memory interface (SMI) Flexible static memory controller (FSMC) up to 16-bit data bus width, supporting NAND Flash External memory interface (EMI) up to 16bit data bus width, supporting NOR Flash and FPGAs Security Cryptographic accelerator Connectivity 2 x USB 2.0 Host 1 x USB 2.0 Device 2 x fast Ethernet MII/SMII ports 2 x CAN interface 3 x SSP Synchronous serial port (SPI, Microwire or TI protocol) 2 x I2C 1 x fast IrDA interface 3 x UART interface 1 x standard parallel device port Peripherals supported TFT/STN LCD controller (resolution up to 1024 x 768 and up to 24 bpp) Touchscreen support Miscellaneous functions
LFBGA289 (15 x 15 x 1.7 mm)
Integrated real time clock, watchdog, and system controller 8-channel 10-bit ADC, 1 Msps 4 x PWM timers JPEG CODEC accelerator 6x 16-bit general purpose timers with programmable prescaler, 4 capture inputs Up to 102 GPIOs with interrupt capability
Applications
The SPEAr320 embedded MPU is configurable for a range of industrial and consumer applications such as:

Programmable logic controllers Factory automation Printers Device summary

Temp range, C -40 to 85 Package LFBGA289 (15x15 mm, pitch 0.8 mm) Packing
Table 1.
Order code
SPEAR320-2
Tray
December 2010
Doc ID 16755 Rev 4
1/76
www.st.com 1
Contents
SPEAr320
Contents
1 2 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 CPU ARM 926EJ-S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Embedded memory units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Mobile DDR/DDR2 memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Serial memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 External memory interface (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SDIO controller/MMC card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 14 Multichannel DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SMII/MII Ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MII Ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 CAN controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 USB2 host controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 USB2 device controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 CLCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Parallel port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Synchronous serial ports (SSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.19.1 3.19.2 3.19.3 UART0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 UART2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.20 3.21 3.22 3.23
JPEG CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Cryptographic co-processor (C3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8-channel ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 System controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.23.1 Power saving system mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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Contents Clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.24 3.25 3.26 3.27 3.28
Vectored interrupt controller (VIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 General purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PWM timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1 4.2 4.3 Required external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Shared I/O pins (PL_GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 PL_GPIO pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Configuration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Boot pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.4
PL_GPIO pin sharing for debug modes . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5 6
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Maximum power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Overshoot and undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3V I/O characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 LPDDR and DDR2 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Removing power supplies for power saving . . . . . . . . . . . . . . . . . . . . . . . 47 Power on reset (MRESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.1 DDR2 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.1.1 DDR2 read cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Doc ID 16755 Rev 4
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Contents 7.1.2 7.1.3
SPEAr320 DDR2 write cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 DDR2 command timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.2
CLCD timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.2.1 7.2.2
2
CLCD timing characteristics direct clock . . . . . . . . . . . . . . . . . . . . . . . . 52 CLCD timing characteristics divided clock . . . . . . . . . . . . . . . . . . . . . . . 53
7.3 7.4
I C timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 FSMC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

7.4.1 7.4.2 8-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 16-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.5
Ether MAC 10/100 Mbps timing characteristics . . . . . . . . . . . . . . . . . . . . 60

7.5.1 7.5.2 7.5.3 MII transmit timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 MII receive timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 MDIO timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.6 7.7
SMI - Serial memory interface timing characteristics . . . . . . . . . . . . . . . . 64 SSP timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

7.7.1 7.7.2 SPI master mode timings (clock phase = 0) . . . . . . . . . . . . . . . . . . . . . 68 SPI master mode timings (clock phase = 1) . . . . . . . . . . . . . . . . . . . . . 69
7.8 7.9
UART timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
8 9
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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Doc ID 16755 Rev 4
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List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Master clock, RTC, Reset and 3.3 V comparator pin descriptions . . . . . . . . . . . . . . . . . . . 25 Power supply pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Debug pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Serial memory interface (SMI) pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 USB pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 ADC pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DDR pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PL_GPIO pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PL_GPIO multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table shading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Ball sharing during debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 SPEAr320 main memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Reconfigurable array subsystem memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Maximum power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Overshoot and undershoot specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Low voltage TTL DC input specification (3 V< VDD <3.6 V) . . . . . . . . . . . . . . . . . . . . . . . . 46 Low voltage TTL DC output specification (3 V< VDD <3.6 V) . . . . . . . . . . . . . . . . . . . . . . . 46 Pull-up and pull-down characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 On die termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 DDR2 Read cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 DDR2 Write cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 DDR2 Command timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 CLCD timings with CLCP direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 CLCD timings with CLCP divided . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Output delays for I2C signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Time characteristics for I2C in high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Time characteristics for I2C in fast speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Time characteristics for I2C in standard speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Time characteristics for 8-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Time characteristics for 16-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . 60 MII TX timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 MDC/MDIO timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 SMI_DATAIN timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SMI_DATAOUT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 SMI_CSn fall timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 SMI_CSn rise timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Timing requirements for SMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Timing requirements for SSP (all modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Timing requirements for SPI master mode (clock phase = 0). . . . . . . . . . . . . . . . . . . . . . . 68 Switching characteristics over recommended operating conditions for SPI master mode (clock phase = 0)68 Timing requirements for SPI master mode (clock phase = 1). . . . . . . . . . . . . . . . . . . . . . . 69
Doc ID 16755 Rev 4
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List of tables Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54.
SPEAr320
Switching characteristics over recommended operating conditions for SPI master mode (clock phase =1 )69 UART transmit timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 UART receive timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 LFBGA289 (15 x 15 x 1.7 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Thermal resistance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical system architecture using SPEAr320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Typical SMII system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Hierarchical multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 DDR2 Read cycle waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 DDR2 Read cycle path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 DDR2 Write cycle waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 DDR2 Write cycle path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 DDR2 Command waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 DDR2 Command path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 CLCD waveform with CLCP direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 CLCD block diagram with CLCP direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 CLCD waveform with CLCP divided . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 CLCD block diagram with CLCP divided . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 I2C output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 I2C input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Output signal waveforms for I2C signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 RC delay circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Output pads for 8-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Input pads for 8-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Output command signal waveforms for 8-bit NAND Flash configuration . . . . . . . . . . . . . . 57 Output address signal waveforms for 8-bit NAND Flash configuration. . . . . . . . . . . . . . . . 58 In/out data address signal waveforms for 8-bit NAND Flash configuration. . . . . . . . . . . . . 58 Output pads for 16-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Input pads for 16-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Output command signal waveforms 16-bit NAND Flash configuration . . . . . . . . . . . . . . . . 59 Output address signal waveforms 16-bit NAND Flash configuration . . . . . . . . . . . . . . . . . 60 In/out data signal waveforms for 16-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . 60 MII TX waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Block diagram of MII TX pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 MII RX waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Block diagram of MII RX pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 MDC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Paths from MDC/MDIO pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 SMI_DATAIN data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SMI_DATAOUT/SMI_CSn data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SMI_DATAOUT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 SMICSn fall timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 SMI_CSn rise timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 SSP_CLK timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 SPI master mode external timing (clock phase = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 SPI master mode external timing (clock phase = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 UART transmit and receive timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 LFBGA289 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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Description
SPEAr320
Description
The SPEAr320 is a member of the SPEAr family of embedded MPUs, optimized for industrial automation and consumer applications. It is based on the powerful ARM926EJ-S processor (up to 333 MHz), widely used in applications where high computation performance is required. In addition, SPEAr320 has an MMU that allows virtual memory management -- making the system compliant with Linux operating system. It also offers 16 KB of data cache, 16 KB of instruction cache, JTAG and ETM (Embedded Trace Macrocell) for debug operations. A full set of peripherals allows the system to be used in many applications, some typical applications being factory automation, printer and consumer applications. Figure 1. Functional block diagram
EMI NOR Flash/ FPGA interface FSMC NAND Flash interface Mobile DDR/DDR2 memory controller MultiChannel DMA controller IrDA USB Device 2.0 +Phy Serial Flash interface C3 Crypto accelerator SDIO/MMC card interface JPEG CODEC accelerator 4x PWM timer
IrDA
Up to 102 GPIOs
2x Ethernet 10/100 (SMII/MII interface)
2x CAN
3x UART
LCD controller 1024*768
6x general purpose timer USB Host 2.0
Phy
Hub Phy
32 KBytes BootRom
ADC 8 KBytes SRAM 3x SSP
Interrupt controller
System controller
MMU ICache
2x I2C master/slave ARM926EJ-S @333 MHz Std parallel port
Watchdog
RTC
PLLs
DCache
JTAG/trace
= Functions with shared I/Os depending on the device configuration.
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SPEAr320
Main features
Main features
ARM926EJ-S 32-bit RISC CPU, up to 333 MHz 16 Kbytes of instruction cache, 16 Kbytes of data cache 3 instruction sets: 32-bit for high performance, 16-bit (Thumb) for efficient code density, byte Java mode (Jazelle) for direct execution of Java code. Tightly Coupled Memory AMBA bus interface
32-KByte on-chip BootRom 8-KByte on-chip SRAM External DRAM memory interface: 8/16-bit (mobile DDR@166 MHz) 8/16-bit (DDR2@333 MHz)
Serial memory interface SDIO interface supporting SPI, SD1, SFD4 and SD8 modes 8/16-bits NAND Flash controller (FSMC) External memory interface (EMI) for connecting NOR Flash or FPGAs Boot capability from NAND Flash, serial/parallel NOR Flash Boot and field upgrade capability from USB High performance 8-channel DMA controller 2x Ethernet MAC 10/100 Mbps with MII/SMII PHY interface Two USB2.0 host (high-full-low speed) with integrated PHY transceiver One USB2.0 device (high-full-low speed) with integrated PHY transceiver 2x CAN 2.0 interfaces Up to 102 GPIOs with interrupt capability Up to 4 PWM outputs 3x SSP master/slave (supporting Motorola, Texas instruments, National semiconductor protocols) up to 41.5 Mbps Standard Parallel Port (SPP device implementation) 2x I2C master/slave interface (slow- fast-high speed, up to 1.2Mb/s) 3x UART: UART0 (up to 3 Mbps) with hardware flow control and modem interface, UART1 (up to 7 Mbps) with hardware flow control (in some operating modes) and UART2 (up to 7 Mbps) with software flow control ADC 10-bit, 1 Msps 8 inputs/1-bit DAC JPEG CODEC accelerator 1 clock/pixel Color LCD interface (up to 1024X768, 24-bits CLCD controller, TFT and STN panels) Touchscreen support Crypto accelerator (DES/3DES/AES/SHA1) Advanced power saving features Normal, Slow, Doze and Sleep modes CPU clock with software-programmable frequency Enhanced dynamic power-domain management
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Main features

SPEAr320 Clock gating functionality Low frequency operating mode Automatic power saving controlled from application activity demands
Vectored interrupt controller System and peripheral controller 3 pairs of 16-bit general purpose timers with programmable prescaler RTC with separate power supply allowing battery connection Watchdog timer Miscellaneous registers array for embedded MPU configuration
Programmable PLL for CPU and system clocks JTAG IEEE 1149.1 boundary scan ETM functionality multiplexed on primary pins Supply voltages 1.2 V core, 1.8 V/2.5 V DDR, 2.5 V PLLs, 1.5 V RTC and 3.3 V I/Os Operating temperature: - 40 to 85 C LFBGA289 (15 x 15 mm, pitch 0.8 mm)
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SPEAr320
Architecture overview
The SPEAr320 internal architecture is based on several shared subsystem logic blocks interconnected through a multilayer interconnection matrix. The switch matrix structure allows different subsystem dataflow to be executed in parallel improving the core platform efficiency. High performance master agents are directly interconnected with the memory controller reducing the memory access latency. The overall memory bandwidth assigned to each master port can be programmed and optimized through an internal efficient weighted roundrobin arbitration mechanism.
Figure 2.
Typical system architecture using SPEAr320

Internet Access Phy SPEAr320 USB2.0 PHY device 2x Ethernet USB2.0 PHY Host
TouchScreen
NAND Flash NOR Flash FPGA Flash EEPROM DDR2 Mobile DDR MMC SD-Card SDIO
FSMC EMI
Parallel port
ADC
LCD controller
SMI DDR memory controller
ARM 926EJ-S up to 333 MHz 8-channel DMA 6 timers / WD
8 KB embed. SRAM 32 KB embed. ROM MMU Interrupt/syst controller
USB2.0 PHY Host
SDIO/MMC JTAG
JPEG CODEC accelerator C3 Crypto accelerator
IrdDA
Debug, trace ETM9 RTC Clock, Reset GPIO
CAN 2x CAN 4x PWM 3x UART 3x SSP 2x I2C Controller Automation Network
24 MHz 32 kHz
3.1
CPU ARM 926EJ-S

The core of the SPEAr320 is an ARM926EJ-S reduced instruction set computer (RISC) processor. It supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to trade off between high performance and high code density and includes features for efficient execution of Java byte codes.
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SPEAr320
The ARM CPU and is clocked at a frequency up to 333 MHz. It has a 16-Kbyte instruction cache, a 16-Kbyte data cache, and features a memory management unit (MMU) which makes it fully compliant with Linux and VxWorks operating systems. It also includes an embedded trace module (ETM Medium+) for real-time CPU activity tracing and debugging. It supports 4-bit and 8-bit normal trace mode and 4-bit demultiplexed trace mode, with normal or half-rate clock.
3.2
Embedded memory units

32 Kbytes of BootROM 8 Kbytes of SRAM
3.3
Mobile DDR/DDR2 memory controller

SPEAr320 integrates a high performance multi-channel memory controller able to support low power Mobile DDR and DDR2 double data rate memory devices. The multi-port architecture ensures memory is shared efficiently among different high-bandwidth client modules. It has 6 internal ports. One of them is reserved for register access during the controller initialization while the other five are used to access the external memory. It also includes the physical layer (PHY) and DLLs for fine tuning the timing parameters to maximize the data valid windows at different frequencies.
3.4
Serial memory interface

SPEAr320 provides a serial memory interface (SMI), acting as an AHB slave interface (32-, 16- or 8-bit) to SPI-compatible off-chip memories. These serial memories can be used either as data storage or for code execution. Main features:
Supports the following SPI-compatible Flash and EEPROM devices: STMicroelectronics M25Pxxx, M45Pxxx STMicroelectronics M95xxx, except M95040, M95020 and M95010 ATMEL AT25Fxx YMC Y25Fxx SST SST25LFxx
Acts always as a SPI master and up to 2 SPI slave memory devices are supported (with separate chip select signals), with up to 16 MB address space each SMI clock signal (SMICLK) is generated by SMI (and input to all slaves) using a clock provided by the AHB bus SMICLK can be up to 50 MHz in fast read mode (or 20 MHz in normal mode). It can be controlled by a programmable 7-bit prescaler allowing up to 127 different clock frequencies.
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SPEAr320
3.5
External memory interface (EMI)

The EMI Controller provides a simple external memory interface that can be used for example to connect to NOR Flash memory or FPGA devices. Main features:

EMI bus master 16 and 8-bit transfers Can access 4 different peripherals using CS#, one at a time. Supports single asynchronous transfers. Supports peripherals which use Byte Lane procedure
3.6
SDIO controller/MMC card interface

The SDIO host controller has an AMBA compatible interface and conforms to the SD host Controller Standard Specification Version 2.0. It handles SDIO/SD Protocol at transmission level, packing data, adding cyclic redundancy check (CRC), start/end bit and checking for transaction format correctness. The host controller provides programmed IO and DMA data transfer method. Main features:
Meets the following specifications: SD Host Controller Standard Specification Version 2.0 SDIO card specification version 2.0 SD Memory Card Specification Draft version 2.0 SD Memory Card Security Specification version 1.01 MMC Specification version 3.31 and 4.2
Supports both DMA and Non-DMA mode of operation Supports MMC Plus and MMC Mobile Card Detection (Insertion / Removal) Card password protection Host clock rate variable between 0 and 48 MHz Supports 1 bit, 4 bit and 8 bit SD modes and SPI mode Supports Multi Media Card Interrupt mode Allows card to interrupt host in 1 bit, 4 bit, 8 bit SD modes and SPI mode. Up to 100 Mbits per second data rate using 4 parallel data lines (SD4 bit mode) Up to 416 Mbits per second data rate using 8 bit parallel data lines (SD8 bit mode) Cyclic Redundancy Check CRC7 for command and CRC16 for data integrity Designed to work with I/O cards, Read-only cards and Read/Write cards Error Correction Code (ECC) support for MMC4.2 cards Supports Read wait Control, Suspend/Resume operation Supports FIFO Overrun and Underrun condition by stopping SD clock Conforms to AMBA specification AHB (2.0)
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SPEAr320
3.7
Flexible static memory controller (FSMC)

SPEAr320 provides a Flexible Static Memory Controller (FSMC) which interfaces the AHB bus to external parallel NAND Flash memories.

Provides an interface between AHB system bus and external NAND Flash memory devices. 8/16-bit wide data path FSMC performs only one access at a time and only one external device is accessed Supports little-endian and big-endian memory architectures AHB burst transfer handling to reduce access time to external devices Supplies an independent configuration for each memory bank Programmable timings to support a wide range of devices Programmable wait states (up to 31) Programmable bus turnaround cycles (up to 15) Programmable output enable and write enable delays (up to 15)
Independent chip select control for each memory bank Shares the address bus and the data bus with all the external peripherals Only chips selects are unique for each peripheral External asynchronous wait control Boot memory bank configurable at reset using external control pins
3.8
Multichannel DMA controller

Within its basic subsystem, SPEAr320 provides a DMA controller (DMAC) able to service up to 8 independent DMA channels for serial data transfers between single source and destination (i.e., memory-to-memory, memory-to-peripheral, peripheral to- memory, and peripheral-to-peripheral). Each DMA channel can support a unidirectional transfer, with internal four-word FIFO per channel.
3.9
SMII/MII Ethernet controller

SPEAr320 features two Ethernet MACs, one supporting SMII and one supporting SMII and MII. Each MAC channel has dedicated TX/RX signals while synchronization and clock signals are common for PHY connection. Figure 3 shows the typical SMII configuration:
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SPEAr320 Figure 3. Typical SMII system

2 Tx 2 Rx 2 MAC ports SYNC 2x PHY
Clock
Each Ethernet port provides the following features:

Compatible with IEEE Standard 802.3 10 and 100 Mbit/s operation Full and half duplex operation Statistics counter registers for RMON/MIB Interrupt generation to signal receive and transmit completion Automatic pad and CRC generation on transmitted frames Automatic discard of frames received with errors Address checking logic supports up to four specific 48-bit addresses Supports promiscuous mode where all valid received frames are copied to memory Hash matching of unicast and multicast destination addresses External address matching of received frames Physical layer management through MDIO interface Supports serial network interface operation Half duplex flow control by forcing collisions on incoming frames Full duplex flow control with recognition of incoming pause frames and hardware generation of transmitted pause frames Support for 802.1Q VLAN tagging with recognition of incoming VLAN and priority tagged frames Multiple buffers per receive and transmit frame Wake on LAN support Jumbo frames of up to 10240 bytes supported Configurable Endianess for the DMA Interface (AHB Master)
3.10
MII Ethernet controller

SPEAr320 provides an Ethernet MAC 10/100 Universal (commonly referred to as MACUNIV), enabling to transmit and receive data over Ethernet in compliance with the IEEE 802.3-2002 standard.
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Architecture overview Main features:

SPEAr320
Supports the default Media Independent Interface (MII) defined in the IEEE 802.3 specifications. Supports 10/100 Mbps data transfer rates Local FIFO available (4 Kbyte RX, 2 Kbyte TX) Supports both half-duplex and full-duplex operation. In half-duplex operation, CSMA/CD protocol is provided Programmable frame length to support both standard and jumbo Ethernet frames with size up to 16 Kbytes 32/64/128-bit data transfer interface on system-side. A variety of flexible address filtering modes are supported A set of control and status registers (CSRs) to control GMAC core operation Native DMA with single-channel transmit and receive engines, providing 32/64/128-bit data transfers DMA implements dual-buffer (ring) or linked-list (chained) descriptor chaining An AHB slave acting as programming interface to access all CSRs, for both DMA and GMAC core subsystems An AHB master for data transfer to system memory 32-bit AHB master bus width, supporting 32, 64, and 128-bit wide data transactions It supports both big-endian and little-endian.
3.11
CAN controller
SPEAr320 has two CAN controllers for interfacing CAN 2.0 networks. Main features:

Supports CAN protocol version 2.0 part A and B Bit rates up to 1 MBit/s 16 message objects(136 X 16 message RAM) Each message object has its own identifier mask Maskable interrupt Programmable loop-back mode for self-test operation Disabled automatic retransmission mode for time triggered CAN applications
3.12
USB2 host controller

SPEAr320 has two fully independent USB 2.0 hosts. Each consists of 5 major blocks:

EHCI capable of managing high-speed transfers (HS mode, 480 Mbps) OHCI that manages the full and the low speed transfers (12 and 1.5 Mbps) Local 2-Kbyte FIFO Local DMA Integrated USB2 transceiver (PHY)
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SPEAr320
Architecture overview Both hosts can manage an external power switch, providing a control line to enable or disable the power, and an input line to sense any over-current condition detected by the external switch. One host controller at time can perform high speed transfer.
3.13
USB2 device controller

Main features:

Supports the 480 Mbps high-speed mode (HS) for USB 2.0, as well as the 12 Mbps full-speed (FS) and the low-speed (LS modes) for USB 1.1 Supports 16 physical endpoints, configurable as different logical endpoints Integrated USB transceiver (PHY) Local 4 Kbyte FIFO shared among all the endpoints DMA mode and slave-only mode are supported In DMA mode, the UDC supports descriptor-based memory structures in application memory In both modes, an AHB slave is provided by UDC-AHB, acting as programming interface to access to memory-mapped control and status registers (CSRs) An AHB master for data transfer to system memory is provided, supporting 8, 16, and 32-bit wide data transactions on the AHB bus A USB plug (UPD) detects the connection of a cable.
3.14
CLCD controller
SPEAr320 has a color liquid crystal display controller (CLCDC) that provides all the necessary control signals to interface directly to a variety of color and monochrome LCD panels. Main features:

Resolution programmable up to 1024 x 768 16-bpp true-color non-palletized, for color STN and TFT 24-bpp true-color non-palletized, for color TFT Supports single and dual panel mono super twisted nematic (STN) displays with 4 or 8bit interfaces Supports single and dual-panel color and monochrome STN displays Supports thin film transistor (TFT) color displays 15 gray-level mono, 3375 color STN, and 32 K color TFT support 1, 2, or 4 bits per pixel (bpp) palletized displays for mono STN 1, 2, 4 or 8-bpp palletized color displays for color STN and TFT Programmable timing for different display panels 256 entry, 16-bit palette RAM, arranged as a 128 x 32-bit RAM physically frame, line and pixel clock signals AC bias signal for STN and data enable signal for TFT panels patented gray scale algorithm Supports little and big-endian
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SPEAr320
3.15
GPIOs
A maximum of 102 GPIOs (PL_GPIOs) are available when part of the embedded or customization IPs are not needed (see Section 4.3: Shared I/O pins (PL_GPIOs)). Within its basic subsystem, SPEAr320 provides a base General Purpose Input/Output (GPIO) block (basGPIO). The base GPIO block provides 6 programmable inputs or outputs. Each input/output can be controlled in two distinct modes:

Software mode, through an APB interface. Hardware mode, through a hardware control interface. Six individually programmable input/output pins (default to input at reset) An APB slave acting as control interface in "software mode" Programmable interrupt generation capability on any number of pins. Hardware control capability of GPIO lines for different system configurations. Bit masking in both read and write operation through address lines.
Main features of the base GPIO block are:

Other GPIO blocks are present in the reconfigurable array subsystem.
3.16
Parallel port
Main features:

Slave mode device interface for standard parallel port host Supports unidirectional 8-bit data transfer from host to slave Supports 9th bit for parity/data/command etc. Maskable interrupts for data, device reset, auto line feed APB input clock frequency required is 83 MHz for acknowledgement timings Conforms to AMBA-APB specifications
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3.17
Synchronous serial ports (SSP)

SPEAr320 provides three synchronous serial ports (SSP) that offer a master or slave interface to enable synchronous serial communication with slave or master peripherals Main features:

Master or slave operation. Programmable clock bit rate and prescale. Separate transmit and receive first-in, first-out memory buffers, 16-bits wide, 8 locations deep. Programmable choice of interface operation: SPI (Motorola) Microwire (National Semiconductor) TI synchronous serial.
Programmable data frame size from 4 to 16-bits. Independent masking of transmit FIFO, receive FIFO, and receive overrun interrupts. Internal loopback test mode available. DMA interface
3.18
I2C
The SPEAr320 has 2 I2C interfaces: Main features:

Compliance to the I2C bus specification (Philips) Supports three modes: Standard (100 kbps) Fast (400 kbps) High-speed (3.4 Mbps)
Clock synchronization Master and slave mode configuration possible Multi-master mode (bus arbitration) 7-bit or 10-bit addressing 7-bit or 10-bit combined format transfers Slave bulk transfer mode Ignores CBUS addresses (predessor to I2C that used to share the I2C bus) Transmit and receive buffers Interrupt or polled-mode operation handles bit and byte waiting at all bus speeds Digital filter for the received SDA and SCL lines Handles component parameters for configurable software driver support Supports APB data bus widths of 8, 16 and 32-bits.
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3.19
UARTs
The SPEAr320 has 3 UARTs with different capabilities.
3.19.1
UART0
Main features:

Separate 16 x 8 (16 locations deep x 8-bit wide) transmit and 16 x 12 receive FIFOs to reduce CPU interrupts Speed up to 3 Mbps Hardware and/or software flow control Modem interface signals
3.19.2
UART1
Main features:

Separate 16 x 8 (16 location deep x 8-bit wide) transmit and 16x12 receive FIFOs to reduce CPU interrupts Speed up to 7 Mbps Hardware flow control (in Small Printers and Automation Expansion modes only) and/or software flow control
3.19.3
UART2
Main features:

Separate 16 x 8 (16 location deep x 8-bit wide) transmit and 16x12 receive FIFOs to reduce CPU interrupts Speed up to 7 Mbps Software flow control
3.20
JPEG CODEC
SPEAr320 provides a JPEG CODEC with header processing (JPGC), able to decode (or encode) image data contained in the SPEAr320 RAM, from the JPEG (or MCU) format to the MCU (or JPEG) format.
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SPEAr320 Main features:

Compliance with the baseline JPEG standard (ISO/IEC 10918-1) Single-clock per pixel encoding/decoding Support for up to four channels of component color 8-bit/channel pixel depths Programmable quantization tables (up to four) Programmable Huffman tables (two AC and two DC) Programmable minimum coded unit (MCU) Configurable JPEG header processing Support for restart marker insertion Use of two DMA channels and of two 8 x 32-bits FIFO's (local to the JPEG) for efficient transferring and buffering of encoded/decoded data from/to the CODEC core.
3.21
Cryptographic co-processor (C3)

SPEAr320 has an embedded Channel Control Coprocessor (C3). C3 is a high-performance instruction driven DMA based co-processor. It executes instruction flows generated by the host processor. After it has been set-up by the host it runs in a completely autonomous way (DMA data in, data processing, DMA data out), until the completion of all the requested operations. C3 has been used to accelerate the processing of cryptographic, security and network security applications. It can be used for other types of data intensive applications as well. Hardware cryptographic co-processor features are listed below:
Supported cryptographic algorithms: Advanced encryption standard (AES) cipher in ECB, CBC, CTR modes. Data encryption standard (DES) cipher in ECB and CBC modes. SHA-1, HMAC-SHA-1, MD5, HMAC-MD5 digests.
Instruction driven DMA based programmable engine. AHB master port for data access from/to system memory. AHB slave port for co-processor register accesses and initial engine-setup. The co-processor is fully autonomous (DMA input reading, cryptographic operation execution, DMA output writing) after being set up by the host processor. The co-processor executes programs written by the host in memory, it can execute an unlimited list of programs. The co-processor supports hardware chaining of cryptographic blocks for optimized execution of data-flow requiring multiple algorithms processing over the same set of data (for example encryption + hashing on the fly).
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SPEAr320
3.22
8-channel ADC
Main features:

Successive approximation conversion method 10-bit resolution @1 Msps Hardware supporting up to 13.5 bits resolution at 8 ksps by oversampling and accumulation Eight analog input (AIN) channels, ranging from 0 to 2.5 V INL 1 LSB, DNL 1 LSB Programmable conversion speed, (min. conversion time is 1 s) Programmable averaging of results from 1 (No averaging) up to 128 Programmable auto scan for all the eight channels.
3.23
System controller
The System Controller provides an interface for controlling the operation of the overall system. Main features:

Power saving system mode control Crystal oscillator and PLL control Configuration of system response to interrupts Reset status capture and soft reset generation Watchdog and timer module clock enable
3.23.1
Power saving system mode control

Using three mode control bits, the system controller switch the SPEAr320 to any one of four different modes: DOZE, SLEEP, SLOW and NORMAL.
SLEEP mode: In this mode the system clocks, HCLK and CLK, are disabled and the System Controller clock SCLK is driven by a low speed oscillator (nominally 32768 Hz). When either a FIQ or an IRQ interrupt is generated (through the VIC) the system enters DOZE mode. Additionally, the operating mode setting in the system control register automatically changes from SLEEP to DOZE. DOZE mode: In this mode the system clocks, HCLK and CLK, and the System Controller clock SCLK are driven by a low speed oscillator. The System Controller moves into SLEEP mode from DOZE mode only when none of the mode control bits are set and the processor is in Wait-for-interrupt state. If SLOW mode or NORMAL mode is required the system moves into the XTAL control transition state to initialize the crystal oscillator. SLOW mode: During this mode, both the system clocks and the System Controller clock are driven by the crystal oscillator. If NORMAL mode is selected, the system goes into the "PLL control" transition state. If neither the SLOW nor the NORMAL mode control bits are set, the system goes into the "Switch from XTAL" transition state. NORMAL mode: In NORMAL mode, both the system clocks and the System Controller clock are driven by the PLL output. If the NORMAL mode control bit is not set, then the system goes into the "Switch from PLL" transition state.
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SPEAr320
3.23.2
Clock and reset system

The clock system is a fully programmable block that generates all the clocks necessary to the chip. The default operating clock frequencies are:

Clock @ 333 MHz for the CPU. Clock @ 166 MHz for AHB bus and AHB peripherals. Clock @ 83 MHz for, APB bus and APB peripherals. Clock @ 333 MHz for DDR memory interface.
The default values give the maximum allowed clock frequencies. The clock frequencies are fully programmable through dedicated registers. The clock system consists of 2 main parts: a multi clock generator block and two internal PLLs. The multi clock generator block, takes a reference signal (which is usually delivered by the PLL), generates all clocks for the IPs of SPEAr320 according to dedicated programmable registers. Each PLL uses an oscillator input of 24 MHz to generate a clock signal at a frequency corresponding at the highest of the group. This is the reference signal used by the multi clock generator block to obtain all the other requested clocks for the group. Its main feature is electromagnetic interference reduction capability. The user can set up the PLL in order to modulate the VCO with a triangular wave. The resulting signal has a spectrum (and power) spread over a small programmable range of frequencies centered on F0 (the VCO frequency), obtaining minimum electromagnetic emissions. This method replaces all the other traditional methods of EMI reduction, such as filtering, ferrite beads, chokes, adding power layers and ground planes to PCBs, metal shielding and so on. This gives the customer appreciable cost savings. In sleep mode the SPEAr320 runs with the PLL disabled so the available frequency is 24 MHz or a sub-multiple (/2, /4, /8).
3.24
Vectored interrupt controller (VIC)

The VIC allows the OS interrupt handler to quickly dispatch interrupt service routines in response to peripheral interrupts. There are 32 interrupt lines and the VIC uses a separate bit position for each interrupt source. Software controls each request line to generate software interrupts.
3.25
General purpose timers

SPEAr320 provides 6 general purpose timers (GPTs) acting as APB slaves. Each GPT consists of 2 channels, each one made up of a programmable 16-bit counter and a dedicated 8-bit timer clock prescaler. The programmable 8-bit prescaler performs a clock division by 1 up to 256, and different input frequencies can be chosen through configuration registers (a frequency range from 3.96 Hz to 48 MHz can be synthesized).
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Architecture overview Two different modes of operation are available :

SPEAr320
Auto-reload mode, an interrupt source is activated, the counter is automatically cleared and then it restarts incrementing. Single-shot mode, an interrupt source is activated, the counter is stopped and the GPT is disabled.
3.26
PWM timers
SPEAr320 provides 4 PWM timers. Main features:

Prescaler to define the input clock frequency to each timer Programmable duty cycle from 0% to 100% Programmable pulse length APB slave interface for register programming
3.27
Watchdog timer
The ARM watchdog module consists of a 32-bit down counter with a programmable timeout interval that has the capability to generate an interrupt and a reset signal on timing out. The watchdog module is intended to be used to apply a reset to a system in the event of a software failure.
3.28
RTC oscillator
The RTC provides a 1-second resolution clock. This keeps time when the system is inactive and can be used to wake the system up when a programmed alarm time is reached. It has a clock trimming feature to compensate for the accuracy of the 32.768 kHz crystal and a secured time update. Main features:

Time-of-day clock in 24 hour mode Calendar Alarm capability Isolation mode, allowing RTC to work even if power is not supplied to the rest of the device.
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SPEAr320
Pin description
Pin description
The following tables describe the pinout of the SPEAr320 listed by functional block. List of abbreviations: PU = Pull Up PD = Pull Down
4.1
Required external components

1. 2. 3. DDR_COMP_1V8: place an external 121 kresistor between ball P4 and ball R4 USB_TX_RTUNE: connect an external 43.2 k pull-down resistor to ball K5 DIGITAL_REXT: place an external 121 k resistor between ball G4 and ball F4.
4.2
Dedicated pins
Table 2.
Group
Master clock, RTC, Reset and 3.3 V comparator pin descriptions

Signal name MCLK_XI Ball P1 P2 E2 E1 Direction Input Output Input Output Function 24 MHz (typical) crystal in 24 MHz (typical) crystal out 32 kHz crystal in 32 kHz crystal out Pin type
Master Clock MCLK_XO RTC_XI RTC RTC_XO
Oscillator 2.5 V capable
Oscillator 1V5 capable TTL Schmitt trigger input buffer, 3.3 V tolerant, PU Analog, 3.3 V capable Power
Reset
MRESET
M17
Input
Main Reset
DIGITAL_REXT 3.3 V Comp. DIGITAL_GNDBG COMP
G4 F4
Output Power
Configuration Power
Table 3.
Group
Power supply pin description

Signal name Ball G6 G7 G8 G9 G10 G11 H6 H7 H8 H9 H10 H11 J6 J7 J8 J9 J10 J11 K6 K7 K8 K9 K10 K11 L6 L7 L8 L9 L10 M8 M9 M10 L5 Value
DIGITAL GROUND
GND
0V
USB_HOST1_HOST0_DEVICE_DVSS
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Pin description Table 3.

Group
SPEAr320 Power supply pin description (continued)

Signal name RTC_GND DITH_PLL_VSS_ANA USB_HOST1_VSSA USB_HOST0_VSSA Ball F2 G1 J2 L1 L3 0V USB_DEVICE_VSSA DITH_VSS2V5 MCLK_GND MCLK_GNDSUB ADC_AGND I/O CORE DIGITAL_VDDE3V3 VDD USB_HOST0_VDD2V5 USB_HOST0_VDD3V3 USB_HOST1_VDD2V5 USB_HOST1_VDD3V3 USB_DEVICE_VDD2V5 USB_DEVICE_VDD3V3 USB_HOST1_HOST0_DEVICE_DVDD1V2 N2 N4 P3 R3 N12 F5 F6 F7 F10 F11 F12 G5 J12 K12 L12 M12 F8 F9 G12 H5 H12 J5 L11 M6 M7 M11 L2 K4 K3 J1 N1 N3 M3 R1 R2 G2 M4 M5 N5 N6 N7 N8 N9 N10 N11 N13 F1 3.3 V 1.2 V 2.5 V 3.3 V 2.5 V 3.3 V 2.5 V 3.3 V 1.2 V 1.2 V 2.5 V 2.5 V 2.5 V 1.8 V 2.5 V 1.5 V Value
ANALOG GROUND
USB_COMMON_VSSAC
USB HOST0 PHY USB HOST1 PHY USB DEVICE PHY OSCI (master clock) PLL1 PLL2 DDR I/O ADC OSCI RTC
MCLK_VDD MCLK_VDD2V5 DITH_PLL_VDD_ANA DITH_VDD_2V5 DDR_VDDE1V8 ADC_AVDD RTC_VDD1V5
Note:
All the VDD 2V5 power supplies are analog VDD.
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SPEAr320 Table 4.
Group
Pin description Debug pin descriptions

Signal name TEST_0 TEST_1 TEST_2 TEST_3 TEST_4 BOOT_SEL DEBUG nTRST L16 Input Test reset input Ball K16 K15 K14 K13 J15 J14 Reserved, to be fixed at high level TTL Schmitt trigger input buffer, 3.3 V tolerant, PU TTL output buffer, 3.3 V capable 4 mA TTL Schmitt trigger input buffer, 3.3 V tolerant, PU Input Test configuration ports. For functional mode, they have to be set to zero. Direction Function Pin type
TTL input buffer, 3.3 V tolerant, PD
TDO TCK TDI TMS
L15 L17 L14 L13
Output Input Input Input
Test data output Test clock Test data input Test mode select
Table 5.
Group
Serial memory interface (SMI) pin description

Signal name SMI_DATAIN SMI_DATAOUT Ball M13 M14 N17 M15 Output SMI_CS_1 M16 Direction Input Output I/O Function Serial Flash input data Serial Flash output data Serial Flash clock Serial Flash chip select TTL output buffer 3.3 V capable 4 mA Pin type TTL Input Buffer 3.3 V tolerant, PU
SMI SMI_CLK SMI_CS_0
Table 6.
Group
USB pin descriptions

Signal name USB_DEVICE_DP Ball M1 I/O M2 G3 Input Direction Function USB Device D+ USB Device DUSB Device VBUS Pin type Bidirectional analog buffer 5 V tolerant TTL input buffer 3.3 V tolerant, PD
USB DEV
USB_DEVICE_DM USB_DEVICE_VBUS
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Group
SPEAr320 USB pin descriptions (continued)

Signal name USB_HOST1_DP USB_HOST1_DM USB_HOST1_VBUS Ball H1 I/O H2 H3 Output USB HOST1 DUSBHOST1 VBUS USB Host1 Over-Current USB HOST0 D+ I/O USB_HOST0_DM USB_HOST0_VBUS K2 J3 Output USB HOST0 DUSB HOST0 VBUS USB Host0 Over-current Reference resistor Analog Test Output Direction Function USB HOST1 D+ Pin type Bidirectional analog buffer 5 V tolerant TTL output buffer 3.3 V capable, 4 mA TTL input buffer 3.3 V tolerant, PD Bidirectional analog buffer 5 V tolerant TTL output buffer 3.3 V capable, 4 mA TTL Input Buffer 3.3 V tolerant, PD Analog Analog
USB_HOST1_OVERCUR USB HOST USB_HOST0_DP
J4 K1
Input
USB_HOST0_OVERCUR USB_TXRTUNE USB USB_ANALOG_TEST
H4 K5 L4
Input Output Output
Table 7.
Group
ADC pin description

Signal name AIN_0 AIN_1 AIN_2 AIN_3 AIN_4 Ball N16 N15 P17 P16 P15 R17 R16 R15 N14 P14 ADC negative voltage reference ADC positive voltage reference Input ADC analog input channel Analog buffer 2.5 V tolerant Direction Function Pin type
ADC
AIN_5 AIN_6 AIN_7 ADC_VREFN ADC_VREFP
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SPEAr320 Table 8.
Group
Pin description DDR pin description

Signal name DDR_MEM_ADD_0 DDR_MEM_ADD_1 DDR_MEM_ADD_2 DDR_MEM_ADD_3 DDR_MEM_ADD_4 DDR_MEM_ADD_5 DDR_MEM_ADD_6 DDR_MEM_ADD_7 DDR_MEM_ADD_8 DDR_MEM_ADD_9 DDR_MEM_ADD_10 DDR_MEM_ADD_11 DDR_MEM_ADD_12 DDR_MEM_ADD_13 DDR DDR_MEM_ADD_14 DDR_MEM_BA_0 DDR_MEM_BA_1 DDR_MEM_BA_2 DDR_MEM_RAS DDR_MEM_CAS DDR_MEM_WE DDR_MEM_CLKEN DDR_MEM_CLKP DDR_MEM_CLKN DDR_MEM_CS_0 DDR_MEM_CS_1 DDR_MEM_ODT_0 DDR_MEM_ODT_1 Ball T2 T1 U1 U2 U3 U4 U5 T5 R5 P5 P6 R6 T6 U6 R7 P7 P8 R8 U8 T8 T7 U7 T9 Output U9 P9 Output R9 T3 I/O T4 On-Die Termination Enable lines Chip Select SSTL_2/SSTL_1 8 Differential clock Output Output Output Output Row Add. Strobe Col. Add. Strobe Write enable Clock enable Differential SSTL_2/SSTL_1 8 Output Bank select SSTL_2/SSTL_1 8 Output Address Line Direction Function Pin type
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Group
SPEAr320 DDR pin description (continued)

Signal name DDR_MEM_DQ_0 DDR_MEM_DQ_1 DDR_MEM_DQ_2 DDR_MEM_DQ_3 DDR_MEM_DQ_4 DDR_MEM_DQ_5 DDR_MEM_DQ_6 DDR_MEM_DQ_7 DDR_MEM__DQS_0 nDDR_MEM_DQS_0 DDR_MEM_DM_0 DDR_MEM_GATE_O PEN_0 DDR_MEM_DQ_8 DDR_MEM_DQ_9 DDR_MEM_DQ_10 Ball P11 R11 T11 U11 I/O T12 R12 P12 P13 U10 Output T10 U12 R10 T17 T16 U17 U16 I/O DDR_MEM_DQ_12 DDR_MEM_DQ_13 DDR_MEM_DQ_14 DDR_MEM_DQ_15 DDR_MEM_DQS_1 nDDR_MEM_DQS_1 DDR_MEM_DM_1 DDR_MEM_GATE_O PEN_1 DDR_MEM_VREF DDR_MEM_COMP2 V5_GNDBGCOMP DDR_MEM_COMP2 V5_REXT DDR2_EN U14 U13 T13 R13 U15 I/O T15 T14 I/O R14 P10 R4 P4 J13 Input Power Power Input Upper Gate Open Reference Voltage Return for Ext. Resistors Ext. Resistor Configuration Upper Data Strobe Upper Data Mask SSTL_2/SSTL_1 8 Differential SSTL_2/SSTL_1 8 Data Lines (Upper byte) SSTL_2/SSTL_1 8 Output I/O Lower Data Strobe Lower Data Mask Lower Gate Open Differential SSTL_2/SSTL_1 8 Data Lines (Lower byte) SSTL_2/SSTL_1 8 Direction Function Pin type
DDR
DDR_MEM_DQ_11
Analog Power Analog TTL Input Buffer 3.3 V Tolerant, PU
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SPEAr320
Pin description
4.3
Shared I/O pins (PL_GPIOs)

The 98 PL_GPIO and 4 PL_CLK pins have the following characteristics: Output buffer: TTL 3.3 V capable up to 10 mA Input buffer: TTL, 3.3 V tolerant, selectable internal pull up/pull down (PU/PD)
The PL_GPIOs can be configured in different modes. This allows SPEAr320 to be tailored for use in various applications like: Metering concentrators Large power supply controllers Small printers
4.3.1
PL_GPIO pin description

Table 9.
Group
PL_GPIO pin description

Signal name Ball Direction Function Pin type
PL_GPIO_97... PL_GPIO_0 PL_GPIOs PL_CLK1... PL_CLK4
(see the section Table 10)
I/O
General purpose I/O or multiplexed pins (see the (see the section introduction of Table 10) the Section 4.3 programmable here above) logic external clocks
4.3.2
Configuration modes
This section describes the main operating modes created by using a selection of the embedded IPs. The following modes can be selected by programming some control registers present in the reconfigurable array subsystem.

Mode 1: SMII automation networking mode Mode 2: MII automation networking mode Mode 3: Expanded automation mode Mode 4: Printer mode
Table 10: PL_GPIO multiplexing scheme on page 34 shows all the I/O functions available in each mode. Mode 1 is the default mode for SPEAr320.
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Pin description
SPEAr320
SMII automation networking mode

The SMII Automation networking operating mode mainly provides:

NAND Flash interface (8 bits, 4 chip selects) 2 CAN2.0 interfaces 2 SMII interfaces 3 UARTs 1 with hardware flow control (up to 3 Mbps) 2 with software flow control (baud rate up to 7 Mbps)
LCD interface (up to 1024x768, 24-bits LCD controller, TFT and STN panels) Touchscreen facilities 3 independent SSP Synchronous Serial Port (SPI, Microwire or TI protocol) ports GPIOs with interrupt capability SDIO interface supporting SPI, SD1, SD4 and SD8 mode
MII automation networking mode

The MII Automation networking operating mode mainly provides:

NAND Flash interface (8 bits, 4 chip selects) 2 CAN2.0 interfaces 2 MII interfaces 3 UARTs 1 with hardware flow control (up to 3 Mbps) 2 with software flow control (baud rate up to 7 Mbps)
3 independent SSP Synchronous Serial Port (SPI, Microwire or TI protocol) ports GPIOs with interrupt capability SDIO interface supporting SPI, SD1, SD4 and SD8 mode
Expanded automation mode

The Expanded automation operating mode mainly provides:

External Memory Interface (16 data bits, 24 address bits and 4 chip selects) NAND flash interface (8-16 bits and 4 chip selects shared with EMI) 2 CAN2.0 interfaces SMII or MII interface 3 UARTs 1 with hardware flow control (up to 3 Mbps) 1 with hardware flow control (baud rate up to 7 Mbps) 1 with software flow control (baud rateup to 7 Mbps)
SSP port 2 independent I2C interfaces Up to 4 PWM outputs GPIOs with interrupt capabilities
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SPEAr320
Pin description
Printer mode
The printer operating mode mainly provides:

NAND Flash interface (8 bits, 4 chip selects) Up to 4 PWM outputs 2 SMII interfaces 3 UARTs 1 with hardware flow control (up to 3 Mbps) 1 with hardware flow control (baud rate up to 7 Mbps) 1 with software flow control (baud rate up to 7 Mbps)
SDIO interface supporting SPI, SD1, SD4 and SD8 mode Standard Parallel Port (SPP device implementation) 2 independent SSP Synchronous Serial Ports (SPI, Microwire or TI protocol) GPIOs with interrupt capabilities
4.3.3
Alternate functions
Other peripheral functions are listed in the Alternate Functions column of Table 10: PL_GPIO multiplexing scheme and can be individually enabled/disabled configuring the bits of a dedicated control register. Refer to the user manual for the register descriptions.
4.3.4
Boot pins
The status of the boot pins is read at startup by the BootROM. Refer to the description of the Boot register in the SPEAr320 user manual.
4.3.5
GPIOs
The PL_GPIO pins can be used as software controlled general purpose I/Os (GPIOs) if they are not used by the I/O functions of the SPEAr320 IPs. To configure any PL_GPIO pin as GPIO, set the corresponding bit in the GPIO_Select(0 ..3) registers that are 102 bits write registers that select GPIO versus some IPs. Please refer to the SPEAr320 user manual for more detail about these registers.
4.3.6
Multiplexing scheme
To provide the best I/O multiplexing flexibility and the higher number of GPIOs for ARM controlled input-output function, the following hierarchical multiplexing scheme has been implemented.
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Pin description Figure 4. Hierarchical multiplexing scheme

Embedded IPs
SPEAr320
PL_GPIO
GPIOs
SMII automation networking MII automation networking Expanded automation Printer Programmer model control register bits (2:0) GPIO_Select(0 ..3) registers embedded/custom logic selector
Table 10.
PL_GPIO multiplexing scheme

Boot pins Configuration mode (enabled by Programmer model control register bits (2:0)) Alternate function (enabled by embedded/ custom selector) Function in GPIO alternative mode
PL_GPIO_# / ball number
PL_GPIO_97/H16 PL_GPIO_96/H15 PL_GPIO_95/H14 PL_GPIO_94/H13 PL_GPIO_93/G17 PL_GPIO_92/G16 PL_GPIO_91/G15 PL_GPIO_90/G14 PL_GPIO_89/F17 PL_GPIO_88/F16 PL_GPIO_87/G13 PL_GPIO_86/E17 PL_GPIO_85/F15 PL_GPIO_84/D17 PL_GPIO_83/E16
CLD0 CLD1 CLD2 CLD3 CLD4 CLD5 CLD6 CLD7 CLD8 CLD9 CLD10 CLD11 CLD12 CLD13 CLD14
MII1_TXCLK MII1_TXD0 MII1_TXD1 MII1_TXD2 MII1_TXD3 MII1_TXEN MII1_TXER MII1_RXCLK MII1_RXDV MII1_RXER MII1_RXD0 MII1_RXD1 MII1_RXD2 MII1_RXD3 MII1_COL
EMI_A0 EMI_A1 EMI_A2 EMI_A3 EMI_A4 EMI_A5 EMI_A6 EMI_A7 EMI_A8 EMI_A9 EMI_A10 EMI_A11 EMI_A12 EMI_A13 EMI_A14
0 0 0 0 0 0 0 0 0 0 0 0 SPP_DATA0 SPP_DATA1 SPP_DATA2
GPIO_97 GPIO_96 GPIO_95 GPIO_94 GPIO_93 GPIO_92 GPIO_91 GPIO_90 GPIO_89 GPIO_88 GPIO_87 GPIO_86 GPIO_85 GPIO_84 GPIO_83
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SPEAr320 Table 10. PL_GPIO multiplexing scheme (continued)
Pin description
Boot pins
H7 H6 H5 H4 H3 H2 H1
Configuration mode (enabled by Programmer model control register bits (2:0))
Alternate function (enabled by embedded/ custom selector)
Function in GPIO alternative mode
PL_GPIO_82/E15 PL_GPIO_81/C17 PL_GPIO_80/D16 PL_GPIO_79/F14 PL_GPIO_78/D15 PL_GPIO_77/B17 PL_GPIO_76/F13 PL_GPIO_75/E14 PL_GPIO_74/C16 PL_GPIO_73/A17 PL_GPIO_72/B16 PL_GPIO_71/D14
CLD15 CLD16 CLD17 CLD18 CLD19 CLD20 CLD21 CLD22 CLD23 CLAC CLFP CLLP
MII1_CRS MII1_MDIO MII1_MDC 0 0 0 0 0 0 0 0 0
EMI_A15 EMI_A16 EMI_A17 EMI_A18 EMI_A19 EMI_A20 EMI_A21 EMI_A22 EMI_A23 EMI_D8/ FSMC_D8 EMI_D9/ FSMC_D9 EMI_D10/ FSMC_D10 EMI_D11/ FSMC_D11 EMI_WAIT EMI_D0/ FSMC_D0 EMI_D1/ FSMC_D0 EMI_D2/ FSMC_D2 EMI_D3/ FSMC_D3 EMI_D4/ FSMC_D4 EMI_D5/ FSMC_D5 EMI_D6/ FSMC_D6 EMI_D7/ FSMC_D7 FSMC_ADDR_LE EMI_WE/ FSMC_WE EMI_OE/ FSMC_RE FSMC_CMD_LE
SPP_DATA3 SPP_DATA4 SPP_DATA5 SPP_DATA6 SPP_DATA7 SPP_STRBn SPP_ACKn SPP_BUSY SPP_PERROR SPP_SELECT SPP_AUTOFDn SPP_FAULTn
GPIO_82 GPIO_81 GPIO_80 GPIO_79 GPIO_78 GPIO_77 GPIO_76 GPIO_75 GPIO_74 GPIO_73 GPIO_72 GPIO_71
PL_GPIO_70/C15 PL_GPIO_69/A16 PL_GPIO_68/B15 PL_GPIO_67/C14 PL_GPIO_66/E13 PL_GPIO_65/B14 PL_GPIO_64/D13 PL_GPIO_63/C13 PL_GPIO_62/A15 PL_GPIO_61/E12 PL_GPIO_60/A14
CLLE CLPOWER FSMC_D0 FSMC_D1 FSMC_D2 FSMC_D3 FSMC_D4 FSMC_D5 FSMC_D6 FSMC_D7
0 0 FSMC_D0 FSMC_D1 FSMC_D2 FSMC_D3 FSMC_D4 FSMC_D5 FSMC_D6 FSMC_D7
SPP_INITn SPP_SELINn FSMC_D0 FSMC_D1 FSMC_D2 FSMC_D3 FSMC_D4 FSMC_D5 FSMC_D6 FSMC_D7 FSMC_ADDR_LE
GPIO_70 GPIO_69 GPIO_68 GPIO_67 GPIO_66 GPIO_65 GPIO_64 GPIO_63 GPIO_62 GPIO_61 GPIO_60
FSMC_ADDR_L FSMC_ADDR_L E FSMC_WE E FSMC_WE
PL_GPIO_59/B13
FSMC_WE
GPIO_59
PL_GPIO_58/D12
FSMC_RE FSMC_CMD_ LE FSMC_RDY /BSY
FSMC_RE FSMC_CMD_ LE FSMC_RDY/ BSY
FSMC_RE
GPIO_58
PL_GPIO_57/E11
FSMC_CMD_LE
GPIO_57
PL_GPIO_56/C12
FSMC_RDY/BSY
FSMC_RDY/ BSY
GPIO_56
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Pin description Table 10. PL_GPIO multiplexing scheme (continued)

Boot pins
H0 B3 B2 B1 B0 TMR_CPTR4 TMR_CPTR3
SPEAr320
PL_GPIO_55/A13
FSMC_CS0
FSMC_CS0
EMI_CE0/ FSMC_CS0 EMI_CE1/ FSMC_CS1 EMI_CE2/ FSMC_CS2 EMI_CE_3/ FSMC_CS3 EMI_BYTEN0 EMI_BYTEN1 EMI_D12/ FSMC_D12 EMI_D13/ FSMC_D13 EMI_D14/ FSMC_D14 EMI_D15/ FSMC_D15 UART1_DCD UART1_DSR UART1_RTS 0 0 0 0 0 0 UART1_CTS UART1_DTR UART1_RI CAN0_TX CAN0_RX CAN1_TX
FSMC_CS0
GPIO_55
PL_GPIO_54/E10
FSMC_CS1
FSMC_CS1
FSMC_CS1
GPIO_54
PL_GPIO_53/D11
FSMC_CS2
FSMC_CS2
FSMC_CS2
GPIO_53
PL_GPIO_52/B12 PL_GPIO_51/D10 PL_GPIO_50/A12 PL_GPIO_49/C11
FSMC_CS3 SD_CD SD_DAT7 SD_DAT6
GPIO_52 GPIO_51 GPIO_50 GPIO_49
PL_GPIO_48/B11
SD_DAT5
SD_DAT5
SD_DAT5
TMR_CPTR2
GPIO_48
PL_GPIO_47/C10
SD_DAT4
SD_DAT4
SD_DAT4
TMR_CPTR1
GPIO_47
PL_GPIO_46/A11 PL_GPIO_45/B10 PL_GPIO_44/A10 PL_GPIO_43/E9 PL_GPIO_42/D9 PL_GPIO_41/C9 PL_GPIO_40/B9 PL_GPIO_39/A9 PL_GPIO_38/A8 PL_GPIO_37/B8 PL_GPIO_36/C8 PL_GPIO_35/D8 PL_GPIO_34/E8 PL_GPIO_33/E7 PL_GPIO_32/D7 PL_GPIO_31/C7
SD_DAT3 SD_DAT2 SD_DAT1 SD_DAT0 Reserved Reserved Reserved Reserved PWM0 PWM1 TOUCHSCREE NX Reserved SD_LED / PWM2 CAN0_TX CAN0_RX CAN1_TX
SD_DAT3 SD_DAT2 SD_DAT1 SD_DAT0 Reserved Reserved Reserved Reserved PWM0 PWM1 0 0 SD_LED / PWM2 CAN0_TX CAN0_RX CAN1_TX
SD_DAT3 SD_DAT2 SD_DAT1 SD_DAT0 0 0 0 0 0 0 UART1_CTS UART1_DTR UART1_RI UART1_DCD UART1_DSR UART1_RTS
TMR_CLK4 TMR_CLK3 TMR_CLK2 TMR_CLK1 UART0_DTR UART0_RI UART0_DSR UART0_DCD UART0_CTS UART0_RTS SSP0_CS4 SSP0_CS3 SSP0_CS2 basGPIO5 basGPIO4 basGPIO3
GPIO_46 GPIO_45 GPIO_44 GPIO_43 GPIO_42 GPIO_41 GPIO_40 GPIO_39 GPIO_38 GPIO_37 GPIO_36 GPIO_35 GPIO_34 GPIO_33 GPIO_32 GPIO_31
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SPEAr320 Table 10. PL_GPIO multiplexing scheme (continued)
Pin description
Boot pins

basGPIO2
PL_GPIO_30/B7 PL_GPIO_29/A7 PL_GPIO_28/A6 PL_GPIO_27/B6 PL_GPIO_26/A5 PL_GPIO_25/C6 PL_GPIO_24/B5 PL_GPIO_23/A4 PL_GPIO_22/D6 PL_GPIO_21/C5 PL_GPIO_20/B4 PL_GPIO_19/A3 PL_GPIO_18/D5 PL_GPIO_17/C4 PL_GPIO_16/E6 PL_GPIO_15/B3 PL_GPIO_14/A2 PL_GPIO_13/A1 PL_GPIO_12/D4 PL_GPIO_11/E5 PL_GPIO_10/C3 PL_GPIO_9/B2 PL_GPIO_8/C2 PL_GPIO_7/D3 PL_GPIO_6/B1 PL_GPIO_5/D2 PL_GPIO_4/C1 PL_GPIO_3/D1 PL_GPIO_2/E4 PL_GPIO_1/E3 PL_GPIO_0/F3
CAN1_RX UART1_TX UART1_RX SMII0_TX SMII0_RX SMII1_TX SMII1_RX SMII_SYNC SMII_CLKOUT SMII_CLKIN SSP1_MOSI SSP1_CLK SSP1_SS0 SSP1_MISO SSP2_MOSI SSP2_CLK SSP2_SS0 SSP2_MISO PWM3 SMII_MDIO SMII_MDC 0 0 0 0 0 0 0 0 UART2_TX UART2_RX
CAN1_RX UART1_TX UART1_RX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART2_TX UART2_RX
CAN1_RX UART1_TX UART1_RX SMII0_TX SMII0_RX 0 0 SMII_SYNC SMII_CLKOUT SMII_CLKIN 0 0 0 0 0 PWM0 PWM1 PWM2 PWM3 SMII_MDIO SMII_MDC 0 0 0 0 0 0 0 0 UART2_TX UART2_RX UART1_TX UART1_RX SMII0_TX SMII0_RX SMII1_TX SMII1_RX SMII_SYNC SMII_CLKOUT SMII_CLKIN SSP1_MOSI SSP1_CLK SSP1_SS0 SSP1_MISO 0 PWM0 PWM1 PWM2 PWM3 SMII_MDIO SMII_MDC 0 0 0 0 0 0 0 0 UART2_TX UART2_RX
GPIO_30 GPIO_29 GPIO_28 GPIO_27 GPIO_26 GPIO_25 GPIO_24 GPIO_23 GPIO_22 GPIO_21 GPIO_20 GPIO_19 GPIO_18 GPIO_17 GPIO_16 GPIO_15 GPIO_14 GPIO_13 GPIO_12 GPIO_11 GPIO_10 GPIO_9 GPIO_8 GPIO_7 GPIO_6 GPIO_5 GPIO_4 GPIO_3 GPIO_2 GPIO_1 GPIO_0
basGPIO1 basGPIO0 MII0_TXCLK MII0_TXD0 MII0_TXD1 MII0_TXD2 MII0_TXD3 MII0_TXEN MII0_TXER MII0_RXCLK MII0_RXDV MII0_RXER MII0_RXD0 MII0_RXD1 MII0_RXD2 MII0_RXD3 MII0_COL MII0_CRS MII0_MDC MII0_MDIO SSP0_MOSI SSP0_CLK SSP0_SS0 SSP0_MISO I2C0_SDA I2C0_SCL UART0_RX UART0_TX IrDA_RX IrDA_TX
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Pin description Table 10. PL_GPIO multiplexing scheme (continued)

Boot pins Configuration mode (enabled by Programmer model control register bits (2:0)) Alternate function (enabled by embedded/ custom selector)
PL_CLK1 PL_CLK2 PL_CLK3 PL_CLK4
SPEAr320
PL_CLK1/K17 PL_CLK2/J17 PL_CLK3/J16 PL_CLK4/H17
CLCP SD_CLK SD_WP SD_CMD
0 SD_CLK SD_WP SD_CMD
I2C1_SDA I2C1_SCL 0 0
SD_LED SD_CLK SD_WP SD_CMD
GPIO_98 GPIO_99 GPIO_100 GPIO_101
Note:
Table 10 cells filled with 0 or 1 are unused and unless otherwise configured as Alternate function or GPIO, the corresponding pin is held at low or high level respectively by the internal logic. Pins shared by EMI and FSMC: Depending on the AHB address to be accessed the pins are used for EMI or FSMC transfers. Table 11. Table shading
Shading FSMC EMI CLCD Touchscreen UART CAN Ethernet MAC SDIO/MMC PWM timers GPT IrDa SSP I2C Standard Parallel port Pin group FSMC pins: NAND Flash EMI pins Color LCD controller pins Touchscreen pins UART pins CAN pins MII/SMII Ethernet Mac pins SD card controller pins Pulse-width modulator timer module pins Timer pins IrDa pins SSP pins I2C pins Standard parallel port pins
Note:
For the full description of the I/O functions related to each IP, please refer to the corresponding sections of the SPEAR320 user manual.
4.4
PL_GPIO pin sharing for debug modes

In some cases the PL_GPIO pins may be used in different ways for debugging purposes. There are three different cases (see also Table 12):
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SPEAr320 1.
Pin description Case 1 - All the PL_GPIO get values from Boundary scan registers during Ex-test instruction of JTAG . Typically this configuration is used to verify correctness of the soldering process during the production flow . Case 2 - All the PL_GPIO maintain their original meaning but the JTAG Interface is connected to the processor. This configuration is useful during the development phase but offers only "static" debug. Case 3 - Some PL_GPIO, as shown inTable 12: Ball sharing during debug, are used to connect the ETM9 lines to an external box. This configuration is typically used only during the development phase. It offers a very powerful debug capability. When the processor reaches a breakpoint it is possible, by analyzing the trace buffer, to understand the reason why the processor has reached the break. Ball sharing during debug
Case 1 - no debug 0 0 0 0 1 nTRST_bscan TCK_bscan TSM_bscan TDI_bscan TDO_bscan BSR Value BSR Value BSR Value BSR Value BSR Value BSR Value BSR Value BSR Value BSR Value BSR Value BSR Value BSR Value BSR Value BSR Value BSR Value BSR Value Case 2 - static debug 1 0 0/1 0/1 0/1 nTRST_ARM TCK_ARM TMS_ARM TDI_ARM TDO_ARM Original meaning Original meaning Original meaning Original meaning Original meaning Original meaning Original meaning Original meaning Original meaning Original meaning Original meaning Original meaning Original meaning Original meaning Original meaning Original meaning 0 1 0/1 0/1 0/1 nTRST_ARM TCK_ARM TSM_ARM TDI_ARM TDO_ARM ARM_TRACE_CLK ARM_TRACE_PKTA[0] ARM_TRACE_PKTA[1] ARM_TRACE_PKTA[2] ARM_TRACE_PKTA[3] ARM_TRACE_PKTB[0] ARM_TRACE_PKTB[1] ARM_TRACE_PKTB[2] ARM_TRACE_PKTB[3] ARM_TRACE_SYNCA ARM_TRACE_SYNCB ARM_PIPESTATA[0] ARM_PIPESTATA[1] ARM_PIPESTATA[2] ARM_PIPESTATB[0] ARM_PIPESTATB[1] Case 3 - full debug
2.
3.
Table 12.
Signals Test[0] Test[1] Test[2] Test[3] Test[4] nTRST TCK TMS TDI TDO PL_GPIO[97] PL_GPIO[96] PL_GPIO[95] PL_GPIO[94] PL_GPIO[93] PL_GPIO[92] PL_GPIO[91] PL_GPIO[90] PL_GPIO[89] PL_GPIO[88] PL_GPIO[87] PL_GPIO[86] PL_GPIO[85] PL_GPIO[84] PL_GPIO[83] PL_GPIO[82]
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Pin description Table 12. Ball sharing during debug (continued)

Case 1 - no debug BSR Value BSR Value BSR Value BSR Value BSR Value BSR Value BSR Value BSR Value BSR Value Case 2 - static debug Original meaning Original meaning Original meaning Original meaning Original meaning Original meaning Original meaning Original meaning Original meaning
SPEAr320
Signals PL_GPIO[81] PL_GPIO[80] PL_GPIO[79] PL_GPIO[78] PL_GPIO[77] PL_GPIO[76] PL_GPIO[75] PL_GPIO[74] PL_GPIO[73] PL_GPIO[72:0]
Case 3 - full debug ARM_PIPESTATB[2] ARM_TRACE_PKTA[4] ARM_TRACE_PKTA[5] ARM_TRACE_PKTA[6] ARM_TRACE_PKTA[7] ARM_TRACE_PKTB[4] ARM_TRACE_PKTB[5] ARM_TRACE_PKTB[6] ARM_TRACE_PKTB[7]
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SPEAr320
Memory map
Memory map
Table 13. SPEAr320 main memory map
End address 0x3FFF.FFFF 0xBFFF.FFFF 0xCFFF.FFFF 0xD007.FFFF 0xD00F.FFFF 0xD017.FFFF 0xD01F.FFFF 0xD07F.FFFF 0xD0FF.FFFF 0xD17F.FFFF 0xD1FF.FFFF 0xD7FF.FFFF 0xE07F.FFFF 0xE0FF.FFFF 0xE10F.FFFF 0xE11F.FFFF 0xE12F.FFFF 0xE17F.FFFF 0xE18F.FFFF 0xE19F.FFFF 0xE20F.FFFF 0xE21F.FFFF 0xE27F.FFFF 0xE28F.FFFF 0xE7FF.FFFF 0xEFFF.FFFF 0xF00F.FFFF 0xF10F.FFFF 0xF11F.FFFF 0xF7FF.FFFF 0xFBFF.FFFF Peripheral External DRAM UART0 ADC SSP0 I2C0 JPEG CODEC IrDA SRAM Ethernet controller USB 2.0 device USB 2.0 device USB 2.0 device USB2.0 EHCI 0-1 USB2.0 OHCI 0 USB2.0 OHCI 1 ML USB ARB Timer0 ITC Primary Serial Flash memory Reserved Reserved Reserved Configuration register Reserved Reserved Reserved Reserved Static RAM shared memory (8 Kbytes) Reserved MAC FIFO Configuration registers Plug detect Reserved Reserved Description Low power DDR or DDR2 Reconfigurable array subsystem (See Table 14) Reserved
Start address 0x0000.0000 0x4000.0000 0xC000.0000 0xD000.0000 0xD008.0000 0xD010.0000 0xD018.0000 0xD020.0000 0xD080.0000 0xD100.0000 0xD180.0000 0xD280.0000 0xD800.0000 0xE080.0000 0xE100.0000 0xE110.0000 0xE120.0000 0xE130.0000 0xE180.0000 0xE190.0000 0xE1A0.0000 0xE210.0000 0xE220.0000 0xE280.0000 0xE290.0000 0xE800.0000 0xF000.0000 0xF010.0000 0xF110.0000 0xF120.0000 0xF800.0000
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Memory map Table 13. SPEAr320 main memory map (continued)

End address 0xFC1F.FFFF 0xFC3F.FFFF 0xFC5F.FFFF 0xFC7F.FFFF 0xFC87.FFFF 0xFC8F.FFFF 0xFC97.FFFF 0xFC9F.FFFF 0xFCA7.FFFF 0xFCAF.FFFF 0xFCB7.FFFF 0xFCFF.FFFF 0xFEFF.FFFF 0xFFFF.FFFF Peripheral Serial Flash controller DMA controller DRAM controller Timer 1 Watchdog timer Real time clock basGPIO System controller Miscellaneous registers Timer 2 BootROM Reserved Reserved Reserved
SPEAr320
Start address 0xFC00.0000 0xFC20.0000 0xFC40.0000 0xFC60.0000 0xFC80.0000 0xFC88.0000 0xFC90.0000 0xFC98.0000 0xFCA0.0000 0xFCA8.0000 0xFCB0.0000 0xFCB8.0000 0xFD00.0000 0xFF00.0000
Description
Table 14.
Reconfigurable array subsystem memory map

End address 0x47FF_FFFF 0x4BFF_FFFF 0x5FFF_FFFF 0x6FFF_FFFF 0x7FFF_FFFF 0x8000_3FFF 0x8FFF_FFFF 0x9FFF_FFFF 0xA0FF_FFFF 0xA1FF_FFFF 0xA2FF_FFFF 0xA3FF_FFFF 0xA4FF_FFFF 0xA5FF_FFFF 0xA6FF_FFFF 0xA7FF_FFFF 0xA8FF_FFFF 0xA9CF_FFFF EMI Reserved FSMC Reserved SDIO Boot memory Reserved CLCD Parallel port CAN0 CAN1 UART1 UART2 SSP1 SSP2 I2C1 Quad PWM timer GPIO Peripheral Description
Start address 0x4000_0000 0x4800_0000 0x4C00_0000 0x6000_0000 0x7000_0000 0x8000_0000 0x8000_4000 0x9000_0000 0xA000_0000 0xA100_0000 0xA200_0000 0xA300_0000 0xA400_0000 0xA500_0000 0xA600_0000 0xA700_0000 0xA800_0000 0xA900_0000
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SPEAr320 Table 14. Reconfigurable array subsystem memory map (continued)

End address 0xA9FF_FFFF 0xAAFF_FFFF 0xABFF_FFFF 0xB2FF_FFFF 0xBFFF_FFFF Peripheral Reserved SMII0 SMII1/MII Reserved AHB interface
Memory map
Start address 0xA9D0_0000 0xAA00_0000 0xAB00_0000 0xAC00_0000 0xB300_0000
Description
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Electrical characteristics
SPEAr320
6
6.1
Absolute maximum ratings
This product contains devices to protect the inputs against damage due to high/low static voltages. However it is advisable to take normal precaution to avoid application of any voltage higher/lower than the specified maximum/minimum rated voltages. The absolute maximum rating is the maximum stress that can be applied to a device without causing permanent damage. However, extended exposure to minimum/maximum ratings may affect long-term device reliability. Table 15.
Symbol VDD 1.2 VDD 3.3 VDD 2.5 VDD 1.8 VDD RTC TSTG TJ
Absolute maximum ratings

Parameter Supply voltage for the core Supply voltage for the I/Os Supply voltage for the analog blocks Supply voltage for the DRAM interface RTC supply voltage Storage temperature Junction temperature Minimum value Maximum value - 0.3 - 0.3 - 0.3 - 0.3 -0.3 -55 -40 1.44 3.9 3 2.16 2.16 150 125 Unit V V V V V C C
6.2
Note:
Maximum power consumption

These values take into consideration the worst cases of process variation and voltage range and must be used to design the power supply section of the board. Table 16.
Symbol VDD 1.2 VDD 1.8 VDD RTC VDD 2.5 VDD 3.3 PD

Description Supply voltage for the core Supply voltage for the DRAM interface (1) RTC supply voltage Supply voltage for the analog blocks Supply voltage for the I/Os
(2)
Max 420 160 8 35 15 930(3)
Unit mA mA A mA mA mW
1. Peak current with Linux memory test (50% write and 50% read) plus DMA reading memory. 2. With 30 logic channels connected to the device and simultaneously switching at 10 MHz.
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SPEAr320
3. The maximum current and power values listed above, obtained with typical supply voltages, are not guaranteed to be the highest obtainable. These values are dependent on many factors including the type of applications running, clock rates, use of internal functional capabilities, external interface usage, case temperature, and the power supply voltages. Your specific application can produce significantly different results. 1.2 V current and power are primarily dependent on the applications running and the use of internal chip functions (DMA, USB, Ethernet, and so on). 3.3 V current and power are primarily dependent on the capacitive loading, frequency, and utilization of the external buses.
6.3
DC electrical characteristics
The recommended operating conditions are listed in the following table: Table 17.
Symbol VDD 1.2 VDD 3.3 VDD 2.5 VDD 2.5 VDD 1.8 VDD RTC TC
Recommended operating conditions

Parameter Supply voltage for the core Supply voltage for the I/Os PLL supply voltage Oscillator supply voltage Supply voltage for DRAM interface RTC supply voltage Operating temperature Min 1.14 3 2.25 2.25 1.70 1.3 -40 Typ 1.2 3.3 2.5 2.5 1.8 1.5 Max 1.3 3.6 2.75 2.75 1.9 1.8 85 Unit V V V V V V C
6.4
Overshoot and undershoot

This product can support the following values of overshoot and undershoot. Table 18. Overshoot and undershoot specifications
Parameter Amplitude Ratio of overshoot (or undershoot) duration with respect to pulse width 3V3 I/Os 500 mV 1/3 2V5 I/Os 500 mV 1/3 1V8 I/Os 500 mV 1/3
If the amplitude of the overshoot/undershoot increases (decreases), the ratio of overshoot/undershoot width to the pulse width decreases (increases). The formula relating the two is: Amplitude of OS/US = 0.75*(1- ratio of OS (or US) duration with respect to pulse width) Note: The value of overshoot/undershoot should not exceed the value of 0.5 V. However, the duration of the overshoot/undershoot can be increased by decreasing its amplitude.
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SPEAr320
6.5
3.3V I/O characteristics

The 3.3 V I/Os are compliant with JEDEC standard JESD8b Table 19.
Symbol VIL VIH Vhyst
Low voltage TTL DC input specification (3 V< VDD <3.6 V)

Parameter Low level input voltage High level input voltage Schmitt trigger hysteresis 2 300 800 Min Max 0.8 Unit V V mV
Table 20.
Symbol VOL VOH
Low voltage TTL DC output specification (3 V< VDD <3.6 V)

Parameter Low level output voltage High level output voltage Test condition IOL= X mA (1) IOH= -X mA
(1)
Min
Max 0.3
Unit V V
VDD - 0.3
1. For the max current value (X mA) refer to Section 4: Pin description.
Table 21.
Symbol RPU RPD
Pull-up and pull-down characteristics

Parameter Equivalent pull-up resistance Equivalent pull-down resistance Test condition VI = 0 V VI = VDDE3V3 Min 29 29 Max 67 103 Unit k k
6.6
LPDDR and DDR2 pin characteristics

Table 22.
Symbol VIL
DC characteristics
Parameter Low level input voltage SSTL18 SSTL2 High level input voltage SSTL18 Input voltage hysteresis -0.3 VREF+0.15 VREF+0.125 200 Test condition SSTL2 Min -0.3 Max VREF-0.15 VREF-0.125 VDDE2V5+0.3 VDDE1V8+0.3 Unit V V V V mV
VIH Vhyst
Table 23.
Symbol
Driver characteristics
Parameter Output impedance (strong value) Min 40.5 44.1 Typ 45 49 Max 49.5 53.9 Unit
RO Output impedance (weak value)
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SPEAr320 Table 24.

Symbol RT1*
Electrical characteristics On die termination

Parameter Termination value of resistance for on die termination Termination value of resistance for on die termination Min Typ 75 Max Unit
RT2*
150
Table 25.
Symbol VREFIN
Reference voltage
Parameter Voltage applied to core/pad Min 0.49 * VDDE Typ 0.500 * VDDE Max 0.51 * VDDE Unit V
6.7
Power up sequence
It is recommended to power up the power supplies in the order shown in Figure 5. VDD 1.2 is brought up first, followed by VDD 1.8, then VDD 2.5 and finally VDD 3.3. Figure 5. Power-up sequence
Power-up sequence
VDD 1.2
VDD1.8
V DD 2.5
V DD 3.3
6.8
Removing power supplies for power saving

It is recommended to remove the the power supplies in the order shown in Figure 6. So VDD 3.3 supply is to be removed first, then the VDD 2.5 supply, followed by the VDD 1.8 supply and last the VDD 1.2.
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Electrical characteristics Figure 6. Power-down sequence

Power-down sequence V DD 1.2
SPEAr320
V DD 1.8
V DD 2.5
V DD 3.3
6.9
Power on reset (MRESET)

The MRESET must remain active for at least 10 ms after all the power supplies are in the correct range and should become active in no more than 10 s when one of the power supplies goes out of the correct range.
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Timing requirements
7
7.1
Timing requirements
DDR2 timing characteristics
The characterization timing is done considering an output load of 10 pF on all the DDR pads. The operating conditions are in worst case V = 0.90 V TA = 125 C and in best case V=1.10 V TA = 40 C.
7.1.1
DDR2 read cycle timings

Figure 7. DDR2 Read cycle waveforms
DQS t4 DQ t5 t4 t5 t4
Figure 8.
DDR2 Read cycle path
DQ
t3
D SET Q t1 t2
CLR
DQS
DLL
Table 26.
DDR2 Read cycle timings

Frequency 333 MHz 266 MHz 200 MHz t4 max 1.24 ns 1.43 ns 1.74 ns t5 max -495 ps -306 ps 4 ps t5 max -495 ps -306 ps 4 ps
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Timing requirements Table 26. DDR2 Read cycle timings (continued)

Frequency 166 MHz 133 MHz t4 max 2.00 ns 2.37 ns t5 max 260 ps 634 ps
SPEAr320
t5 max 260 ps 634 ps
7.1.2
DDR2 write cycle timings

Figure 9. DDR2 Write cycle waveforms t6 CLK t6 t6
DQS
t4 DQ
t5
t4
t5
t4
t5
Figure 10. DDR2 Write cycle path
Table 27.
DDR2 Write cycle timings

Frequency 333 MHz 266 MHz 200 MHz 166 MHz 133 MHz t4 max 1.36 1.55 1.86 2.11 2.49 t5 max -1.55 -1.36 -1.05 - 794 -420 Unit ns ns ns ns ns
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Timing requirements
7.1.3
DDR2 command timings

Figure 11. DDR2 Command waveforms
CLK
ADDRESS, STROBEs, AND CONTROL LINES
t4
t5
Figure 12. DDR2 Command path
Table 28.
DDR2 Command timings

Frequency 333 MHz 266 MHz 200 MHz 166 MHz 133 MHz t4 max 1.39 1.77 2.39 2.90 3.65 t5 max 1.40 1.78 2.40 2.91 3.66 Unit ns ns ns ns ns
7.2
CLCD timing characteristics

The characterization timing is done considering an output load of 10 pF on all the outputs. The operating conditions are in worst case V=0.90 V T=125 C and in best case V =1.10 V T= 40 C. The CLCD has a wide variety of configurations and setting and the parameters change accordingly. Two main scenarios will be considered, one with direct clock to output
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Timing requirements
SPEAr320
(166 MHz), setting BCD bit to '1', and the second one with the clock passing through a clock divider (83 MHz), setting BCD bit to '0'.
7.2.1
CLCD timing characteristics direct clock

Figure 13. CLCD waveform with CLCP direct
CLCP Tmax
Tclock
Tmin CLD[23:0], CLAC, CLLE, CLLP, CLFP, CLPOWER
Tstable Tf Tr
Figure 14. CLCD block diagram with CLCP direct
t1 CLCDCLK D
SET
CLD[23:0], CLAC, CLLE, CLLP, CLFP, CLPOWER t2
CLR
CLCP t3
Table 29. CLCD timings with CLCP direct
Parameter tCLOCK direct max (tCLOCK ) tCLOCK direct max rise (tr) tCLOCK direct max (tf) tmin tmax tSTABLE Value 6 ns 0.81 ns 0.87 ns -0.04 ns 3.62 ns 2.34 ns Frequency 166 MHz
Note:
1 2 3
tSTABLE = tCLOCK direct max - (tmax + tmin) For tmax the maximum value is taken from the worst case and best case, while for tmin the minimum value is taken from the worst case and best case. CLCP should be delayed by {tmax + [tCLOCK direct max - (tmax + tmin)]/2} = 4.7915 ns
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Timing requirements
7.2.2
CLCD timing characteristics divided clock

Figure 15. CLCD waveform with CLCP divided
CLCP Tmax Tclock
Tmin CLD[23:0], CLAC, CLLE, CLLP, CLFP, CLPOWER
Tstable Tf Tr
Figure 16. CLCD block diagram with CLCP divided
t1 CLCDCLK D
SET
CLD[23:0], CLAC, CLLE, CLLP, CLFP, CLPOWER t2 CLCP D

SET
CLR
t3
CLR
Table 30.
CLCD timings with CLCP divided

Parameter Value 12 ns 0.81 ns 0.87 ns -0.49 ns 2.38 ns 9.13 ns Frequency 83.3 MHz
tCLOCK divided max tCLOCK divided max rise (tr) tCLOCK divided max (tf) tmin tmax tSTABLE
Note:
1 2 3
tSTABLE = tCLOCK direct max - (tmax + tmin) For tmax the maximum value is taken from the worst case and for tmin the minimum value is taken from the best case. CLCP should be delayed by {tmax + [tCLOCK direct max - (tmax + tmin)]/2} = 6.945 ns
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Timing requirements
SPEAr320
7.3
I2C timing characteristics

The characterization timing is done using primetime considering an output load of 10 pF on SCL and SDA. The operating conditions are V = 0.90 V, TA=125 C in worst case and V =1. 10 V, TA= 40 C in best case. Figure 17. I2C output pins
D HCLK Clr Q Set Q SCL
Set
SDA
Clr
Figure 18. I2C input pins
The flip-flops used to capture the incoming signals are re-synchronized with the AHB clock: so, no input delay calculation is required. Table 31. Output delays for I2C signals
Parameter tHCLK->SCLH tHCLK->SCLL tHCLK->SDAH tHCLK->SDAL Min 8.1067 7.9874 7.5274 7.4081 Max 11.8184 12.6269 11.2453 12.0530 Unit ns ns ns ns
Those values are referred to the common internal source clock which has a period of: tHCLK = 6 ns.
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SPEAr320 Figure 19. Output signal waveforms for I2C signals
Timing requirements
The timing of high and low level of SCL (tSCLHigh and tSCLLow) are programmable. Table 32. Time characteristics for I2C in high-speed mode
Parameter tSU-STA tHD-STA tSU-DAT tHD-DAT tSU-STO tHD-STO Min 157.5897 325.9344 314.0537 ns 0.7812 637.709 4742.1628 Unit
Table 33.
Time characteristics for I2C in fast speed mode

Table 34.
Time characteristics for I2C in standard speed mode

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Timing requirements Note: 1
SPEAr320
The timings shown in Figure 19. depend on the programmed value of TSCLHigh and TSCLLow, so the values present in the three tables here above have been calculated using the minimum programmable values of : IC_HS_SCL_HCNT=19 and IC_HS_SCL_LCNT=53 registers (for High-Speed mode); IC_FS_SCL_HCNT=99 and IC_FS_SCL_LCNT=215 registers (for Fast-Speed mode); IC_SS_SCL_HCNT=664 and IC_SS_SCL_LCNT=780 registers (for Standard-Speed mode). These minimum values depend on the AHB clock frequency, which is 166 MHz.
A device may internally require a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL (Please refer to the I2C Bus Specification v3-0 Jun 2007). However, the SDA data hold time in the I2C controller of SPEAr320 is one-clock cycle based (6 ns with the HCLK clock at 166 MHz). This time may be insufficient for some slave devices. A few slave devices may not receive the valid address due to the lack of SDA hold time and will not acknowledge even if the address is valid. If the SDA data hold time is insufficient, an error may occur. Workaround: If a device needs more SDA data hold time than one clock cycle, an RC delay circuit is needed on the SDA line as illustrated in the following figure: Figure 20. RC delay circuit
For example, R=K and C = 200 pF.
7.4
FSMC timing characteristics

The characterization timing is done using primetime considering an output load of 3 pF on the data, 15 pF on NF_CE, NF_RE and NF_WE and 10 pF on NF_ALE and NF_CLE. The operating conditions are V= 0.90 V, T=125 C in worst case and V=1.10 V, T= 40 C in best case.
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Timing requirements
7.4.1
8-bit NAND Flash configuration

Figure 21. Output pads for 8-bit NAND Flash configuration
D HCLK ...
SET
CLR
...
... D
SET
NFCLE NFCE NFWE NFRE NFRWPRT NFALE NFIO_0..7
CLR
Figure 22. Input pads for 8-bit NAND Flash configuration
NFRB HCLK N F IO _ 0 ..7 CLPO W ER CLLP CLLE ( N F IO _ 8 ..1 5 ) CLFP CLCP CLAC C L D _ 2 3 ..2 2
SET
CLR
SET
C LR
Figure 23. Output command signal waveforms for 8-bit NAND Flash configuration
NFCE TCLE NFCLE TWE NFWE TIO NFIO Command
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Timing requirements
SPEAr320
Figure 24. Output address signal waveforms for 8-bit NAND Flash configuration
NFCE TALE NFALE TWE NFWE TIO NFIO Address
Figure 25. In/out data address signal waveforms for 8-bit NAND Flash configuration
NFCE NFWE NFIO (out) TRE

NFRE
TWE TIO Data Out TREAD TRE -> IO TNFIO -> FFs
NFIO (in)
Table 35.
Time characteristics for 8-bit NAND Flash configuration

Parameter Min -16.85 ns -16.84 ns 11.10 ns 11.18 ns 3.43 ns Max -19.38 ns -19.37 ns 13.04 ns 13.05 ns 8.86 ns
TCLE TALE TWE (s=1) TRE (s=1) TIO (h=1)
Note:
Values in Table 35 are referred to the common internal source clock which has a period of THCLK = 6 ns.
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Timing requirements
7.4.2
16-bit NAND Flash configuration

Figure 26. Output pads for 16-bit NAND Flash configuration
D HCLK
SET
Q Q
CLR
NFCLE NFCE NFWE NFRE NFRWPRT NFALE NFIO_0..7

...
...
...
SET
Q Q
CLR
CLPOWER CLLP CLLE CLFP CLCP CLAC CLD_23..22
(NFIO_8..15)
Figure 27. Input pads for 16-bit NAND Flash configuration

NFRB N F IO _ 0 ..7 CLPO W ER CLLP CLLE CLFP CLCP CLAC C L D _ 2 3 ..2 2 D
SET
D HCLK
SET
CLR
( N F IO _ 8 . .1 5 )
...
.. .
CLR
Figure 28. Output command signal waveforms 16-bit NAND Flash configuration
NFCE TCLE NFCLE TWE NFWE TIO NFIO Command
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Timing requirements
SPEAr320
Figure 29. Output address signal waveforms 16-bit NAND Flash configuration
NFCE TALE NFALE TWE NFWE TIO NFIO Address
Figure 30. In/out data signal waveforms for 16-bit NAND Flash configuration
NFCE NFWE NFIO (out) TRE NFRE NFIO (in)

Table 36.
TWE TIO Data Out TREAD TRE -> IO TNFIO -> FFs
Time characteristics for 16-bit NAND Flash configuration

Parameter MIN -16.85 ns -16.84 ns 11.10 ns 11.18 ns 3.27 ns -19.38 ns -19.37 ns 13.04 ns 13.05 ns 11.35 ns MAX
TCLE TALE TWE (s=1) TRE (s=1) TIO (h=1)
Note:
Values in Table 36 are referred to the common internal source clock which has a period of THCLK = 6 ns.
7.5
Ether MAC 10/100 Mbps timing characteristics

The characterization timing is given for an output load of 5 pF on the MII TX clock and 10 pF on the other pads. The operating conditions are in worst case V=0.90 V T=125 C and in best case V=1.10 V T= 40 C.
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SPEAr320
Timing requirements
7.5.1
MII transmit timing specifications

Figure 31. MII TX waveforms
MIITX_CLK Tmax Tmin Tclock
MII_TXD0-MII_TXD3, MII_TXEN, MII_TXER

Figure 32. Block diagram of MII TX pins
MII_TX[0..3], MII_TXEN, MII_TXER CLK
D
SET
Tf
Tr
t2
CLR
MII_TX[0..3], MII_TXEN, MII_TXER
t3
MII_TXCLK
Table 37.
MII TX timings
Parameter Value using MII 10 Mb [tCLK period = 40 ns 25 MHz] 6.8 ns 2.9 ns 33.2 ns Value using MII 100 Mb [tCLK period = 400 ns 2.5 MHz] 6.8 ns 2.9 ns 393.2 ns
tmax= t2max- t3min tmin= t2min- t3max tSETUP
Note:
To calculate the tSETUP value for the PHY you have to consider the next tCLK rising edge, so you have to apply the following formula: tSETUP = tCLK - tmax
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Timing requirements
SPEAr320
7.5.2
MII receive timing specifications

Figure 33. MII RX waveforms
MII_RXCLK Tclock
MII_RXD0-MII_RXD3, MII_RXER, MII_RXDV
Ts Th Tf Tr
Figure 34. Block diagram of MII RX pins
t2 MII_RX[0..3], MII_RXER, MII_RXDV D t1 MII_RXCLK

CLR SET
Q Q
7.5.3
MDIO timing specifications

Figure 35. MDC waveforms
MDC Tclock
MDIO
Input
Tsetup Thold Tf Tr
Output
Tmax Tmi n
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SPEAr320 Figure 36. Paths from MDC/MDIO pads

INPUT
Q Q
SET
Timing requirements
t1
OUTPUT
CL R
CLK
SET
t2
CL R
MDIO
t3
Table 38. MDC/MDIO timing
Parameter tCLK period tCLK fall (tf) tCLK rise (tr) Value 614.4 ns 1.18 ns 1.14 ns Output tmax = ~tCLK /2 tmin = ~tCLK /2 307 ns 307 ns Input tSETUPmax = t1max - t3min tHOLDmin = t1min - t3max 6.88 ns -1.54 ns
MDC
Frequency 1.63 MHz
Note:
When MDIO is used as output the data are launched on the falling edge of the clock as shown in Figure 35.
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Timing requirements
SPEAr320
7.6
SMI - Serial memory interface timing characteristics

Figure 37. SMI_DATAIN data path
tinput_delay tD
SMI_DATAIN SMI_CLK_i
tH tS
tCD
SMI_CLK
HCLK
tSMIDATAIN arrival
Table 39.
SMI_DATAIN timings
Signal Parameter td_max td_min Value tSMIDATAIN_arrival_max - tinput_delay tSMIDATAIN_arrival_min - tinput_delay tSMI_CLK_i_arrival_min tSMI_CLK_i_arrival_max ts + td_max-tcd_min th - td_min + tcd_max
SMI_DATAIN
tcd_min tcd_max tSETUP_max tHOLD_min
Figure 38. SMI_DATAOUT/SMI_CSn data paths
OUTPUT HCLK
SMI_CLK HCLK
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SPEAr320 Figure 39. SMI_DATAOUT timings
Timing requirements
SMI_CLK
SMI_DATAOUT(FAST)
SMI_DATAOUT(SLOW)
tdelay_min
tdelay_max tarrival
Table 40.
SMI_DATAOUT timings
Signal Parameter tdelay_max tdelay_min Value tarrivalSMIDATAOUT_max - tarrival_SMI_CLK_min tarrivalSMIDATAOUT_min - tarrival_SMI_CLK_max
SMI_DATAOUT
Figure 40. SMICSn fall timings
Table 41.
SMI_CSn fall timings

Signal Parameter tdelay_max tdelay_min Value tarrivalSMICSn_max_fall - tarrival_SMI_CLK_min_fall tarrivalSMICSn_min_fall - tarrival_SMI_CLK_max_fall
SMI_CSn fall
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Timing requirements Figure 41. SMI_CSn rise timings
SPEAr320
Table 42.
SMI_CSn rise timings

Signal Parameter tdelay_max tdelay_min Value tarrivalSMICSn_max_rise - tarrival_SMI_CLK_min_fall tarrivalSMICSn_min_rise - tarrival_SMI_CLK_max_fall
SMI_CSn rise
Table 43.
Timing requirements for SMI

Input setup-hold/output delay Parameter Max Fall time 1.8209 1.6320 8.27482 -2.595889 2.039774 1.922779 1.69768 1.7898169 1.638069 Min 1.4092 1.1959
SMI_CLK Rise time Input setup time SMI_DATAIN Input hold time SMI_DATAOUT Output valid time SMI_CS_0 Output valid time SMI_CS_1Output valid time fall rise fall rise
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SPEAr320
Timing requirements
7.7
SSP timing characteristics

This module provides a programmable length shift register which allows serial communication with other SSP devices through a 3 or 4 wire interface (SSP_CLK, SSP_MISO, SSP_MOSI and SSP_CSn). The SSP supports the following features:

Master/Slave mode operations Chip-selects for interfacing to multiple slave SPI devices. 3 or 4 wire interface (SSP_SCK, SSP_MISO, SSP_MOSI and SSP_CSn) Single interrupt Separate DMA events for SPI Receive and Transmit 16-bit shift register Receive buffer register Programmable character length (2 to 16 bits) Programmable SSP clock frequency range 8-bit clock pre-scaler Programmable clock phase (delay or no delay) Programmable clock polarity
Note:
The following tables and figures show the characterization of the SSP using the SPI protocol. Table 44.
No. 1 2 3 Tc(CLK) Tw(CLKH) Tw(CLKL)
Timing requirements for SSP (all modes)

parameters Cycle time, SSP_CLK Pulse duration, SSP_CLK high Pulse duration, SSP_CLK low value 24 0.49T - 0.51T 0.51T - 0.49T unit ns ns ns
T = Tc(CLK) = SSP_CLK period is equal to the SSP module master clock divided by a configurable divider. Figure 42. SSP_CLK timings
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Timing requirements
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7.7.1
SPI master mode timings (clock phase = 0)

Table 45.
No. 13 tsu(DIV-CLKL)
Timing requirements for SPI master mode (clock phase = 0)

Parameters Setup time, MISO (input) valid before SSP_CLK (output) rising edge Setup time, MISO (input) valid before SSP_CLK (output) falling edge Clock Polarity = 0 Clock Polarity = 1 Min -0.411 Max. -0.342 Unit ns
14
tsu(DIV-CLKH)
-0.411
-0.342
ns
15
th(CLKL-DIV)
Hold time, MISO Clock (input)valid after SSP_CLK Polarity = 0 (output) rising edge Hold time, MISO (input) valid after SSP_CLK (output) falling edge Clock Polarity = 1
0.912
1.720
ns
16
th(CLKH-DIV)
0.912
1.720
ns
P = 1/SSP_CLK in nanoseconds (ns). For example, if the SSP_CLK frequency is 83 MHz, use P = 12.048 ns Table 46.
No. 17 td(CLKH-DOV)
Switching characteristics over recommended operating conditions for SPI master mode (clock phase = 0)
Parameters Delay time, SSP_CLK (output) falling edge to MOSI (output) transition Delay time, SSP_CLK (output) rising edge to MOSI (output) transition Clock Polarity = 0 Clock Polarity = 1 Min -3.138 Max 2.175 Unit ns
18
td(CLKL-DOV)
-3.138
2.175
ns
19
td(ENL-CLKH/L)
Delay time, SSP_CSn (output) falling edge to first SSP_CLK (output) rising or falling edge Delay time, SSP_CLK (output) rising or falling edge to SSP_CSn (output) rising edge
T/2
ns
20
td(CLKH/LENH)
ns
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SPEAr320 Figure 43. SPI master mode external timing (clock phase = 0)
Timing requirements
7.7.2
SPI master mode timings (clock phase = 1)

Table 47.
No. 4 tsu(DIVCLKL)
Timing requirements for SPI master mode (clock phase = 1)

Parameters Setup time, MISO (input) valid before SSP_CLK (output) falling edge Setup time, MISO (input) valid before SSP_CLK (output) rising edge Hold time, MISO (input) valid after SSP_CLK (output) falling edge Hold time, MISO (input) valid after SSP_CLK (output) rising edge Clock polarity = 0 Clock polarity = 1 Clock polarity = 0 Clock polarity = 1 Min -0.411 Max -0.342 Unit ns
tsu(DIVCLKH)
-0.411
-0.342
ns
th(CLKLDIV)
0.912
1.720
ns
th(CLKHDIV)
0.912
1.720
ns
Table 48.
No. 8
Switching characteristics over recommended operating conditions for SPI master mode (clock phase =1 )
Parameters Min Clock Polarity = 0 Clock Polarity = 1 -3.138 Max 2.175 Unit ns
td(CLKHDOV)
Delay time, SSP_CLK (output) rising edge to MOSI (output) transition Delay time, SSP_CLK (output) falling edge to MOSI (output) transition
td(CLKLDOV)
-3.138
2.175
ns
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Timing requirements Table 48.

No. 10 td(ENLCLKH/L)
SPEAr320 Switching characteristics over recommended operating conditions for SPI master mode (clock phase =1 ) (continued)
Parameters Delay time, SSP_CSn (output) falling edge to first SSP_CLK (output) rising or falling edge Delay time, SSP_CLK (output) rising or falling edge to SSP_CSn (output) rising edge Min T Max Unit ns
11
td(CLKH/LENH)
T/2
ns
Figure 44. SPI master mode external timing (clock phase = 1)

SSP_CSn
SSP_SCLK (Clock Polarity = 0) SSP_SCLK (Clock Polarity = 1) SSP_MISO (Input) SSP_MOSI (Output)
7.8
UART timing characteristics

Figure 45. UART transmit and receive timings
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SPEAr320 Table 49.

S.No.
Timing requirements UART transmit timing characteristics

Parameters UART0 Maximum Baud Rate 1 UART1/UART2 Maximum Baud Rate UART Pulse Duration Transmit Data (TxD) UART Transmit Start Bit 0.99B(1) 0.99B(1) Min Max 3 Mbps 7 B(1) B(1) ns ns Unit
2 3
Table 50.
S.No. 4 5
UART receive timing characteristics

Parameters UART Pulse Duration Receive Data (RxD) UART Receive Start Bit Min 0.97B(1) 0.97B(1) Max 1.06B(1) 1.06B(1) Units ns ns
where (1) B = UART baud rate
7.9
Table 51.
Symbol
ADC characteristics
10-bit ADC characteristics
Parameters ADC_CLK frequency ADC supply voltage Positive reference voltage Negative reference voltage Internal reference voltage Startup time Conversion time (fADC_CLK=14 MHz) Conversion time INL DNL Integral linearity error Differential linearity error 13 0 1.95 2 50 1 2.05 Min 3 Typ Max 14 2.5 2.5 Unit MHz V V V V s s ADC_CLK cycles
fADC_CLK AVDD VREFP VREFN VIREF tSTARTUP
tCONV
1 1
LSB LSB
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Package information
SPEAr320
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 52.
Dim. Min. A A1 A2 A3 A4 b D D1 E E1 e F ddd eee fff 14.850 0.450 14.850 0.500 15.000 12.800 15.000 12.800 0.800 1.100 0.200 0.150 0.080 15.150 0.5846 0.270 0.985 0.200 0.800 0.550 15.150 0.0177 0.5846 0.0197 0.5906 0.5039 0.5906 0.5039 0.0315 0.0433 0.0078 0.0059 0.0031 0.5965 Typ. Max. 1.700 0.0106 0.0387 0.0078 0.0315 0.0217 0.5965 Min. Typ. Max. 0.0669
LFBGA289 (15 x 15 x 1.7 mm) mechanical data

mm inches
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SPEAr320 Figure 46. LFBGA289 package dimensions
Package information
Table 53.
Thermal resistance characteristics

package LFBGA289
JC C/W)
18.5
JB C/W)
24.5
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Revision history
SPEAr320
Revision history
Table 54.
Date 12-Nov-2009
Document revision history

Revision 1 Initial release. Removed I2S feature. Changed SPI to SSP where applicable. Updated Figure 1: Functional block diagram and Figure 2: Typical system architecture using SPEAr320. Corrected Figure 3: Typical SMII system. Updated the Features on the first page. Updated Section 3.15: GPIOs. Added Table 9: PL_GPIO pin description. Reviewed and updated the Section 4.3: Shared I/O pins (PL_GPIOs). Added Section 4.4: PL_GPIO pin sharing for debug modes. Updated Section 6.1: Absolute maximum ratings. Deleted the first footnote at the end of the Table 16: Maximum power consumption and modified the text in footnote 3. on page 45 Updated Table 17: Recommended operating conditions. Added VDD RTC line in the Table 15: Absolute maximum ratings and Table 16: Maximum power consumption. Updated Table 23: Driver characteristics. Deleted GMII form Section 7.5: Ether MAC 10/100 Mbps timing characteristics and also 1000 Mbps. Added Section 3.6: SDIO controller/MMC card interface. Updated Section 7.7: SSP timing characteristics. Updated Section 6.7: Power up sequence and added Section 6.8: Removing power supplies for power saving. Separeted Electrical characteristics and Timing requirements into two chapters. Changed the title of Section 6.5: 3.3V I/O characteristics. Added Table 53: Thermal resistance characteristics. Changed all the UART numbering (from 1..3 to 0..2). UART baud rate changed in Section 2: Main features and Section 4.3.2: Configuration modes from > 6 Mbps into up to 6 Mbps. Changes
2-Feb-2010
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SPEAr320 Table 54.

Date
Revision history Document revision history (continued)

Revision Changes
02-Feb-2010
Changed the baud rate for the UARTs with Hardware flow control from up to 460.8 Kbaud into up to 3 Mbps. Table 14: Reconfigurable array subsystem memory map: changed a typo error UART23 into UART2. Section 3.11: CAN controller: changed 32 message objects (132 x 32 message RAM) to 16 message objects (136 x 16 message RAM). Corrected a typo error in the Figure 25: In/out data address signal waveforms for 8-bit NAND Flash configuration and Figure 30: In/out data signal waveforms for 16-bit NAND Flash configuration. Updated Table 3: Power supply pin description and added a note at the end of the table. 2 (continued) Corrected the voltage capable of RTC in the Table 2: Master clock, RTC, Reset and 3.3 V comparator pin descriptions. Updated figures of Section 7.4: FSMC timing characteristics. Updated Figure 31: MII TX waveforms, Figure 32: Block diagram of MII TX pins, Figure 33: MII RX waveforms, Figure 34: Block diagram of MII RX pins Corrected the speed of UART1 and UART2 in Section 3.19.2: UART1 from 5 Mbps into 6 Mbps. Updated Table 2: Master clock, RTC, Reset and 3.3 V comparator pin descriptions, Table 6: USB pin descriptions andTable 8: DDR pin description Minor text corrections. Corrected pin assignment of UART0_RTS and CTS in Table 10: PL_GPIO multiplexing scheme Added Section 7.9: ADC characteristics on page 71 Changed max. speed of UART2 and UART3 in feature descriptions from 6 Mbps to 7 Mbps and updated Table 49: UART transmit timing characteristics on page 71. Corrected SRAM size from 56K to 8 Kbytes in Section 2: Main features on page 9 Updated feature descriptions for the 3 UARTs in Section 3.19: UARTs on page 20
18-Nov-2010
02-Dec-2010
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SPEAr320
Please Read Carefully:
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SPEAr320

Programmable logic controllers Factory automation Printers Device summary

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3.20 3.21 3.22 3.23

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Contents Clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.24 3.25 3.26 3.27 3.28

PL_GPIO pin sharing for debug modes . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

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Contents 7.1.2 7.1.3

SPEAr320 DDR2 write cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 DDR2 command timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

CLCD timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

I C timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 FSMC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Ether MAC 10/100 Mbps timing characteristics . . . . . . . . . . . . . . . . . . . . 60

SMI - Serial memory interface timing characteristics . . . . . . . . . . . . . . . . 64 SSP timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

UART timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

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2x Ethernet 10/100 (SMII/MII interface)

LCD controller 1024*768

6x general purpose timer USB Host 2.0

ADC 8 KBytes SRAM 3x SSP

2x I2C master/slave ARM926EJ-S @333 MHz Std parallel port

= Functions with shared I/Os depending on the device configuration.

Add title on master page

Add subtitle on master page

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Typical system architecture using SPEAr320

SMI DDR memory controller

ARM 926EJ-S up to 333 MHz 8-channel DMA 6 timers / WD

8 KB embed. SRAM 32 KB embed. ROM MMU Interrupt/syst controller

USB2.0 PHY Host

JPEG CODEC accelerator C3 Crypto accelerator

Debug, trace ETM9 RTC Clock, Reset GPIO

CAN 2x CAN 4x PWM 3x UART 3x SSP 2x I2C Controller Automation Network

CPU ARM 926EJ-S

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Embedded memory units

32 Kbytes of BootROM 8 Kbytes of SRAM

Mobile DDR/DDR2 memory controller

Serial memory interface

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External memory interface (EMI)

SDIO controller/MMC card interface

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Flexible static memory controller (FSMC)

Multichannel DMA controller

SMII/MII Ethernet controller

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SPEAr320 Figure 3. Typical SMII system

Each Ethernet port provides the following features:

MII Ethernet controller

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Architecture overview Main features:

USB2 host controller

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USB2 device controller