Journal of the Korean Physical Society, Vol. 41, No. 6, December 2002, pp.

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CMOS Delta-Sigma Frequency Synthesizer with a New Frequency Divider and a Simplied MASH Structure
Soo-Hwan Kim, Min-Sun Keel, Ki-Won Lee and Suk-Ki Kim
Department of Electronics Engineering, Korea University, Seoul 136-701

Shin-Il Lim
Department of Computer Engineering, SeoKyeong University, Seoul 136-704 (Received 23 April 2002, in nal form 7 November 2002) This paper describes a CMOS implementation of a fractional-N frequency synthesizer adopting a new frequency divider and a new simplied 3-stage MASH (multistage noise shaping) delta-sigma modulator. All functional blocks, except for the low-pass lter (LPF), are integrated on a chip. A simple frequency divider architecture with a digital comparator and a modulus mapping circuit in a delta-sigma modulator is suggested for a lower hardware complexity and less power consumption. The proposed fractional-N frequency synthesizer shows a rapid switching time of 2.8 s at a 60-MHz frequency step with inherent high reference frequency and a wide loop bandwidth. The tuning range of the voltage-controlled oscillator (VCO) is 1.62.1 GHz in the measured results. The measured VCO phase noise is as low as 110.27 dBc/Hz at a 600-kHz oset and 122.99 dBc/Hz at a 7.5MHz oset. The measured fractional spur level is 101.6 dBc. The total power consumption is 20.2 mW with a 2.5 V single power supply. The synthesizer is implemented in a 0.25-m standard CMOS process (1-poly, 5-metal) and occupies an active area of 7601280 m.
PACS numbers: 84.30.Ng Keywords: Franctional-N frequency synthesizer, Frenquency divider, Delta-Sigma modulator, Modulus mapping, LC VCO, CMOS RF circuit, Multistage noise shaping

I. INTRODUCTION The demand for higher performance RF circuits has increased with the explosive development in wireless communications. During the past years, they have been fabricated using bipolar junction transistor (BJT) or bipolar-complementary metal oxide semiconductor (BiCMOS) processes [1,2]. Recently, frequency synthesizers in CMOS processes have been designed and are widely regarded for lower power consumption and less silicon area suitable for battery-operated systems with their performances being close to the BJT or Bi-CMOS counterparts. Nowadays RF integrated circuits (ICs) in a CMOS process are focused on higher performances [3, 4]. This paper describes a CMOS fractional frequency synthesizer, one of the key blocks in RF systems, suitable for the requirements of low power, low noise, and high integration. For these requirements, we propose a new frequency divider with a simple architecture and a modulus mapping circuit for reduced hardware complexity in a 3-stage MASH delta-sigma modulator. For low power consumption and low phase noise, LC-VCO (inductorcapacitor voltage-controlled oscillator) with a planar spiral inductor is implemented, and the Q factor of the
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inductor is boosted using a patterned ground shields technique [5].

II. PROPOSED FREQUENCY DIVIDER AND DELTA-SIGMA MODULATOR The conventional fractional-N frequency synthesizer architecture is shown in Fig. 1 [6]. The frequency synthesis function of fractional-N is as follows: When the

Fig. 1. Conventional fractional-N frequency synthesizer.

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Journal of the Korean Physical Society, Vol. 41, No. 6, December 2002

Fig. 3. Similarity of the delta-sigma modulator and the accumulator.

Fig. 2. (a) Conventional frequency divider. (b) Proposed frequency divider.

carry-bit of the adder is generated, it controls the frequency divider ratio (N or N+1) of the dual modulus. If the carry-bit is 1, the divider ratio is N+1; otherwise, it is N. Equation (1) shows the relations between the input reference frequency and the VCO output frequency, where K is the input step of the adder, and m is the bit-width of the adder: fout = = (N + 1) N+ K 2m K 2m K +N 2m 2m fref fref (1)

Fig. 4. Conventional 3-stage MASH (MASH 1-1-1) structure.

From Eq. (1), the channel spacing fch is then given as fch = fref . 2m (2)

Equation (2) shows that a wider channel spacing can be achieved with a higher input reference frequency, which makes the divider ratio small and the phase-locked loop (PLL) loop bandwidth larger. Therefore, a higher input reference frequency enhances loop locking time and the in-band phase noise. However, the periodical switching in fractional-N synthesis generates a fractional spur near the carrier frequency. In general, a noise shaping method with a delta-sigma modulator is commonly used to reduce this phase spur around the carrier [711]. Figure 2(a) shows a block diagram of the conventional frequency divider [12], where the program counter and the swallow counter have a considerable hardware complexity and signicant power consumption because of the clock switching at every cycle. In this paper, we propose a new frequency divider with the simple architecture shown in Fig. 2(b). The proposed frequency divider consists of a program counter and a digital comparator. The digital comparator replaces the function of the swallow counter. The program counter counts the

P output pulses of the dual-modulus divider. During S pulses, the output of the comparator is 1, which means the dual-modulus divider divides the VCO frequency by N+1. After S pulses, the comparator produces an output of 0. Then, the modulus of the dual-modulus divider is set to N. Therefore, the overall divide ratio is NP+S. The advantage of this frequency divider is a smaller switching current. Because the proposed divider has only one counter, its current switching at each clock period is smaller than for a conventional divider, and its layout area is smaller. We also propose a new delta-sigma modulator for low power consumption and small area.

1. The Conventional 3-stage MASH Deltasigma Modulator

A 1st-order delta-sigma modulator can be replaced with one accumulator. As shown in Fig. 3, the input and the output of the delta-sigma modulator are the same as the input and the carry output (y(k)) of the accumulator, and the quantization error is the residue of the accumulator [6, 7]. Figure 4 represents the 3-stage MASH structure, which can be made by cascading three accumulators. M is the integer part of the divider ratio, and K is the frequency word that selects the channel frequency. The fractional part of the divide ratio is decided by K, and the bit width (m) of accumulator, by

CMOS Delta-Sigma Frequency Synthesizer with a New Frequency Divider Soo-Hwan Kim et al.

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Fig. 6. Replica-biased circuit for CML.

Fig. 5. Proposed 3-stage MASH delta-sigma modulator.

K/2m . The whole divide ratio is M+K/2m . In the conventional delta-sigma modulator, there are many adders and dierentiators.

2. Proposed 3-stage MASH Delta-sigma Modulator Using a Modulus-mapping Circuit

The proposed 3-stage delta-sigma modulator adopting a modulus-mapping circuit is shown in Fig. 5. In our developed circuit, we replace the numerous adders and dierentiators with the new modulus-mapping circuit, which functions the same as the conventional delta-sigma modulator. The advantage of the proposed structure is the reduced power consumption and the minimized the hardware complexity of the 3-stage MASH delta-sigma modulator. The noise shaping function of the conventional MASH is fullled by dierentiating and adding the carry bits of each accumulator. The proposed structure with modulus mapping circuit, however, does not need any dierentiation and addition because the carry bits of the each accumulator are mapped into the appropriate modulus value directly. Since the dierentiators and adders are replaced with this single modulus-mapping circuit, the layout area and the power consumption are substantially reduced.

Fig. 7. Simulation of the proposed frequency divider (P=5, S=2).

III. CIRCUIT DESIGN AND SIMULATION

1. Frequency Divider

The frequency divider that deals with RF-band signals entails higher power consumption and is susceptible to noise. CML (current-mode logic) with a dierential pair and a replica-bias circuit enables the frequency divider

to operate at high frequency, and the output swing can be kept constant. A dual-modulus divider block and a DTC (divide-by-two circuit) are designed with the CML because they should handle gigahertz band signals with low switching noise. Since the PMOS load in the CML should operate in the linear region, the bias voltage of the PMOS load should be set in the linear region, regardless of the supply voltage variations. The replica bias circuit [13,18,19], shown in Fig. 6, produces BIASN and BIASP from VBGR (bandgap reference voltage). It continuously adjusts the PMOS loads of the CML in the linear region, and the output voltage swing is constant, regardless of the supply voltage and the temperature variations. Figure 7 presents the simulation result for the proposed frequency divider. The swallow counter consumes power at every clock cycle because it consists of D ipops. We replace the swallow counter with the simple digital comparator to reduce the power consumption in the proposed frequency divider. In this simulation, P=5, S=2, N=4, and the input frequency is 2 GHz. The divider ratio is 2(45+2) = 44. The period of the FDIV pulse corresponds to 44 periods of FVCO. The pin names are

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Journal of the Korean Physical Society, Vol. 41, No. 6, December 2002 Table 1. Divider ratio at each accumulator output. C X X X X X X 0 0 0 0 1 1 1 1 CX X 0 0 1 1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Mod cont. +0 +1 +0 +1 1 +0 +0 +1 2 1 +1 +2 1 +0

ACC1

ACC2

ACC3

Fig. 8. (a) Modulus-mapping circuit and (b) Comparison of the conventional layout size with the proposed layout size.

FVCO: Input signal to the frequency divider (VCO output), DTCO: Output signal divided by two from the VCO output, Dout: Dual-modulus output (CML level), CKP: Dual-modulus output (CMOS level), FDIV: Overow signal of the program counter (output signal from the frequency divider), MC: The signal aligned with dual-modulus output (CKP) at the falling edge. The current consumption of the proposed frequency divider is 460 uA, which is a 27 % reduction compared to a conventional circuit which uses current switching at every clock cycle.

Fig. 9. 3-stage delta-sigma modulator simulation.

2. 3-stage MASH Delta-sigma Modulator

Figure 5 shows the modulus-mapping circuit proposed in this paper to reduce the hardware complexity and power consumption according to the output of each accumulator. All adders and dierentiators in a conventional 3-stage MASH modulator are replaced with only one modulus-mapping circuit. To design the modulusmapping circuit, we should dene the modulus control value (6 bit) by using the output of each accumulator. The mapping table for the proposed modulus-mapping circuit is shown in Table 1. C, C-, and C0 represent the carry signals of each accumulator. Figure 8(a) and (b) show the proposed modulus-mapping circuit, which is synthesized from Table 1, and its layout area in comparison to the conventional one. A reduction of 44 % in the layout area and 18 Figure 9 shows the simulation results of the deltasigma modulator. In the simulation, the sequences that controlled the frequency divider were varied as 0, 0, 0, 3,

Fig. 10. Spiral inductor layout and its equivalent circuit.

Table 2. Optimized spiral inductor parameters. L R CS1 RS1 CS2 RS2 Q SRF (nH) () (fF) () (fF) () @1.8GHz (GHz) 2.39 7.53 229 72.9 188 101 3.70 9.67

1, 2, 3, 0, 0, 0, 0, 0, 3, 3, 2 at each clock. The sequence values were between 3 to +4. The value added with M modulated the frequency divide ratio.

3. VCO

CMOS Delta-Sigma Frequency Synthesizer with a New Frequency Divider Soo-Hwan Kim et al.

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Fig. 11. LC VCO schematic.

An inductor with a patterned grounded shield [5] and P+/N-well varactor diodes are used for better phase noise characteristics. We can achieve a 2.39 nH inductance with a Q factor of 3.7 in the simulation. Table 2 and Fig. 10 show the optimized inductor parameters and its equivalent spiral inductor model used in simulation [14,15]. These parameters are extracted at a frequency of 1.8 GHz. An LC VCO with a cross-coupled pair is shown in Fig. 11 [18]. The negative resistance composed of M1, M2, M3, and M4 provides stable oscillation. Figures 12(a) and (b) represent the measurement results of the phase noise performances of 110.27 dBc/Hz at a 600 kHz oset and 122.9 dBc/Hz at a 7.5 MHz oset. The relation between the input control voltage of the VCO and the oscillating frequency is shown in Fig. 13. The control voltage range is 0.62.5 V, and the VCO tuning range is 1.62.1 GHz. The VCO gain is 263 MHz/V with good linearity.

Fig. 12. VCO phase noise characteristic @ (a) a 600-kHz oset and (b) a 7.5-MHz oset.

4. Frequency Synthesizer Fig. 13. VCO. Voltage-frequency linear characteristic of the

The following parameters are used for the simulation of the whole fractional-N frequency synthesizer: The tracking process is shown in Fig. 14. After the PLL is in lock, a frequency step variation of 60 MHz can be obtained by changing the divider ratio from 45.375 to 46.875. The settling time is 2.8 s. The measurement result is shown in Fig. 15(a) and (b). When the input reference frequency is 30 MHz and the divide ratio is 62 (2(NP+S), N=4, P=7, S=3), which means that the frequency synthesizer operates as a integer division mode, the reference spur noise characteristic of the output signal is 94.6 dBc. When the divide ratio is set to 62.125 (K=1), the output signal

Fig. 14. Tracking Process (60-MHz step).

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Journal of the Korean Physical Society, Vol. 41, No. 6, December 2002

Fig. 16. Chip microphotograph.

posed chip has the fastest switching time with less power consumption.

IV. LAYOUT
Fig. 15. (a) Input reference spur characteristic and (b) fractional reference spur characteristic (K=1).

Table 3. Characteristics of the fractional-N frequency synthesizer. Items Supply voltage Reference frequency VCO tuning range VCO gain Measurement Results 2.5 V 10 % 30 MHz 1.62.1 GHz 263 MHz/V 110.27 dBc/Hz @ 600-kHz oset Phase noise 122.9 dBc/Hz @ 7.5-MHz oset Locking time 2.8 s @ 60 MHz frequency step (simulation result) Power dissipation 20.2 mW @ VDD = 2.5 V (w/o buer) Chip area 7601280 m Technology 0.25-m standard CMOS (1P5M)

Figure 16 is the chip microphotograph. The power supply in the analog blocks is separated from the digital blocks to avoid digital switching noise. The chip is fabricated in a 0.25 m standard CMOS process (1-poly, 5-metal) and occupies an active area of 7601280 m without the bonding pad.

V. CONCLUSION We have developed a 2-GHz fractional-N frequency synthesizer in a 0.25-m standard CMOS process (1poly, 5-metal). A new frequency divider and a modulusmapping circuit for lower power consumption and less chip area suitable for battery-operated systems are proposed, and a LC VCO and a 3-stage MASH delta-sigma modulator are used for low phase noise characteristics. The measurement results for the VCO phase noise are 110.27 dBc/Hz at a 600 kHz oset and 122.9 dBc/Hz at a 7.5 MHz oset, and the VCO gain is 263 MHz/V. The reference spur is 94.6 dBc with a 30-MHz input reference frequency and the fractional spur is 101.6 dBc. Compared with the latest published frequency synthesizers, the proposed chip has the fastest switching time (2.8 s) with less power consumption.

frequency is at 1.85375 GHz (62.12530 MHz), and the fractional spur is 101.6 dBc. In Fig. 15(b), the undesired spurs in the integer division (Fig. 15(a)) are removed by modulating the divide ratio in the fractional division. The main characteristics of the designed fractional-N synthesizer are summarized in Table 3, and in Table 4, the performances are compared with those of the latest published frequency synthesizers. The simulation results show that the pro-

ACKNOWLEDGMENTS

CMOS Delta-Sigma Frequency Synthesizer with a New Frequency Divider Soo-Hwan Kim et al. Table 4. Comparison with other frequency synthesizers. Max. Freq. 1 GHz 1.1 GHz 2.5 GHz 1.8 GHz 2.1 GHz Supply Current 5.6mA @ 3.3 V 10.8 mA @ 2.7 V 41 mA @ 3.3 V 35 mA @2V 8.1 mA @ 2.5 V

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Ref. 98 CICC [13] 00 JSSC [11] 00 ISSCC [16] 02 JSSC [17] This work

Technology 0.5 m CMOS 0.5 m CMOS 0.5 m CMOS 0.25 m CMOS 0.25 m CMOS

Architecture 3rd-order MASH 3rd-order 3-bit 3rd-order 3-bit 3rd-order MASH 3rd-order MASH

Locking Time 172 s 150 s @100 MHz 5 s @110 MHz 226 s @104 MHz 2.8 s @ 60 MHz

(: Frequency synthesizer with integrated VCO)

This research has been partially supported by the IDEC (IC Design Educational Center).

REFERENCES
[1] T. S. Aytur and B. Razavi, IEEE J. Solid-State Circ. 30, 1457 (1995). [2] M. Soyuer, Keith A. Jenkins, Joachim N. Burghart, Herschel A. Ainspan, Frank J. Canora, Sila Ponnapalli, John F. Ewen and William E. Pence, IEEE J. Solid-State Circ. 31, 268 (1995). [3] A. N. Karanicolas, IEEE J. Solid-State Circ. 31, 1939 (1996). [4] J. Craninckx and M. Steyaert, IEEE J. Solid-State Circ. 30, 1474 (1995). [5] C. P.Yue and S. S.Wong, IEEE J. Solid-State Circ. 33, 743 (1998). [6] T. A. D. Riley, M. A. Copeland and T. A. Kwasniewski, IEEE J. Solid-State Circ. 28, 553 (1993). [7] B. Miller and B. Conley, IEEE Trans. Instr. Meas. 40, 578 (1991). [8] M. H. Perrott, T. L. Tewksbury III and C. G. Sodini, IEEE J. Solid-State Circ. 32, 2048 (1997).

[9] N. M. Filiol, T. A. D. Riley, Calvin Plett and M. A. Copeland, IEEE J. Solid-State Circ. 33, 998 (1998). [10] B. H. Park and P. E. Allen, Proc. IEEE Custom Integrated Circ. Conf. (Santa Clara, May, 1998), 26.4.1. [11] W. Rhee, B. S. Song and A. Ali, IEEE J. Solid-State Circ. 35, 1453 (2000). [12] B. Razavi, RF Microelectronics (Prentice Hall PTR, NJ, 1998). [13] B. H. Park, Ph.D. thesis, Georgia Institute of Technology (1997). [14] N. M. Nguyen and R. G. Meyer, IEEE J. Solid-State Circ. 25, 1028 (1990). [15] J. Craninckx and M. Steyaert, IEEE J. Solid-State Circ. 32, 736 (1997). [16] S. Willingham, M. Perrot, B. Setterberg, A. Grzegorek and B. McFarland, ISSCC Dig. of Tech. Papers (San Francisco, Jan., 2000), p. 200. [17] Bram De Muer and Michel S. J. Steyaert, IEEE J. SolidState Circ. 37, 835 (2002). [18] Gun Sang Lee, Je Kwang Cho, Jae Shin Lee, Suki Kim and Nam Ki Min, J. Korean Phys. Soc. 39, 14 (2001). [19] Jae-Shin Lee, Woo-Kang Jin, Gun-Sang Lee, Suki Kim, Min-Ki Kim and Dong-Myung Choi, J. Korean Phys. Soc. 38, 167 (2001).