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Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info1
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This chapter introduces using DSP Builder for digital signal processing (DSP) designs on Altera FPGAs. It introduces the DSP Builder standard and advanced blocksets, and the Altera-provided DSP IP libraries.
3G wireless Voice over Internet protocol (VoIP) Multimedia systems Radar and satellite systems Medical systems Image-processing applications Consumer electronics.
Specialized DSP processors can implement many of these applications. Although these DSP processors are programmable through software, their hardware architecture is not flexible. Therefore, fixed hardware architecture such as bus performance bottlenecks, a fixed number of multiply accumulate (MAC) blocks, fixed memory, fixed hardware accelerator blocks, and fixed data widths limit DSP processors. The DSP processors fixed hardware architecture is not suitable for some applications that require customized DSP function implementations. FPGAs provide a reconfigurable solution for implementing DSP applications, higher DSP throughput, and more raw data processing power than DSP processors. You can reconfigure FPGAs in hardware, therefore they offer complete hardware customization while implementing various DSP applications. You can customize the architecture, bus structure, memory, hardware accelerator blocks, and the number of MAC blocks in an FPGA system.
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High-density FPGAs incorporate embedded silicon features that can implement complete systems inside an FPGA, creating a system on a programmable chip (SOPC) implementation. Embedded silicon features such as embedded memory, DSP blocks, and embedded processors are ideally suited for implementing DSP functions such as finite impulse response (FIR) filters, fast Fourier transforms (FFTs), correlators, equalizers, encoders, and decoders. The embedded DSP blocks also provide other functionality such as accumulation, addition and subtraction, and summation, which are common arithmetic operations in DSP functions. Altera FPGAs offer much more multiplier bandwidth than DSP processors, which only offer a limited number of multipliers. One determining factor of the overall DSP bandwidth is the multiplier bandwidth, therefore the overall DSP bandwidth of FPGAs can be much higher using FPGAs than with a DSP processors. Many DSP applications use external memory devices to manage large amounts of data processing. The embedded memory in FPGAs meets these requirements and also eliminates the need for external memory devices in some cases. Embedded processors in FPGAs provide overall system integration and flexibility while partitioning the system between hardware and software. You can implement the systems software components in the embedded processors and implement the hardware components in the FPGA's general logic resources. Altera devices provide a choice between embedded soft core processors and embedded hard core processors. You can implement soft core processors such as the Nios II embedded processor in FPGAs and add multiple system peripherals. The Nios II processor supports a user-determinable multi-master bus architecture that optimizes the bus bandwidth and removes potential bottlenecks found in DSP processors. You can use multimaster buses to define as many buses and as much performance as needed for a particular application. Off-the-shelf DSP processors make compromises between size and performance when they choose the number of data buses on the chip, potentially limiting performance. Soft embedded processors in FPGAs provide access to custom instructions such as the MUL instruction in Nios II processors that can perform a multiplication operation in two clock cycles using hardware multipliers. FPGA devices provide a flexible platform to accelerate performance-critical functions in hardware because of the configurability of the devices logic resources. DSP processors have predefined hardware accelerator blocks, but FPGAs can implement hardware accelerators for each application, allowing the best achievable performance from hardware acceleration. You can implement hardware accelerator blocks with parameterizable IP functions or from scratch using HDL. f Altera offers many IP cores for DSP design, for more information about these IP cores, refer to Chapter 2, Introducing DSP IP Cores. You can parameterize Altera DSP IP cores for the most efficient hardware implementation and to provide maximum flexibility. You can easily port the IP to new FPGA families, leading to higher performance and lower cost. The flexibility of programmable logic and soft IP cores allows you to quickly adapt your designs to new standards without waiting for long lead times usually associated with DSP processors.
Chapter 1: Introducing DSP Design Software Design Flow with DSP Processors
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Use DSP Processor Tools (Compiler, Assembler, Linker, and Debugger) to Implement Algorithm
You can use algorithm development tools such as MATLAB to optimize DSP algorithms and Simulink for system-level modeling. The algorithms and the system-level models are then implemented in C/C++ or assembly code with an integrated development environment that provides design, simulation, debug, and real-time verification tools. You can use standard C-based DSP libraries to shorten design cycles and derive the benefits of design re-use.
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Figure 12. DSP Builder General Design Flow for Altera FPGAs
Use MATLAB or Simulink to Design Algorithm
DSP Libraries
Build System
Develop Software
Build System
Configure FPGA
Configure FPGA
Configure FPGA
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DSP Builder shortens DSP design cycles by helping you create the hardware representation of a DSP design in an algorithm-friendly development environment. DSP Builder integrates the algorithm development, simulation, and verification capabilities of The MathWorks MATLAB and Simulink system-level design tools with the Altera Quartus II software and third-party synthesis and simulation tools. You can combine Simulink blocks with DSP Builder blocks and IP blocks to verify system level specifications and perform simulation (Figure 21). DSP Builder supports all Altera DSP IP cores.
Figure 21. DSP Builder Design Flow
Design in MATLAB or Simulink
MATLAB/ Simulink
DSP Builder
IP
DSP block
ModelSim
SOPC Builder
Cycle-accurate behavioral models Multiple clock domain management Control rich with backpressure support Access to specific hardware device features Hardware-in-the-loop (HIL) support enables FPGA hardware cosimulation Support for importing VHDL or Verilog HDL design entities
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Tabular and graphical state machine support Rapid prototyping using Altera DSP development boards SignalTap II logic analyzer debugging support Direct instantiation of DSP IP cores
The DSP Builder advanced blockset does not interface directly with the DSP IP cores but instead includes its own timing-driven IP blocks that can generate high performance FIR, CIC, NCO, and FFT models. The advanced blockset has the following features:
Specification driven design with automatic pipelining and folding High level synthesis technology High performance timing-driven IP models Multichannel designs with automatically vectorized inputs Automatic generation of memory-mapped interfaces Simulink fixed-point types Single system clock for the main datapath logic Feed-forward datapath with minimum control Portability across different device families High-level resource trade-offs such as hard versus soft multipliers
You can use both blocksets in subsystems of the same design when you want to combine features from each blockset. For example, when you want to combine an IP model from the advanced blockset with development board support or hardware-in-loop (HIL) from the standard blockset.
Standard Blockset
You can use blocks from the standard blockset to create a hardware implementation of a system modeled in Simulink in sampled time. DSP Builder contains bit- and cycle-accurate Simulink blockswhich cover basic operations such as arithmetic or storage functionsand takes advantage of key device features such as built-in PLLs, DSP blocks, and embedded memory. You can integrate complex functions by including IP cores in your DSP Builder model. You can also use the faster performance and richer instrumentation of hardware cosimulation by implementing parts of your design in an FPGA. The standard blockset supports imported HDL subsystems including HDL defined in a Quartus II project file. f For more information about the standard blockset, refer to Volume 2: DSP Builder Standard Blockset in the DSP Builder Handbook.
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Advanced Blockset
The DSP Builder advanced blockset consists of a number of Simulink libraries that allow you to implement DSP designs quickly and easily. The blockset is based on a high-level synthesis technology that optimizes the untimed netlist into low-level, pipelined hardware for the target FPGA device and clock rate. DSP Builder implements the hardware as VHDL with scripts that integrate with the Quartus II software and the ModelSim simulator. The combination of these features allows you to create a design without intimate device knowledge, which can run on a variety of FPGA families with different hardware architectures. After specifying the desired clock frequency, number of channels, and other top-level design constraints, the generated RTL is automatically pipelined to achieve timing closure. By analyzing the system-level constraints, DSP Builder also optimizes folding (time-division multiplexed (TDM) designs) to achieve optimum logic utilization, with no need for manual RTL editing. The synthesis technology also allows you to easily increase or decrease the number of channels. For example, in your FIR filter or digital up conversion signal chain, you can use a parameter file within the Simulink design. DSP Builder then adds the required TDM control logic and generates the updated RTL. The advanced blockset includes a library of basic control blocks and two component librariesModelIP and ModelPrim. These are useful in the following circumstances:
The ModelIP library consists of a set of multichannel, multirate cycle- accurate filters, mixers, and a numerically controlled oscillator (NCO) that allow you to quickly create designs for digital front end applications. Altera provides several implementation examples including up and down converters. The ModelPrim library allows you to create fast efficient designs captured in the behavioral domain rather than the implementation domain by combining zero latency primitive blocks. For example, you can use a delay block and DSP Builder decides how to implement that delay.
The advanced blockset is particularly suited for streaming algorithms characterized by continuous data streams and occasional control. For example, RF card designs that comprise long filter chains. f For more information about the advanced blockset, refer to Volume 3: DSP Builder Advanced Blockset in the DSP Builder Handbook.
Tool Integration
The DSP Builder standard and advanced blocksets are designed to operate with the Simulink, ModelSim software, Quartus II software, and Qsys.
Simulink
DSP Builder is interoperable with other Simulink blocksets. In particular, use the basic Simulink blockset to create interactive testbenches.
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The DSP Builder standard blockset uses signed integer, unsigned integer or signed fractional signal types and can be connected to other Simulink blocks using type casting Input and Output blocks. f For information about the internal signal types used by the standard blockset, refer to Volume 2: DSP Builder Standard Blockset in the DSP Builder Handbook. The VHDL model for standard blockset subsystems is generated when you compare the Simulink simulation results with the ModelSim simulator when you use the TestBench block. f For information about Simulink fixed point types, the signal processing blockset and the communications blockset, refer to the MATLAB Help. A VHDL model generates for subsystems with the advanced blockset when you run a Simulink simulation. There are many examples of using Simulink blocks in the tutorial and design examples. In particular, use Simulink scopes in the advanced blockset example to identify signals to add to the ModelSim Wave window for display as a digital or analog signal. f For information about the tutorials and design examples, refer to Design Examples in DSP Builder Standard Blockset Libraires section in volume 2 of the DSP Builder Handbook and the DSP Builder Advanced Blockset Libraires section in volume 3 of the DSP Builder Handbook.
ModelSim
You can run the ModelSim simulator from within a DSP Builder standard or advanced blockset design, if the ModelSim executable (vsim.exe) is in your path. Use the TestBench block to integrate between the DSP Builder standard blockset and the ModelSim simulator. When you click Compile against HDL, a VHDL testbench generates and a tb_<model name>.tcl script generates that you can use to load the testbench into the ModelSim simulator. You can optionally load the ModelSim GUI for interactive simulation. f For more information, refer to the description of the TestBench block in the DSP Builder Standard Blockset Libraires section in volume 2 of the DSP Builder Handbook.
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You can use any of the following generated scripts to integrate between the DSP Builder advanced blockset and the ModelSim simulator:
Control.do. This script, named after the control block (normally Control) compiles the entire design with RTL equivalents of the testbench structures, adds all relevant signals to the Wave window, and runs for the same period as the Simulink simulation. The script relies on some subordinate scripts that recursively compile library files, all the RTL files in the project, and adds the signals to the Wave window, before the simulation is started. Use these easy-to-follow scripts when building custom flows. To automatically load the design in the ModelSim simulator, click on the Run Modelsim block in the top-level model. f Only a subset of the Simulink blocks are translated into RTL that you can use for simulation in the ModelSim simulator. For a list of compatible blocks, refer to the Run ModelSim block descriptionin the DSP Builder Advanced Blockset Libraires section in volume 3 of the DSP Builder Handbook.
<block name>_atb.do. This script runs the automatic testbench flow for a block. It relies on reading some stimulus files at run time to verify a hardware block. The automatic testbench flow runs a rigorous test and returns a result whether or not the outputs match.
For more information, refer to the Comparison with RTL section in the DSP Builder Advanced Blockset Libraires section in volume 3 of the DSP Builder Handbook.
Quartus II Software
The standard blockset is tightly integrated with the Quartus II software using the Signal Compiler block. You can choose the device family and device, synthesize your design, run the Quartus II Fitter, and program your selected device. You can also enable the SignalTap II logic analyzer or export synthesizable model of your design. The advanced blockset allows you to build high-speed, high-performance DSP datapaths. In most production designs there is an RTL layer surrounding this datapath to perform interfacing to processors, high speed I/O, memories, and so on. To complete the design, use the DSP Builder standard blockset, Qsys, or RTL to assign board level components. The Quartus II software can then complete the synthesis and place and route process. You can automatically load a design into the Quartus II software by clicking on the Run Quartus II block in the top-level model.
Qsys
The DSP Builder standard blockset includes a library of Avalon Memory-Mapped (Avalon-MM) and Avalon Streaming (Avalon-ST) interface blocks. A Tcl script <model name>_add.tcl is created by Signal Compiler, which can add your design to a Quartus II project. Any design that includes the Avalon interface blocks is automatically available for connection to other Avalon components in Qsys.
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For an example of the standard blockset integration with Qsys, refer to the Using the Interface Library chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook. DSP Builder creates a memory-mapped interface and class.ptf file for each advanced blockset design. This file can expose the processor bus for connection in Qsys. A DSP Builder advanced blockset subsystem is available from the System Contents tab in Qsys after you add the path to the class.ptf file to the Qsys IP search path.
For an example of the advanced blockset integration with Qsys, refer to the DSP Builder Advanced Blockset User Guide section in volume 3 of the DSP Builder Handbook.
System Requirements
As DSP Builder integrates with the The MathWorks MATLAB and Simulink tools and with the Altera Quartus II software, ensure both tools are available on your workstation before you install DSP Builder. f For system requirements and installation instructions, refer to Altera Software Installation and Licensing. You should use the same version of the Quartus II software and DSP Builder. Table 31 lists the tool dependencies for DSP Builder.
Table 31. DSP Builder Tool Dependencies Tool DSP Builder The MathWorks (MATLAB and Simulink) (1), (2), (3)
Notes to Table 31:
(1) DSP Builder only supports 32-bit versions of The MathWorks release. (2) DSP Builder does not work with MATLAB in read-only mode. If your PC issues error messages while creating board components during the DSP Builder installation, reinstall MATLAB with the READ ONLY option unchecked. (3) The DSP Builder advanced blockset uses Simulink fixed-point types for all operations and requires licensed versions of Simulink Fixed Point. Altera also recommends the Simulink Signal Processing Blockset and Communications blocksets, which the design examples use.
Software Version 10.1 R2009a R2009b R2010a 10.0 R2008a R2008b R2009a 9.1 R2008a R2008b R2009a
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4. Read the Altera license agreement. Turn on I have read the license agreement and click Proceed to Final Step. 5. Follow the instructions on the download and installation page to download the executable and save it to your hard disk. 6. If you download the Linux version of DSP Builder, use the following command to untar the file:
tar xvf 90_dsp_builder_linux.tar
If you do not have Internet access, contact your local Altera representative to obtain the Altera Complete Design Suite DVD.
The Quartus II software The MATLAB and Simulink tools The ModelSim simulator
2. Click Run (Windows Start menu). 3. Type <path>\DSPBuilder-<version>.exe, where <path> is the location of the downloaded file. 4. Click OK. The DSP Builder <version> - InstallShield Wizard dialog box appears. 5. Follow the online instructions to install a new version. You are prompted for the locations of the Quartus II and MATLAB software you want to use with DSP Builder. You can also choose whether to install the standard, advanced, or both blocksets. 1 MATLAB is runs in a minimized window during the installation. The transcript may include a number of entity creation error messages, which you can ignore and all components initialize correctly.
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The Quartus II software The MATLAB and Simulink tools The ModelSim simulator If you have an existing version of DSP Builder, remove the existing dsp_builder and dspba directories before running the installation script.
2. Type <path>/install --setup_matlab, where <path> is the location of the downloaded files. 3. Follow the on-line instructions. The installer prompts you for the location of the Quartus II software you want to use with DSP Builder. The standard and advanced blocksets install by default when you use the Linux installation script. However, you can specify the option --dspb_only to install only the standard blockset or --dspba_only to install only the advanced blockset. You can also use the --auto option to install both blocksets using default locations without prompting for the location of the Quartus II software. 1 The MATLAB path, libraries and classpath are set up using scripts that write to your local matlab subdirectory.
Altera provides the gtar and gzip executables with the archive file in case there are compatibility issues with the default executables. Setting the MATLAB Path If you use the --setup_matlab option, the installer creates a startup.m script in $HOME/matlab. This script automatically sets the MATLAB path and classpath when you start MATLAB. Alternatively you can set the MATLAB path by clicking Set Path on the File menu in MATLAB and adding the following paths for the standard blockset:
<installation directory>/dsp_builder/bin <installation directory>/dsp_builder/bin/matlab <installation directory>/dsp_builder/bin/mdllibrary
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You can optionally add paths to each of the directories that contain example design models if you want to open them from your current working directory. Setting the Classpath The startup.m file that the installer creates also updates the static classpath to include the dspb_sblocks.jar file. Alternatively, you can copy classpath.txt from /toolbox/local/ in the MATLAB installation into a local directory, changing it to include <installation directory>/dsp_builder/bin/dspb_sblocks.jar, and then invoking MATLAB from this local directory. 1 You can check the classpath by running javaclasspath in MATLAB to confirm that the dspb_sblocks.jar file is on the static classpath. Setting LD_LIBRARY_PATH Set the LD_LIBRARY_PATH environment variable for the C++ shared libraries to work properly. If it is not set correctly, the following MATLAB error messages appear:
Invalid MEX-file ... .mexglx
If you set LD_LIBRARY_PATH globally it may affect other programs. Therefore set it either in a script that you use to start MATLAB or create a .matlab7rc.sh in your home directory. You must have the following paths:
<installation directory>/linux for the Quartus II software <installation directory>/dsp_builder/bin for the DSP Builder standard blockset <installation directory>/dspba/Blocksets/BaseBlocks/post2008a for the DSP Builder advanced blockset.
The matlab7rc.sh file has sections for each operating system. For 32-bit Linux, the relevant section is marked:
#-----------------------------------------------------------------;; glnx86) #------------------------------------------------------------------
If you add the required paths to LDPATH_SUFFIX, MATLAB adds them to the end of the LD_LIBRARY_PATH variable when it starts up. 1 You can check that the library path has been set correctly by using the following command in MATLAB:
getenv('LD_LIBRARY_PATH')
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After installing DSP Builder, the Altera DSP Builder standard blockset and the Altera DSP Builder advanced blockset libraries, which you specified, are available in the Simulink library browser in the MATLAB software.
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Previous Versions
A previous version of DSP Builder cannot coexist with a current version in the same version of MATLAB. However, you can register each version of DSP Builder with different versions of MATLAB. Refer to Using Multiple Versions of MATLAB on page 37. 1 Use DSP Builder with a matching version of the Quartus II software.
MATLAB Procedures
Table 31 on page 31 shows the which versions of MATLAB you can use with DSP Builder .
Standard Blockset
1. Open a command prompt and change directory to the standard blockset installation:
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2. Run the following command to register the DSP Builder blocksets with the required MATLAB version:
setupMatlabClassPath install <MATLAB Installation Path> <DSP Builder Installation Path>\dsp_builder
You must use quotation marks around the DSP Builder or MATLAB installation path, if the paths include spaces.
Advanced Blockset
1. Open MATLAB and change directory to the advanced blockset installation:
cd <DSP Builder Installation Path>dspba
2. Run the following command in the MATLAB command window to register the DSP Builder advanced blockset with the current MATLAB version:
alt_adv_dspb_install
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The Quartus II software The LeonardoSpectrum software The Synplify software The MATLAB and Simulink tools The ModelSim simulator The Precision RTL synthesis software
2. Open the DSP Builder license file in a text editor. The file contains one FEATURE line, spanning two lines. 3. Open your Quartus II license.dat file in a text editor. 4. Copy the FEATURE line from the DSP Builder license file and paste it into the Quartus II license file. 1 Do not delete any FEATURE lines from the Quartus II license file.
5. Save the Quartus II license file. 1 When using editors such as Microsoft Word or Notepad, ensure that the file does not have any extra extensions appended to it after you save (for example, license.dat.txt or license.dat.doc). Verify the file name at the system command prompt.
PLL period multiply and divide values must be integers The PLL output clock period is incorrect after update When upgrading a design with a PLL, extra clock blocks are created for each distinct sample time The PLL input clock frequency information is lost during the update process Clock blocks do not support rate change divider
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Chapter 4: Updating From Earlier Versions Limitations of the Update Model Utility
Table 41. Model Update Issues (Part 2 of 2) Issue Error assigning clock for Dual-Clock FIFO block Error assigning PLL clock for Multi-Rate DFF block Unnecessary clock specification for source blocks Action Under some circumstances - noted by the message No clock specified for {write/read} port, ... you may have to manually select clocks after upgrading designs containing the Dual-Clock FIFO block. When upgrading a multirate DFF block connected to a PLL clock, an error is issued of the form: Cannot update clock in block foo/Multi-Rate DFF. Original clock source: PLL CLOCK0. The blocks must be manually corrected to reference the PLL clock. In general, source blocks do not need to specify a clock domain, if it can be inferred from the blocks they are driving. However, the update path always specifies a clock if it is not the base clock. Your multi-clock design may be easier to maintain if, after upgrading, you manually turn off Specify Clock for source blocks especially constant, VCC and GND blocks wherever possible. These errors can usually be fixed by turning off Specify Clock on the constant block. If the block is fed into several clock domains, you also need to add a Tsamp block before each one.
Errors issued if a constant, GND or VCC block is driving a block with a different sample time
The BP block does not A warning is issued if your design includes a bus probe (BP) block which was set to display support sample time mode the sample time because this option is no longer supported. Phase selection has been standardized across all blocks The Multi Channel Display and Extract blocks are not supported HIL designs must be recompiled Changes to rounding method used for the MATLAB arrays initialize the LUT and RAM blocks Results in behavioral change when upgrading blocks that use phase selection.
These blocks are no longer supported and should be removed before running the update script. You can use the Avalon-ST Packet Format Converter block directly in place of these blocks. To prevent HDL being generated, insert Output blocks followed by Non-synthesizable Input blocks on the inputs to the Avalon-ST packet format converter block. For designs with Hardware in the Loop, you must recreate the Quartus II project and recompile the HIL revision after upgrading. The rounding method used when the data values specified by an initializing MATLAB array are not exactly expressed if the data type changes. For example, if you specify the data type as Unsigned Integer and the value as 1.9 in a pre-v7.1 design, this value was rounded up to 2; it is now rounded down to 1. You should the check the outputs from LUT or RAM blocks if an error is issued stating that the values cannot be exactly represented in the selected data format and choose revised initialization values that can be represented exactly if the outputs are not as expected. Altbus blocks used as black box inputs or outputs must be manually changed to HDL Input and HDL Output blocks and a HDL Entity block added to specify the HDL file and clock/reset ports. Rename any block containing a / character in its name.
Black box subsystem are not updated An error is issued for any block name which has a / character AltBus blocks within subsystems which function as input pins not updated correctly Device Programmer block is not supported The External RAM block is not updated
Move the input pins to the top level or replace them by Input blocks. (It is better to replace these AltBus blocks before upgrading to ensure that the clock signals are set correctly.)
Remove the Device Programmer block before running the update program. Use Signal Compiler or a HIL block to program the DSP development board. This block is outside the DSP Builder system and is not automatically updated. You must manually replace any pre-7.1 External RAM blocks in your designs with the latest version.
Chapter 4: Updating From Earlier Versions Updating the IP Cores in your Design
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This command automatically regenerates all the IP cores in the updated design, using the existing parameterizations.
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Chapter 4: Updating From Earlier Versions Updating the IP Cores in your Design
Additional Information
Revision History
The following table shows the revision history for this document.
Date December 2010 July 2010 Version 10.1 10.0 Updated MATLAB version support. First release. Changes Made
Typographic Conventions
The following table shows the typographic conventions that this document uses.
Visual Cue Bold Type with Initial Capital Letters bold type Meaning Indicates command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box. For GUI elements, capitalization matches the GUI. Indicates directory names, project names, disk drive names, file names, file name extensions, dialog box options, software utility names, and other GUI labels. For example, \qdesigns directory, d: drive, and chiptrip.gdf file. Indicates document titles. For example, AN 519: Stratix IV Design Guidelines. Indicates variables. For example, n + 1. Variable names are enclosed in angle brackets (< >). For example, <file name> and <project name>.pof file. Initial Capital Letters Indicates keyboard keys and menu names. For example, Delete key and the Options menu.
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Meaning Quotation marks indicate references to sections within a document and titles of Quartus II Help topics. For example, Typographic Conventions. Indicates signal, port, register, bit, block, and primitive names. For example, data1, tdi, and input. Active-low signals are denoted by suffix n. For example, resetn. Indicates command line commands and anything that must be typed exactly as it appears. For example, c:\qdesigns\tutorial\chiptrip.gdf. Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword SUBDESIGN), and logic function names (for example, TRI).
Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets indicate a list of items when the sequence of the items is not important. The hand points to information that requires special attention. A caution calls attention to a condition or possible situation that can damage or destroy the product or your work. A warning calls attention to a condition or possible situation that can cause you injury. The angled arrow instructs you to press Enter. The feet direct you to more information about a particular topic.
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Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Contents
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Bit Width Design Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Data Width Propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Tapped Delay Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Arithmetic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Frequency Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Single Clock Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Multiple Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Using Clock and Clock_Derived Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 Clock Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 Using the PLL Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Using Advanced PLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 Timing Semantics Between Simulink and HDL Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 Simulink Simulation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 HDL Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 Startup & Initial Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 DSP Builder Global Reset Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 Reference Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 Signal Compiler and TestBench Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 Design Flows for Synthesis, Compilation and Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 Hierarchical Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Goto and From Block Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 Create Black Box and HDL Import . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 Using a MATLAB Array or .hex File to Initialize a Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 Comparison Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 Adding Comments to Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 Adding Quartus II Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Displaying Port Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 Displaying the Pipeline Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 Updating HDL Import Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 Analyzing the Hardware Resource Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 Loading Additional ModelSim Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 Making Quartus II Assignments to Block Entity Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
MegaCore Functions Design Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 Simulink Files Associated with a MegaCore Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 Simulating MegaCore Functions That Have a Reset Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 Setting the Device Family for MegaCore Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
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Avalon-ST Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 Avalon-ST Packet Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 Avalon-ST Packet Format Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
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Troubleshooting Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Signal Compiler Cannot Checkout a Valid License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Verifying That Your DSP Builder Licensing Functions Properly . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Verifying That the LM_LICENSE_FILE Variable Is Set Correctly . . . . . . . . . . . . . . . . . . . . . . . . . 133 Verifying the Quartus II Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 If You Still Cannot Get a License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Loop Detected While Propagating Bit Widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 The MegaCore Functions Library Does Not Appear in Simulink . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 The Synthesis Flow Does Not Run Properly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Check the Software Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 DSP Development Board Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 SignalTap II Analysis Appears to Hang . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Error if Output Block Connected to an Altera Synthesis Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Warning if Input/Output Blocks Conflict with clock or aclr Ports . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Wiring the Asynchronous Clear Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Error Issues when a Design Includes Pre-v7.1 Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Creating an Input Terminator for Debugging a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 A Specified Path Cannot be Found or a File Name is Too Long . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Incorrect Interpretation of Number Format in Output from MegaCore Functions . . . . . . . . . . . . . 137 Simulation Mismatch For FIR Compiler MegaCore Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Simulation Mismatch After Changing Signals or Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Unexpected Exception Error when Generating Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 VHDL Entity Names Change if a Model is Modified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Algebraic Loop Causes Simulation to Fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Parameter Entry Problems in the DSP Block Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 DSP Builder System Not Detected in SOPC Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 MATLAB Runs Out of Java Virtual Machine Heap Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 ModelSim Fails to Invoke From DSP Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Unexpected End of File Error When Comparing Simulation Results . . . . . . . . . . . . . . . . . . . . . . . 1310
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Avalon-MM Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Avalon-MM Read FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Avalon-MM Write FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 Avalon-ST Packet Format Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 PFC Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 Packet Format Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 Packet Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 Multi-Packet Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 Avalon-ST Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 Avalon-ST Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
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Cyclone II EP2C70 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Cyclone III EP3C25 Starter Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Cyclone III EP3C120 DSP Board (LED/PB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Cyclone III EP3C120 DSP Board (7-Seg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1310 Cyclone III EP3C120 DSP Board (HSMC A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1310 Cyclone III EP3C120 DSP Board (HSMC B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1310 Stratix EP1S25 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1310 Stratix EP1S80 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1310 Stratix II EP2S60 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1311 Stratix II EP2S180 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1311 Stratix II EP2S90GX PCI Express Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1311 Stratix III EP3SL150 DSP Board (LED/PB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1311 Stratix III EP3SL150 DSP Board (7-Seg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1311 Stratix III EP3SL150 DSP Board (HSMC A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1311 Stratix III EP3SL150 DSP Board (HSMC B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1312 Combined Blockset Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1312
Additional Information
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info1
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The following table shows the revision dates for the sections in this volume.
Section DSP Builder Standard Blockset User Guide DSP Builder Standard Blockset Libraries Version 1.0 1.0 Date June 2010 June 2010 Part Number HB_DSPA_STD_UG-1.0 HB_DSPA_STD_LIB-1.0
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Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Revision History
The following table shows the revision history for this section.
Date June 2010 Version 1.0 First published. Changes Made
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Release Information
Table 11 provides information about this release of DSP Builder.
Table 11. DSP Builder Release Information Item Version Release Date Ordering Code Description 10.0 June 2010 IPT-DSPBUILDER
Arria GX Arria II GX Cyclone Cyclone II Cyclone III. Stratix Stratix GX Stratix II Stratix II GX Stratix III Stratix IV
Memory Options
A number of the blocks in the Storage library allow you to choose the required memory block type. In general, DSP Builder lists all supported memory block types as options although some may not be available for all device families. Table 12 on page 11 shows the device families that support each memory block type.
Table 12. Supported Memory Block Types Memory Block Type M144K M9K MLAB Device Family Stratix IV, Stratix III, Arria II GX Stratix IV, Stratix III, Cyclone III, Arria II GX Stratix IV, Stratix III, Arria II GX
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Table 12. Supported Memory Block Types Memory Block Type M-RAM M4K M512 Device Family Stratix II GX, Stratix II, Stratix GX, Stratix, Arria GX Stratix II GX, Stratix II, Stratix GX, Stratix, Arria GX, Cyclone II, Cyclone Stratix II GX, Stratix II, Stratix GX, Stratix, Arria GX
For more information about each memory block type, refer to the Quartus II Help.
Features
DSP Builder standard blockset supports the following features:
Links The MathWorks MATLAB (Signal Processing ToolBox and Filter Design Toolbox) and Simulink software with the Altera Quartus II software. Generates VHDL testbench and controls Quartus II compilation. Provides a variety of fixed-point arithmetic and logical operators for use with the Simulink software. Enables rapid prototyping using Altera DSP development boards. Supports the SignalTap II logic analyzeran embedded signal analyzer that probes signals from the Altera device on the DSP board and imports the data into the MATLAB workspace to ease visual analysis. Allows HDL import of VHDL or Verilog HDL design entities and HDL defined in a Quartus II project file. Supports hardware-in-the loop (HIL) to enable FPGA hardware accelerated cosimulation with Simulink. Supports Avalon Memory-Mapped (Avalon-MM) interfaces including user configurable blocks, which you can use to build custom logic that works with the Nios II processor and other SOPC Builder designs. Supports Avalon Streaming (Avalon-ST) interfaces including an Packet Format Converter block and configurable Avalon-ST sink and Avalon-ST source blocks. Allows you to instance Altera DSP MegaCore functions in a DSP Builder design model. Supports tabular and graphical state machine editing.
For information about new features and errata in this release, refer to the DSP Builder Release Notes and Errata.
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General Description
Digital signal processing (DSP) system design in Altera programmable logic devices (PLDs) requires both high-level algorithm and hardware description language (HDL) development tools. The Altera DSP Builder integrates these tools by combining the algorithm development, simulation, and verification capabilities of The MathWorks MATLAB and Simulink system-level design tools with VHDL and Verilog HDL design flows, including the Altera Quartus II software. DSP Builder shortens DSP design cycles by helping you create the hardware representation of a DSP design in an algorithm-friendly development environment. You can combine existing MATLAB functions and Simulink blocks with Altera DSP Builder blocks and Altera intellectual property (IP) MegaCore functions to link system-level design and implementation with DSP algorithm development. In this way, DSP Builder allows system, algorithm, and hardware designers to share a common development platform. The DSP Builder Signal Compiler block reads Simulink Model Files (.mdl) that contain other DSP Builder blocks and MegaCore functions. Signal Compiler then generates the VHDL files and Tcl scripts for synthesis, hardware implementation, and simulation.
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2. Getting Started
Design Flow
When using DSP Builder, you start by creating a Simulink design model in the MathWorks software. After you have created your model, you can compile directly in the Quartus II software, output VHDL files for synthesis and Quartus II compilation, or generate files for VHDL simulation. DSP Builder generates VHDL and does not generate Verilog HDL. However, after you have created a Quartus II project, you can use the quartus_map command in the Quartus II software to run a simulation netlist flow that generates files for Verilog HDL simulation. f For information about this flow, refer to the Quartus II help.
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The design flow involves the following steps: 1. Use the MathWorks software to create a model with a combination of Simulink and DSP Builder blocks. 1 Separate The DSP Builder blocks in your design from the Simulink blocks by Input and Output blocks from the DSP Builder IO and Bus library.
2. Include a Clock block from the DSP Builder AltLab library to specify the base clock for your design, which must have a period greater than 1ps but less than 2.1 ms. 1 If no base clock exists in your design, DSP Builder creates a default clock with a 20ns real-world period and a Simulink sample time of 1. You can derive additional clocks from the base clock by adding Clock_Derived blocks.
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3. Set a discrete (no continuous states) solver in Simulink. Choose a Fixed-step solver type if you are using a single clock domain or a Variable-step type if you use multiple clock domains. To set the solver options, click Configuration Parameters on the Simulation menu to open the Configuration Parameters dialog box and select the Solver page (Figure 22).
Figure 22. Configuration Parameters for Simulation
For detailed information about solver options, refer to the description of the Solver Pane in the Simulink Help.
4. Simulate your model in Simulink using a Scope block to monitor the results. 5. Run Signal Compiler to setup RTL simulation and synthesis. 6. Perform RTL simulation. DSP Builder supports an automated flow for the ModelSim software (using the TestBench block). You can also use the generated VHDL for manual simulation in other simulation tools. 7. Use the output files generated by the DSP Builder Signal Compiler block to perform RTL synthesis. Alternatively, you can synthesize the VHDL files manually using other synthesis tools. 8. Compile your design in the Quartus II software. 9. Download to a hardware development board and test. For an automated design flow, the Signal Compiler block generates VHDL and Tcl scripts for synthesis in the Quartus II software. The Tcl scripts let you perform synthesis and compilation automatically in the MATLAB and Simulink environment. You can synthesize and simulate the output files in other software tools without the Tcl scripts. In addition, the Testbench block generates a testbench and supporting files for VHDL simulation.
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For information about controlling the DSP Builder design flow using Signal Compiler, refer to Design Flows for Synthesis, Compilation and Simulation on page 319. For more information about the blocks in the DSP Builder blockset, refer to the DSP Builder Reference Manual.
You are using a PC running Windows XP. You are familiar with the MATLAB, Simulink, Quartus II, and ModelSim software and the software is installed on your PC in the default locations. You have basic knowledge of the Simulink software. f For information about using the Simulink software, refer to the Simulink Help.
You can use the singen.mdl model file in <DSP Builder install path>\DesignExamples\Tutorials\GettingStartedSinMdl or you can create your own amplitude modulation model. To create the amplitude modulation model, follow these instructions.
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5. Click OK. 1 For information about how you can calculate the frequency., refer to the equation in Frequency Design Rules on page 38.
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3. Drag and drop the Input block from the Simulink Library Browser into your model. Position the block to the right of the Sine Wave block. If you are unsure how to position the blocks or draw connection lines, refer to the completed design (Figure 27 on page 214). 1 You can use the Up, Down, Right, and Left arrow keys to adjust the position of a block.
4. Click the text under the block icon in your model. Delete the text Input and type the text SinIn to change the name of the block instance. 5. Double-click the SinIn block in your model to display the Block Parameters dialog box. 6. Set the SinIn block parameters (Table 22).
Table 22. Parameters for the SinIn Block Parameter Bus Type [number of bits].[] Specify Clock Value Signed Integer 16 Off
7. Click OK. 8. Draw a connection line from the right side of the Sine Wave block to the left side of the SinIn block by holding down the left mouse button and dragging the cursor between the blocks. 1 Alternatively, you can select a block, hold down the Ctrl key and click the destination block to automatically make a connection between the two blocks.
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5. Click the Optional Ports tab and set the parameters (Table 23).
Table 23. Parameters for the Delay Block. Parameter Clock Phase Selection Use Enable Port Use Synchronous Clear port Value 01 Off Off
6. Click OK. 7. Draw a connection line from the right side of the SinIn block to the left side of the Delay block.
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Table 24. Parameters for the SinDelay Block Parameter Bus Type [number of bits].[] External Type Value Signed Integer 16 Inferred
6. Click OK. 7. Repeat steps 4 to 6 for the SinIn2 block setting the parameters (Table 25).
Table 25. Parameters for the SinIn2 Block Parameter Bus Type [number of bits].[] External Type Value Signed Integer 16 Inferred
8. Draw a connection line from the right side of the Delay block to the left side of the SinDelay block.
5. Click OK. 6. Draw a connection line from the bottom left of the Mux block to the right side of the SinDelay block. 7. Draw a connection line from the top left of the Mux block to the line between the SinIn2 block. 8. Draw a connection line from the SinIn2 block to the line between the SinIn and Delay blocks.
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1. Select the Simulink Sources library in the Simulink Library Browser. 2. Drag and drop a Random Number block into your model, positioning it underneath the Sine Wave block. 3. Double-click the Random Number block in your model to display the Block Parameters dialog box. 4. Set the Random Number block parameters (Table 27).
Table 27. Parameters for the Random number Block Parameter Mean Variance Initial seed Sample time Interpret vector parameters as 1-D Value 0 1 0 25e9 On
The dialog box options change to display only the relevant options when you select a new bus type.
6. Click OK. 7. Draw a connection line from the right side of the Random Bitstream block to the left side of the Noise block.
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5. Click OK. 6. Draw a connection line from the right side of the Noise block to the top left side of the Bus Builder block.
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Table 210. Parameters for the Product Block Parameter Bus Type Number of Pipeline Stages Value Inferred 0
The bit width parameters are set automatically when you select Inferred bus type. The parameters in the Optional Ports and Settings tab of this dialog box can be left with their default values.
5. Click OK. 6. Draw a connection line from the top left of the Product block to the line between the Delay and SinDelay blocks.
6. Click OK. 7. Double-click the StreamBit block to display the Block Parameters dialog box (Figure 26).
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9. Draw connection lines from the right side of the Product block to the left side of the StreamMod block, and from the right side of the Bus Builder block to the left side of the StreamBit block.
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5. Click OK. 6. Close the Scope. 7. Make connections to connect the complete your design as follows: a. From the right side of the Mux block to the top left side of the Scope block. b. From the right side of the StreamMod block to the middle left side of the Scope block. c. From the right side of the StreamBit block to the bottom left of the Scope block. d. From the bottom left of the Product block to the line between the Bus Builder block and the StreamBit block. Figure 27 shows the required connections.
Figure 27. Amplitude Modulation Design Example
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A clock block is required to set a Simulink sample time that matches the sample time specified on the Sine Wave and Random Bitstream blocks. If no base clock exists in your design, a default clock with a 20ns real-world period and a Simulink sample time of 1 is automatically created.
For detailed information about solver options, refer to the description of the Solver Pane in the Simulink Help.
3. Click OK.
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4. Start simulation by clicking Start on the Simulation menu. 5. Double-click the Scope block to view the simulation results. 6. Click the Autoscale icon (binoculars) to auto-scale the waveforms. Figure 29 shows the scaled waveforms.
Figure 29. Scope Simulation Results
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5. When the compilation completes successfully, click OK. 6. Click Save on the File menu to save your model.
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6. Turn on the Launch GUI option. This option causes the ModelSim GUI to launch when you invoke the ModelSim simulation. 7. Click Generate HDL to generate a VDHL-based testbench from your model. 8. Click Run Simulink to generate Simulink simulation results for the testbench. 9. Click Run ModelSim to load your design into ModelSim. Your design simulates with the output displaying in the ModelSim Wave window. The testbench initializes all your design registers with a pulse on the aclr input signal. 10. All waveforms initially show using digital format in the ModelSim Wave window. Change the format of the sinin, sindelay and streammod signals to analog. 1 In ModelSim 6.4a, you can right-click to display the popup menu, point to Format and click on Analog (Automatic). The user interface commands may be different in other versions of ModelSim.
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11. Click Zoom Full on the right button pop-up menu in the ModelSim Wave window. The simulation results display as an analog waveform (Figure 213).
Figure 213. Analog Display
The introductory DSP Builder tutorial is complete. The next section shows how you can add a DSP Builder design to a new or existing Quartus II project. Subsequent chapters in this user guide provide examples that illustrate some of the additional design features supported by DSP Builder.
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3. Specify the name of the project. For example, NewProject and the name of the top-level design entity for the project. 1 The name of the top-level design entity typically has the same name as the project.
4. Click Next to display the Add Files page. There are no files to add for this tutorial. 5. Click Next to display the Family & Device Settings page and check that the required device family is selected. This should normally be the same device family as specified for Signal Compiler in Compiling the Design on page 216. 6. Click Finish to close the wizard and create the new project. 1 When you specify a directory that does not already exist, a message asks if the specified directory should be created. Click Yes to create the directory.
An example instantiation is added to your Quartus II project. 3. Click the Files tab in the Quartus II software. 4. Right-click singen.mdl and click Select Set as Top-Level Entity. 5. Compile the Quartus II design by clicking Start Compilation on the Processing menu. 1 You can copy the component declaration from the example file for your own code.
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DSP Builder Naming Conventions Using a MATLAB Variable Fixed-Point Notation Bit Width Design Rule Frequency Design Rules Timing Semantics Between Simulink and HDL Simulation Signal Compiler and TestBench Blocks Hierarchical Design Goto and From Block Support Create Black Box and HDL Import Using a MATLAB Array or .hex File to Initialize a Block Comparison Utility Adding Comments to Blocks Adding Quartus II Constraints Displaying Port Data Types Displaying the Pipeline Depth Updating HDL Import Blocks Analyzing the Hardware Resource Usage Loading Additional ModelSim Commands Making Quartus II Assignments to Block Entity Names
VHDL is not case sensitive. For example, the input port MyInput and MYINPUT is the same VHDL entity. Avoid using VHDL keywords for DSP Builder port names. Do not use illegal characters. VHDL identifier names can contain only a - z, 0 - 9, and underscore (_) characters.
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Begin all port names with a letter (a - z). VHDL does not allow identifiers to begin with non-alphabetic characters or end with an underscore. Do not use two underscores in succession (__) in port names because it is illegal in VHDL.
White spaces in the names for the blocks, components, and signals are converted to an underscore when DSP Builder converts the Simulink model file (.mdl) into VHDL.
Fixed-Point Notation
Figure 31 describes the fixed-point notation that I/O formats use in the DSP Builder block descriptions.
Table 31. Fixed-Point Notation Description Signed binary: [L].[R] where: fractional (SBF) representation; a fractional number Signed binary; integer (INT) Unsigned binary; integer (UINT) [L] where: Notation [L] is the number of bits to the left of the binary point and the MSB is the sign bit [R] is the number of bits to the right of the binary point [L] is the number of bits of the signed bus and the MSB is the sign bit [L] is the number of bits of the unsigned bus A Simulink signed binary signal A[L] maps to STD_LOGIC_VECTOR({L - 1} DOWNTO 0) A Simulink unsigned binary signal A[L] maps to STD_LOGIC_VECTOR({L - 1} DOWNTO 0) Simulink-to-HDL Translation (1), (2) A Simulink SBF signal A[L].[R] maps in VHDL to STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0)
[L] where:
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Simulink-to-HDL Translation (1), (2) A Simulink single bit integer signal maps to STD_LOGIC
Figure 31 graphically compares the signed binary fractional, signed binary, and unsigned binary number formats.
Figure 31. Number Format Comparison
[number of bits].[]represents the number of bits to the left of the binary point including the sign bit.
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[].[number of bits]represents the number of bits to the right of the binary point.
In VHDL, DSP Builder types the signals as STD_LOGIC_VECTOR. For example, DSP Builder represents the 4-bit binary number 1101 as: Simulink VHDL This signed integer is interpreted as 3 This signed STD_LOGIC_VECTOR is interpreted as 3
If you change the location of the binary point to 11.01, that is, two bits on the left side of the binary point and two bits on the right side, DSP Builder represents the numbers as: Simulink VHDL This signed fraction is interpreted as 0.75 This signed STD_LOGIC_VECTOR is interpreted as 3
From a system-level analysis point of view, multiplying a number by 0.75 or 3 is very different, especially when looking at the bit width growth. In the first case, the multiplier output bus grows on the most significant bit (MSB), in the second case, the multiplier output bus grows on the least significant bit (LSB). In both cases, the binary numbers are identical. However, the location of the binary point affects how a simulator formats the representation of the signal. For complex systems, you can adjust the binary point location to define the signal range and the area of interest. f For more information about number systems, refer to AN 83: Binary Numbering Systems.
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The fir3tapsub.mdl design is a 3-tap finite impulse response (FIR) filter and has the following attributes:
The input data signal is an 8-bit signed integer bus The output data signal is a 20-bit signed integer bus Three Delay blocks build the tapped delay line The coefficient values are {1.0000, -5.0000, 1.0000}, a Gain block performs the coefficient multiplication
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Arithmetic Operation
Figure 35 shows the arithmetic section of the filter, that computes the output yout:
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yout k =
x k i c i
i=0
where c[i] are the coefficients and x[k - i] are the data.
Figure 35. 3-Tap FIR Filter Arithmetic Operation in Quartus II Version RTL Viewer
This design requires three multipliers and one parallel adder. The arithmetic operations increase the bus width in the following ways:
Multiplying a b in SBF format (where l is left and r is right) is equal to: [la].[ra] [lb].[rb] The bus width of the resulting signal is: ([la] + [lb]).([ra] + [rb])
Adding a + b + c in SBF format (where l is left and r is right) is equal to: [la].[ra] + [lb].[rb] + [lc].[rc] The bus width of the resulting signal is: (max([la], [lb], [lc]) + 2).(max([ra], [rb], [rc]))
The parallel adder has three input buses of 14, 16, and 14 bits. To perform this addition in binary, DSP Builder automatically sign extends the 14-bit busses to 16 bits. The output bit width of the parallel adder is 18 bits, which covers the full resolution.
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The following options can change the internal bit width resolution and therefore change the size of the hardware required to perform the function that Simulink describes:
Change the bit width of the input data. Change the bit width of the output data. The VHDL synthesis tool removes any unused logic. Insert a Bus Conversion block to change the internal signal bit width.
Figure 36 shows how you can use Bus Conversion blocks to control internal bit widths.
Figure 36. 3-Tap Filter with BusConversion to Control Bit Widths
In Figure 36, the output of the Gain block has 4 bits removed. Port data type display is enabled in this example and shows that the inputs to the Delay blocks are of type INT_8 but the outputs from the Bus Conversion blocks are of type INT_6. 1 You can also achieve bus conversion by inserting an AltBus, Round, or Saturate block. The RTL view illustrates the effect of this truncation. The parallel adder required has a smaller bit width and the synthesis tool reduces the size of the multiplier to have a 9-bit output (Figure 37).
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Figure 37. 3-Tap Filter with BusConversion to Control Bit Widths in Quartus II RTL Viewer
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Do not use DSP Builder combinational blocks for rate transitions to ensure that the behavior of the DSP Builder Simulink model is identical to the generated RTL representation. Figure 38 illustrates an incorrect use of the DSP Builder Logical Bit Operator (NOT) block.
Figure 38. Example of Incorrect Usage: Mixed Sampling Rate on a NOT Block
Two DSP Builder blocks can operate with two different sampling periods. However for most DSP Builder blocks, the sampling period of each input port and each output port must be identical. Although this rule applies most of the DSP Builder blocks, there are some exceptions such as the Dual-Clock FIFO block where the sampling period of the read input port is expected to be different than the sampling period of the write input port.
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For a datapath using mixed clock domains, the design may require additional register decoupling around the register that is between the domains. This requirement is especially true when the source data rate is higher than the destination register, in other words, when the data of a register is toggling at the higher rate than the registers clock pin (Figure 39).
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The Clock block defines the base clock domain, and Clock_Derived blocks define other clock domains. DSP Builder specifies sample times in terms of the base clock sample time. If there is no Clock block, DSP Builder uses a default base clock, with a Simulink sample time of 1, and a hardware clock period of 20 s. This feature is available across all device families that DSP Builder supports. If no Clock block is present, the design uses a default clock pin named clock and a default active-low reset pin named aclr. The Signal Compiler block assigns a clock buffer and a dedicated clock-tree to clock-signal input pin automatically to maintain minimum clock skew. If your design contains more Clock and Clock_Derived blocks than there are clock buffers available, non dedicated routing resources route the clock signals.
Clock Assignment
DSP Builder identifies registered DSP Builder blocks such as the Delay block and implicitly connects the clock, clock enable, and reset signals in the VHDL design for synthesis. When your design does not contain a Clock block, Clock_Derived block, or PLL block, all the registered DSP Builder block clock pins connect to a single clock domain (signal clock in VHDL). Define clock domains by the clock source blocks: the Clock block, the Clock_Derived block and the PLL block. The Clock block defines the base clock domain. You can specify its Simulink sample time and hardware clock period directly. If there is no Clock block, there is a default base clock with a Simulink sample time of 1. You can use the Clock_Derived block to define clock domains in terms of the base clock. DSP Builder specifies the sample time of a derived clock as a multiple and divisor of the base clock sample time. The PLL block maps to a hardware PLL. You can use it to define multiple clock domains with sample times specified in terms of the PLL input clock. Use the PLL input clock either as the base clock or a derived clock. Each clock domain has an associated reset pin. The Clock block and each of the Clock_Derived blocks have their own reset pin, the name of which is in the block's parameter dialog box. The clock domains of the PLL block share the reset pin of the PLL block's input clock. When your design contains clock source blocks, DSP Builder implicitly connects the clock pins of all the registered blocks to the appropriate clock pin or PLL output. DSP Builder also connects the reset pins of the registered blocks to the top-level reset port for the block's clock domain. DSP Builder blocks fall into the following clocking categories:
Combinational blocksthe output always changes at the same sample time slot as the input. Registered blocksthe output changes after a variable number of sample time slots.
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The Magnitude block translates as a combinational signal in VHDL. DSP Builder does not add clock pins to this function. Figure 312 illustrates the behavior of a registered DSP block. In the VHDL netlist, DSP Builder adds clock pin inputs to this function. The Delay block, with the Clock Phase Selection parameter equal to 100, is converted into a VHDL shift register with a decimation of three and an initial value of zero.
Figure 312. Delay Block: Registered Behavior
For feedback circuitry (the output of a block fed back into the input of a block), a registered block must be in the feedback loop. Otherwise, DSP Builder creates an unresolved combinational loop (Figure 313).
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Use the PLL block and assign different sampling periods on registered DSP Builder blocks to design multirate designs. Alternatively, use a single clock domain with clock enable and the following design rules to design multirate designs without the DSP Builder PLL block:
The fastest sample rate is an integer multiple of the slower sample rates. The Clock Phase Selection field in the Block Parameters dialog box specifies the values for the Delay block. The Clock Phase Selection box accepts a binary pattern string to describe the clock phase selection. DSP Builder processes each digit or bit of this string sequentially on every cycle of the fastest clock. When a bit is equal to one, DSP Builder enables the block; when a bit is equal to zero, DSP Builder disables the block. Table 32 shows some examples of typical clock phase selections.
Table 32. Clock Phase Selection Example Phase 1 10 0100 Description The Delay block is always enabled and captures all data passing through the block (sampled at the rate 1). The Delay block is enabled every other phase and every other data (sampled at the rate 1) passes through. The Delay block is enabled on the 2nd phase out of 4 and only the 2nd data out of 4 (sampled at the rate 1) passes through. The data on phases 1, 3, and 4 does not pass through the Delay block.
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Figure 314 compares the scopes for the Delay block operating at a one quarter rate on the 1000 and 0100 phases, respectively.
Figure 314. 1000 as Opposed to 0100 Phase Delay
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Figure 316 shows the clock setting configuration for the PLL block in the design example MultipleClockDelay.mdl. Output clock PLL_clk0 is set to 800 ns, and output clock PLL_clk1 is set to 100 ns.
Figure 316. PLL Setting
Datapath A (green in Figure 315) operates on output clock PLL_clk0 and datapath B (red in Figure 315) operates on output clock PLL_clk1. Specify these clocks by setting the Specify Clock option and enter the clock name in the Block Parameter dialog box for each input block. In this design, the Sample time parameters for the Sine Wave a block and Sine Wave b block are set explicitly to 1e-006 and 1e-007, so that DSP Builder provides data to the input blocks at the rate at which they sample.
Create a new Quartus II project and use the MegaWizard Plug-In to configure the ALTPLL block. Add the DSP Builder .mdl file to the Quartus II project as a source file. Create a top-level design that instantiates your ALTPLL variation and your DSP Builder design.
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Chapter 3: Design Rules and Procedures Timing Semantics Between Simulink and HDL Simulation
Chapter 3: Design Rules and Procedures Timing Semantics Between Simulink and HDL Simulation
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In addition, when targeting a development board, the Block Parameters dialog box for the DSP Board configuration block typically includes a Global Reset Pin selection box where you can choose from a list of pins that correspond to the DIP and push-button switches. The reset logic polarity can be either active-high or active-low. When you select active-low, the value of the reset signal in Simulink simulation is still 0 for inactive and 1 for active. However, DSP Builder inserts a NOT gate on the input pin in the generated hardware. The value of the reset signal in simulation is therefore the value as it exists across the internal design, rather then the value at the input pin. Quartus II synthesis interprets this reset as an asynchronous reset, and uses an input of the logic element look-up table to instantiate the function. The HDL simulates correctly in this case because the testbench produces the reset input as required.
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Chapter 3: Design Rules and Procedures Timing Semantics Between Simulink and HDL Simulation
This timing is not true when crossing clock domains. For example, Figure 318 shows the timing delays in a design with a derived clock that has half the base clock period. In general, DSP Builder is not cycle-accurate when crossing clock domains.
Figure 318. Multiple-Clock Timing Relationships
Chapter 3: Design Rules and Procedures Signal Compiler and TestBench Blocks
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Automatic flowallows you to control the entire design process in the MATLAB or Simulink environment with the Signal Compiler block. With this flow, your design compiles inside a temporary Quartus II project. The results of the synthesis and compilation display in the Signal Compiler Messages box. You can also use the automatic flow to download your design into supported development boards. Manual flowyou can also add the .mdl file to an existing Quartus II project using the <model name>_add.tcl script. This script is generated whenever the Signal Compiler or TestBench block is run. You can use the script to add the .mdl file and any imported HDL to your project. You can then instantiate your design in HDL. Simulation flowif the ModelSim executable (vsim.exe) is on your path, you can use the TestBench block to compile your design for ModelSim simulation. You can then automatically compare the Simulink and ModelSim simulation results.
For an example that uses the Signal Compiler blocker, refer to page 214 of the Getting Started. f For information about the parameters for the Signal Compiler and TestBench blocks, refer to the AltLab Library chapter of the DSP Builder Reference Manual.
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Hierarchical Design
DSP Builder supports hierarchical design using the Simulink Subsystem block. DSP Builder preserves the hierarchy structure in a VHDL design and each hierarchical level in a Simulink model file (.mdl) translates into one VHDL file. For example, Figure 319 illustrates a hierarchy for a design fir3tap.mdl, which implements two FIR filters.
Figure 319. Hierarchical Design Example
For information about naming the Subsystem block instances, refer to DSP Builder Naming Conventions on page 31.
Chapter 3: Design Rules and Procedures Goto and From Block Support
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Use the Goto blocks ([ReadAddr], [WriteAddr], and [WriteEna] with the From blocks ([ReadAddr], [WriteAddr], and [WriteEna], which connect to the dual-port RAM blocks.
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Chapter 3: Design Rules and Procedures Create Black Box and HDL Import
Comparison Utility
DSP Builder provides a simple utility that runs simulation comparison between Simulink and ModelSim from the command line:
alt_dspbuilder_verifymodel('modelname.mdl', 'logfile.txt')r
A testbench GUI displays messages as DSP Builder performs the comparison. The command returns true (1) or false (0) according to whether the simulation results match and the output is recorded in the specified log file. f For more information about running a comparison between Simulink and ModelSim, refer to Performing RTL Simulation in Chapter 2.
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DSP Builder includes the comment text next to the instantiation of the block in the generated HDL.
For detailed information about Quartus II assignments, refer to the Quartus II Settings File Reference Manual.
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For more information about the DSP Builder internal signal types, refer to Fixed-Point Notation on page 32.
Chapter 3: Design Rules and Procedures Analyzing the Hardware Resource Usage
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You can use the alt_dspbuilder_refresh_hdlimport command to update these blocks. This command checks that the referenced HDL files (or Quartus II project) exists. If it finds the references, the HDL Import dialog box opens and a compilation is automatically invokes to regenerate the Simulink model. If it finds neither, but there is an existing simulation netlist, it uses this netlist for simulation. To run the command, follow these steps: 1. Start the MATLAB or Simulink software. 2. Open a Simulink model that contains imported HDL. 3. Run the command by typing the following at the MATLAB prompt: alt_dspbuilder_refresh_hdlimport r You can optionally select a HDL Import block to run the command on only the selected subsystem.
The Resource Usage dialog box updates to show a detailed report of the resources that each of the blocks require in your model that generate hardware.
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Chapter 3: Design Rules and Procedures Analyzing the Hardware Resource Usage
For example, Figure 324 shows the hardware resources that the Product block requires in the amplitude modulation example.
Figure 324. Resource Usage Dialog Box
The information depends on the selected device family. Refer to the device documentation for more information.
You can also click the Timing tab and click Highlight path to highlight the critical paths on your design. 1 When the source and destination in the dialog box are the same and a single block is highlights, the critical path is due to the internal function or a feedback loop. For a more complex example, the entire critical path through your design may highlight.
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Changing the parameterization of the block causes the entity name to change. If you want to make an assignment to a block in the Quartus II project, and for the assignment to remain when the block parameters change, you can use regular expressions in the assignments. For example, you may want to make a Preserve Registers assignment to the Delay blocks in Figure 325 to prevent them from merging.
Figure 325. Entity Name Assignment Example
Using the Quartus II Assignment Editor and Node Finder tools, you can identify the names of the registers and make the assignments to them. For example, if your model is my_model, the names may be:
my_model_GN:auto_inst|alt_dspbuilder_delay_GNLVAGVO3B:Delay|alt_dsp builder_SDelay:Delay1i|DelayLine my_model_GN:auto_inst|alt_dspbuilder_delay_GNLVAGVO3B:Delay1|alt_ds pbuilder_SDelay:Delay1i|DelayLine
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Chapter 3: Design Rules and Procedures Making Quartus II Assignments to Block Entity Names
These assignments prevent merging of the registers. If you change the length of the delay, the assignments are no longer valid. However, you can edit the To field of the assignment and use a regular expression that is still valid if the entity name changes due to a parameter change: Replace the eight alphanumeric characters following the GN in the block entity name with .{8}, which is a regular expression that matches any eight characters. The targets of the assignments then become:
my_model_GN:auto_inst|alt_dspbuilder_delay_GN.{8}:Delay|alt_dspbuil der_SDelay:Delay1i|DelayLine my_model_GN:auto_inst|alt_dspbuilder_delay_GN.{8}:Delay1|alt_dspbui lder_SDelay:Delay1i|DelayLine
If you want the assignment to apply to the whole block, not just the specific nodes, you can use the following code:
my_model_GN:auto_inst|alt_dspbuilder_delay_GN.{8}:Delay my_model_GN:auto_inst|alt_dspbuilder_delay_GN.{8}:Delay1
This type of assignment can be useful for a complicated block that contains many registers when you want the assignment to apply to all of the registers.
Altera provides a number of parameterizable intellectual property (IP) MegaCore functions that you can integrate into the Simulink model of your DSP Builder designs. 1 The OpenCore Plus evaluation feature allows you to download and evaluate these MegaCore functions in hardware and simulation prior to licensing. Blocks represent these MegaCore functions in the MegaCore Functions library of the Altera DSP Builder Blockset in the Simulink Library Browser. You must parameterize and generate these MegaCore functions after you add one of these blocks to your model. f Refer to MegaCore Function Design Example on page 43 for an example of the design flow using these MegaCore functions.
The process of building the MegaCore function blocks may take several minutes. Do not close MATLAB before the process completes. Expect and ignore any messages of the form Cannot find the declaration of element 'entity'. when installing a new MegaCore library. Running this command, creates a MegaCore Functions subfolder below the Altera DSP Builder Blockset in the Simulink Library Browser. In this folder, there is a blue block with a version name for each of the installed MegaCore functions.
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4. Browse to the directory in which you want to save the file. This directory becomes your working directory. This tutorial creates and uses the working directory <DSP Builder install path>\DesignExamples\Tutorials\MegaCore 5. Type the file name into the File name box. This tutorial uses the name mc_example.mdl. 6. Click Save.
3. Drag and drop a blue versioned fir_compiler_v9.0 block into your model (Figure 42).
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4. Rename the block to my_fir_compiler. To rename the block, click the default name (the text outside of the block itself) and edit the text. Naming conventions are described in DSP Builder Naming Conventions on page 31.
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1. Add two Sine Wave blocks (from the Simulink Sources library). 1 DSP Builder automatically gives the second block a unique name.
2. Use the Block Parameters dialog box to set the parameters for the Sine Wave block (Table 41).
Table 41. Parameters for the Sine Wave Blocks Value Parameter Sine type Time Amplitude Bias Samples per period Number of offset examples Sample time Interpret vector parameters as 1-D Sine Wave Sample based Use simulation time 64 0 200 0 1 On Sine Wave1 Sample based Use simulation time 64 0 7 0 1 On
3. Repeat Step 2 for the Sine Wave1 block. 4. Connect the outputs from the Sine Wave and Sine Wave1 blocks to an Add block (from the Simulink Math Operations library). 5. Add an Input block (from the IO & Bus library in the Altera DSP Builder Blockset) and connect it between the Add block and the ast_sink_data pin on the my_fir_compiler block. 6. Use the Block Parameters dialog box to set the parameters (Table 42).
Table 42. Parameters for the Input Block Parameter Bus Type [number of bits].[] Specify Clock Value Signed Integer 8 Off
7. Add a Constant block (from the IO & Bus library) and connect this block to both the ast_sink_valid and ast_source_ready pins on the my_fir_compiler block. 8. Add another Constant block (from the IO & Bus library) and connect this block to the ast_sink_error pin on the my_fir_compiler block. 9. Use the Block Parameters dialog box to set the parameters for the Constant block (Table 43).
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Table 43. Parameters for the Constant Blocks Value Parameter Constant Value Bus Type [Number of Bits].[] Rounding Mode Saturation Mode Specify Clock Constant 1 Single Bit Truncate Wrap Off Constant1 0 Signed Integer 2 Truncate Wrap Off
10. Repeat Step 9 for the Constant1 block. 11. Add a Single Pulse block (from the Gate & Control library in the Altera DSP Builder Blockset) and connect it to the reset_n pin on the my_fir_compiler block. 12. Use the Block Parameters dialog box to set the parameters (Table 44).
Table 44. Parameters for the Single Pulse Block Parameter Signal Generation Type Delay Specify Clock Value Step Up 50 Off
13. Add an Output block (from the IO & Bus library in the Altera DSP Builder Blockset) to your design and connect it to the ast_source_data pin on the my_fir_compiler block. 14. Use the Block Parameters dialog box to set the parameters (Table 45 on page 47).
Table 45. Parameters for the Output Block Parameter Bus Type [number of bits].[] External Type Value Signed Integer 18 Inferred
15. Add a Scope block (from the Simulink Sinks library). Use the Scope Parameters dialog box to configure the Scope block as a 2-input scope. 16. Connect the Scope block to the Input and Output blocks to monitor the source noise data and the filtered output. Figure 44 shows how your model looks.
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2. Select the Solver page and set the parameters (Table 46).
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Table 46. Configuration Parameters for the singen Model Parameter Start time Stop time Type Solver Value 0.0 5000 Fixed-step discrete (no continuous states)
For detailed information about solver options, refer to the description of the Solver Pane in the Simulink Help.
3. Click OK. 4. On the Simulation menu in the simulink model, click Start. The scope output shows the effect of the low-pass filter in the bottom window (Figure 46).
Figure 46. Simulation Output
Check that the FIR filter block behaves as you expect and filters high-frequency data as a low-pass filter. 1 You may need to use the Autoscale command in the Scope display to view the complete waveforms.
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4. Click Compile. 5. When the compilation has completed successfully, click OK.
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4. Ensure that Enable Test Bench generation is on. 5. Click the Advanced Tab (Figure 49).
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6. Turn on the Launch GUI option to launch the ModelSim GUI if you invoke ModelSim simulation. 7. Click Generate HDL to generate a VDHL-based testbench from your model. 8. Click Run Simulink to generate Simulink simulation results for the testbench. 9. Click Run ModelSim to simulate your design in ModelSim. Your design loads into ModelSim and simulates with the Wave window displaying the output. 1 All waveforms initially show using digital format in the ModelSim Wave window.
10. Right-click the input signal in the ModelSim Wave window and click Properties in the pop-up menu to display the Wave Properties dialog box. Click the Format tab and change the format to Analog with height 75 and Scale 0.25. 11. Repeat Step 10 for the output signal in the ModelSim Wave window and use the Wave Properties dialog box to change the format to Analog with height 75 and scale 0.001.
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12. Click Zoom Full on the right button right button pop-up menu in the ModelSim Wave window. The ModelSim simulator now displays the input and output waveforms in analog format (Figure 410).
Figure 410. Generated HDL for mc_example Simulated in ModelSim Simulator
1. Click Compare Results in the Testbench Generator dialog box to compare the simulink results with the ModelSim-generated results. The message Exact Match indicates that the results are identical. 2. Click OK to close the Testbench Generator dialog box.
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DSP Builder needs the following specific files to simulate a MegaCore function variation:
If your MegaCore function variation is my_function, and generates in VHDL, your design variation is in a my_function.vhd file in your design directory. If your design is my_design, the simulation information is in a DSPBuilder_my_design_import/my_function.vo.simdb file.
You must simulate an initial reset cycle (with the step input) to replicate hardware behavior. As in hardware, this reset cycle must be sufficiently long to propagate through the core, which may be 50 clock cycles or more for some MegaCore functions such as the FIR Compiler. Additional adjustment of the reset cycles may be necessary when a MegaCore function receives data from other MegaCore functions, to ensure that the blocks leave the reset state in the correct order and DSP Builder delays them by the appropriate number of cycles.
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The CIC MegaCore function uses a MegaWizard user interface. This interface always inherits the device family setting from the Signal Compiler block. If there is no Signal Compiler block in your design, DSP Builder uses the Stratix device family by default. MegaCore functions that use IP Toolbench allow you to modify the device family setting in the IP Toolbench interface. 1 The FFT, FIR Compiler, NCO, Reed Solomon Compiler, and Viterbi Compiler MegaCore functions use IP Toolbench. If you change the device family in Signal Compiler, you must check that any IP Toolbench MegaCore functions have the correct device family set to ensure that the simulation models and generated hardware are consistent.
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5. Using HIL
Adding the HIL block to your Simulink model allows you to cosimulate a Quartus II software design with a physical FPGA board implementing a portion of that design. You define the contents and function of the FPGA by creating and compiling a Quartus II project. A simple JTAG interface between Simulink and the FPGA board links the two. The main benefits of using the HIL block are faster simulation and richer instrumentation. The Quartus II project you embed in an FPGA runs faster than a software-only simulation. To further increase simulation speed, the HIL block offers frame and burst modes of data transfer that are significantly faster than single-step mode when you use it with suitable designs. The HIL block also makes available to the hardware a large Simulink library of sinks and sources, such as channel models and spectrum analyzers, which can give you greater control and observability. This chapter explains the HIL block design flow, walks through an example using the HIL block, and discusses the optional burst and frame data transfer modes.
3. Specify parameters for the HIL block, including the following options:
The Quartus II project to define its functionality The clock and reset pins The reset active level The input and output pin characteristics The use of single-step versus burst and frame mode
4. Compile the HIL block to create a programming object file (.pof) for hardware cosimulation.
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5. Scan for JTAG cables and hardware devices connected to the local host or any remotely enabled hosts. 6. Program the board that contains your target FPGA. 7. Simulate the combined software and hardware system in Simulink. 1 When using a HIL block in a Simulink model, set a fixed-step, single tasking solver.
HIL Requirements
The HIL block has the following requirements:
An FPGA board with a JTAG interface (Stratix, Stratix II, Stratix III, Cyclone, Cyclone II, or Cyclone III device). A valid Quartus II project that contains a single clock domain from Simulink. DSP Builder creates an internal Quartus II project when you run Signal Compiler. A JTAG download cable (for example, a ByteBlasterMV, ByteBlaster II, ByteBlaster, MasterBlaster, or USB-Blaster cable). A maximum of one HIL block for each JTAG download cable.
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Imaging edge detection Export example Fast Fourier Transform (FFT) Frequency sweep
This section shows the frequency sweep design. 1 This tutorial uses the Stratix II hardware device on an Altera Stratix II EP2S60 DSP Development Board. However, you can also use any other supported device and development board. To create a frequency sweep design, follow these steps: 1. Run MATLAB, and open the model FreqSweep.mdl in the <DSP Builder install path>\DesignExamples\Tutorials\HIL\FreqSweep directory. Figure 52 shows the model.
Figure 52. Frequency Sweep Model
2. Double-click the Signal Compiler block. In the dialog box that appears (Figure 53 on page 54), click Compile. This action creates a Quartus II project, FreqSweep.qpf, compiles your model for synthesis, and runs the Quartus II Fitter. Progress is indicated by status messages and a scrolling bar at the bottom of the dialog box.
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3. Review the Messages, then click OK to close the Signal Compiler dialog box. 4. Replace the internal functions of the frequency sweep model with an HIL block. Open the model FreqSweep_HIL.mdl from the FreqSweep directory (step 1). Figure 54 shows this model, with the HIL block in place.
Figure 54. Frequency Sweep Design Model Using the HIL Block
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5. Double-click the frequency sweep HIL block to display the Hardware in the loop dialog box. 6. Select the Quartus II project by browsing into the FreqSweep_dspbuilder directory to locate the FreqSweep.qpf file. 1 The full path to this file is visible in the dialog box when you select this file.
7. Select Clock from the list of available clock pins. 1 HIL does not support multiple clock domains and only the specified signal is the HIL clock signal. The HIL treats any other clocks in your design as input signals.
8. Select aclr from the list of available reset pins. 9. Identify the signed ports:
Select the Input port and click Unsigned. Select each output port (OutputCordic and OutputFilter) and click Signed.
10. Select the reset level to be Active_High. 11. Select the mode of operation by turning off Burst Mode. 12. Click Next page. to display the second page of the Hardware in the loop dialog box. 13. Specify a value for the FPGA device and click Compile with Quartus II to compile the HIL design. 1 If no output writes to the MATLAB command window, check that the original Quartus II project is up-to-date and compiles with he same version of the Quartus II software that compiles your Simulink model.
14. Click Scan Jtag to find available cables and hardware devices in the chain. 15. Select the JTAG download cable that references the required FPGA device and click Configure FPGA to program the FPGA on the board. 16. Click Close.
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17. Simulate your design in Simulink. Figure 55 shows the scope display from the finished design.
Figure 55. Scope Output from the FrequencySweep Model with HIL Block
A latency is introduced on the output signals of the HIL block making feedback loop difficult outside the FPGA device.
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When you set this option, you can specify the required number of data packets as the Burst length. The HIL block sends data to the hardware in bursts of the size you specify. 1 DSP Builder determines the size of the packet by the larger of the total input data width or the total output data width. If the packet size multiplied by the Burst length exceeds the preset data array, DSP Builder sets the Burst length to 1. In the HIL model (C++), DSP Builder defines an array for storing the input and output data to the HIL as 0x800000 byte in size. When the data record size (max of total input bits and output bits) / 8 burst length 2 (for both input and output) exceeds this number, DSP Builder resets the burst length to 1.
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Simulation using burst mode works the same as single clock mode, but DSP Builder introduces a latency of the specific packet size on the output signals of the HIL blocks. As a consequence, feedback-loops may not work properly unless you enclose them in the HIL block, and some intervention may be necessary when comparing or visualizing HIL simulation results. The HIL block uses software buffers to send and receive from the hardware, so you can change these buffer sizes without recompiling the HIL function.
The HIL block works with the concept of blocks of data (frames). DSP Builder provides the data frames at regular intervals. There is one input synchronization and one output synchronization signal available. The latency between the input synchronization and output synchronization signals is constant.
In frame mode, the HIL block monitors the input synchronization and output synchronization signals and increases the output delay to align the output data frames with the input data frames. For example, if the burst length is 1024 and the latency 3, the delay is 1027 (1024 + 3) without frame mode or 2048 (aligned to the next frame) with frame mode on. The burst packet size in frame mode must be a multiple of the frame packet interval. For example, if packets arrive every 100 clocks, you can use a frame burst size of N 100 clocks (N positive integer). Figure 57 illustrates a DSP Builder design with a FFT MegaCore function configured for the Stratix II target device family, with a transform length of 64 points, data precision of 16 bits, and twiddle precision of 16 bits.
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Figure 57. DSP Builder Design Using the FFT MegaCore Function
Figure 58 on page 59 shows the FFT design with a HIL block (and the parameters from Figure 56 on page 57).
Figure 58. Using the FFT Design With an HIL Block
The FFT MegaCore function respectively uses the Avalon-ST interface signals sink_eop and source_valid in the HIL block as the input synchronization and output synchronization signals. f Refer to the FFT MegaCore Function User Guide for additional information about the input and output port signal timing.
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This chapter describes how to set up and run the SignalTap II logic analyzer. In this chapter, you analyze three internal nodes in a simple switch controller design named switch_control.mdl. This design flow works for any of the Altera development boards that DSP Builder supports. f For detailed information about the supported development boards, refer to the Boards Library chapter in the DSP Builder Standard Blockset Libraries section in volume 2 of the DSP Builder Handbook. In this design, an LED on the DSP development board turns on or off depending on the state of user-controlled switches and the value of the incrementer. The design consists of an incrementer function feeding a comparator, and four switches that feed into two AND gates. The comparator and AND gate outputs feed an OR gate, which feeds an LED on the DSP development board. The SignalTap II logic analyzer captures the signal activity at the output of the two AND gates and the incrementer of the design loads into the Altera device on the development board. The logic analyzer retrieves the values and displays them in the MATLAB work space. f For more information about using the SignalTap II logic analyzer with the Quartus II software, refer to the Quartus II Help or to Volume 3 of the Quartus II Handbook. A SignalTap II Logic Analyzer block in DSP Builder includes the following characteristics:
Has a simple, easy-to-use interface Analyzes signals in the top-level design file Uses a single clock source Captures data around a trigger point. 88% of the data is pre-trigger and 12% of the data is post-trigger
Alternatively, you can use the Quartus II software to instantiate of the SignalTap II logic analyzer in your design. The Quartus II software supports additional features, such as using multiple clock domains, and adjusting the percentage of data captured around the trigger point.
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4. Choose one of the JTAG cable ports in the Signal Compiler dialog box or the SignalTap II Logic Analyzer dialog box. 5. Using Signal Compiler, synthesize your model, perform compilation in the Quartus II software, and download your design into the DSP development board (starter or professional). 6. Specify the required trigger conditions in the SignalTap II Logic Analyzer block. f For details of the SignalTap II Logic Analyzer and SignalTap II Node blocks, refer to the descriptions of these blocks in the AltLab Library chapter in the DSP Builder Standard Blockset Libraries section in volume 2 of the DSP Builder Handbook.
SignalTap II Nodes
A node represents a wire carrying a signal that travels between different logical components of a design file. The SignalTap II logic analyzer can capture signals from any internal device node in a design file, including I/O pins. The SignalTap II logic analyzer can analyze up to 128 internal nodes or I/O elements. As more it capture more signals, it uses more logic elements (LEs) or embedded system blocks (ESBs). Before capturing signals, assign each node to analyze to a SignalTap II logic analyzer input channel. To assign a node to an input channel, you must connect it to a SignalTap II Node block.
Dont care Low High Rising edge Falling edge Either edge
The SignalTap II logic analyzer triggers when it detects the trigger pattern on the input signals.
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You can start from the design in the original_design directory. Alternatively, you can use the design in the completed_walkthrough directory and go directly to Turning On the SignalTap II Option in Signal Compiler on page 66.
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1. Select the Boards library from the Altera DSP Builder Blockset folder in the Simulink library browser. 2. Open the CycloneIIEP2C35 folder. Drag and drop the Cyclone II EP2C35 DSP Development Board configuration block into your model. 3. Drag and drop the SW2 and SW3 blocks close to the AND_Gate2 block in your model. Connect these switch blocks to the AND_Gate2 inputs. 4. Drag and drop the SW4 and SW5 blocks close to the AND_Gate1 block in your model. Connect these switch blocks to the AND_Gate1 inputs. 1 You can rotate the SW5 block to make the connection easier by right-clicking the block and clicking Rotate Block on the Format menu.
5. Drag and drop the LED0 block close to the OR_Gate block in your model. Connect this block to the OR_Gate output. 6. Select the Simulink Sources library. Drag and drop a Pulse Generator block near to the SW2 and SW3 blocks and connect it to these blocks. 7. Drag and drop another Pulse Generator block near the SW4 and SW5 blocks and connect it to these blocks. Figure 63 shows your model.
Figure 63. Switch Control Example with Board, Pulse Generator and Terminator Blocks
8. Use the Block Parameters dialog box to set the parameters (Table 61) for both pulse generator blocks.
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Table 61. Parameters for the Pulse Generator Blocks Parameter Pulse type Time Amplitude Period Pulse Width Phase delay Interpret vector parameters as 1-D Value Time based Use Simulation time 1 2 50 0 On
9. Select the Simulink Sinks library. Drag and drop a Terminator block near to the OR_Gate block and connect it to this block.
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2. Click the text under the block icon in your model and change the block instance name by deleting the text and typing the new text firstandout. 3. Add a SignalTap II Node block between the AND_Gate2 block and the OR_Gate block and name it secondandout. 4. Add a SignalTap II Node block between the Eightbit Counter block and the Comparator block and name it cntout. 5. Click Save on the File menu.
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3. Select a depth of 128 for the SignalTap II sample buffer (that is, the number of samples stored for each input signal) in the SignalTap II depth list. 4. Verify that the Use Base Clock option is on. 5. Click the Simple tab and verify that the Use Board Block to Specify Device option is on. 6. Click the Compile button. When the conversion is complete, information messages in the dialog box display the memory allocated during processing. 1 You must compile your design before you open the SignalTap II Analyzer block because the block relies on data files that create during compilation.
7. Click Scan Jtag and select the appropriate download cable and device (for example, USB-Blaster cable and EP2C35 device). 8. Click Program to download your design to the development board. 9. Click OK.
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3. Press switch SW4 on the DSP development board to trigger the SignalTap II logic analyzer. 1 If you press and hold switch SW2 or SW3 while pressing switch SW4, the trigger condition is not met and acquisition does not occur.
4. Click OK in the SignalTap II Logic Analyzer dialog box when you finish. DSP Builder interprets the captured data as unsigned values and displays them in MATLAB plots. It stores the values in MATLAB .mat files in the working directory. Figure 65 shows the MATLAB plot for the SignalTap II node firstandout.
Figure 65. MATLAB Plot for SignalTap II Node firstandout
Figure 66 shows the MATLAB plot for the SignalTap II node secondandout.
Figure 66. MATLAB Plot for SignalTap II Node secondandout
Figure 67 shows the MATLAB plot for the SignalTap II node cntout.
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For more information about the SignalTap II Logic Analyzer block, refer to the SignalTap II Logic Analyzer block description in the AltLab Library chapter in the DSP Builder Standard Blockset Libraries section in volume 2 of the DSP Builder Handbook.
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This chapter describes how to use the Avalon-MM blocks in the Interfaces library to create a design that functions as a custom peripheral to SOPC Builder. SOPC Builder is a system development tool for creating systems that can contain processors, peripherals, and memories. SOPC Builder automates the task of integrating hardware components into a larger system. To integrate a DSP Builder design into your SOPC Builder system, your peripheral must meet the Avalon-MM interface or Avalon-ST interface specification and qualify as a SOPC Builder-ready component. The Interfaces library supports peripherals that use the Avalon-MM and Avalon-ST interface specifications. 1 The correct version of MATLAB with DSP Builder must be available on your system path to integrate DSP Builder .mdl files in SOPC Builder.
Avalon-MM Interface
The Avalon Interface Specifications provide peripheral designers with a basis for describing the address-based read and write interfaces on master (for example, a microprocessor or DMA controller) and slave peripherals (for example, a memory, UART, or timer). The Avalon-MM Master and Avalon-MM Slave blocks in DSP Builder provide a seamless flow for creating a DSP Builder block as a custom peripheral and integrating the block into your SOPC Builder system. These blocks provide you the following benefits:
Automates the process of specifying Avalon-MM ports that are compatible with the Avalon-MM bus Supports multiple Avalon-MM master and Avalon-MM slave instantiations Saves time spent hand coding glue logic that connects Avalon-MM ports to DSP blocks
For more information about SOPC Builder, refer to the Quartus II Handbook Volume 4: SOPC Builder; for more information about the Avalon-MM Interface, refer to the Avalon Interface Specifications.
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clock address read readdata write writedata byteenable readyfordata dataavailable endofpacket readdatavalid waitrequest beginbursttransfer burst count irq begintransfer chipselect
For more information about these signals, refer to the DSP Builder Standard Blockset Libraries section in volume 2 of the DSP Builder Handbook.
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Figure 71 shows a block that describes an Avalon-MM slave interface where all the Avalon-MM signals are enabled.
Figure 71. Avalon-MM Slave Block Signals
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Each of the input and output ports of the block correspond to the input and output ports of the pin or bus that Figure 71 shows between the ports. Inputs to the DSP Builder core display as right pointing bus or pins; outputs from the core display as left pointing pins or busses. You can use the opposite end of any pins to provide pass-through test data from the Simulink domain.
clock waitrequest address read readdata write writedata byteenable endofpacket readdatavalid flush burstcount irq irqnumber
For more information about these signals, refer to the DSP Builder Standard Blockset Libraries section in volume 2 of the DSP Builder Handbook. Figure 72 on page 75 shows a block that describes an Avalon-MM master interface where all the Avalon-MM signals are enabled.
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Wrapped Blocks
The Avalon-MM Master and Avalon-MM Slave interface blocks allow you to generate a SOPC Builder component in DSP Builder, but they do little to mask the complexities of the interface. The Avalon-MM read and write FIFO blocks in the Interfaces library provide a higher level of abstraction. You can implement a typical DSP core that handles data in a streaming manner, with the signals Data, Valid, and Ready. To provide a high level view, DSP Builder provides you with configurable Avalon-MM Write FIFO and Avalon-MM Read FIFO blocks for you to map Avalon-MM interface signals to this protocol.
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Figure 73 shows an example system with Avalon-MM Write FIFO and Avalon-MM Read FIFO blocks.
Figure 73. Example System with Avalon-MM Write FIFO and Avalon-MM Read FIFO Blocks
TestData (input). Connect this port to a Simulink block that provides simulation data to the Avalon-MM Write FIFO. The data passes to the DataOut port one cycle after the Ready input port asserts. Stall (input). Connect this port to a Simulink block. It simulates stall conditions of the Avalon-MM bus and hence underflow to the SOPC Builder component. For any simulation cycle where Stall asserts, the Avalon-MM Write Test Converter caches the test data and releases in order, one sample per clock, when stall is de-asserted. Ready (input). Connect this port to a DSP Builder block. It indicates that the downstream hardware is ready for data. DataOut (output). Connect this port to a DSP Builder block that corresponds to the oldest unsent data sample received on the TestData port. DataValid (output). Connect this port to a DSP Builder block and assert whenever DataOut corresponds to real data.
Double-click on an Avalon-MM Write FIFO block to open the Block Parameters dialog box so that you can set parameters for the data type, data width and FIFO depth. 1 To open the hierarchy below the Avalon-MM Write FIFO block, right-click the block and click Look Under Mask on the pop-up menu. You can use this design as a template to design new functionality (for example, when you use an Avalon-MM address input to split incoming streams).
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The Avalon-MM Write Test Converter block handles caching and conversion of Simulink or MATLAB data into accesses over the Avalon-MM interface. You can use this block to test the functionality of your design. The Avalon-MM Write Test Converter is simulation only and does not synthesize to HDL.
Stall (input). Connect this port to a Simulink block. It simulates stall conditions of the Avalon-MM bus and hence backpressure to the SOPC Builder component. For any simulation cycle where Stall asserts, no Avalon-MM reads take place and the internal FIFO buffer fills. When full, the Ready output is de-asserted so that you lose no data. Data (input). Connect this port to a DSP Builder block and to outgoing data from the user design. DataValid (input). Connect this port to a DSP Builder block and assert whenever the signal on the Data port corresponds to real data. TestDataOut (output). Connect this port to a Simulink block that corresponds to data received over the Avalon-MM bus. TestDataValid (output). Connect this port to a Simulink block and assert whenever TestDataOut corresponds to real data. Ready (output). When asserted, indicates that the block is ready to receive data.
Double-clicking on an Avalon-MM Write FIFO block opens the Block Parameters dialog box that you can use to set parameters for the data type, data width and FIFO depth. You can open the hierarchy below the Avalon-MM Read FIFO block by right-clicking on the block and choosing Look Under Mask from the pop-up menu. Figure 75 shows the internal content of an Avalon-MM Read FIFO.
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Chapter 7: Using the Interfaces Library Avalon-MM Interface Blocks Design Example
The Avalon-MM Read Data Converter block handles caching and conversion of Simulink or MATLAB data into accesses over the Avalon-MM interface. You can use this block to test the functionality of your design. The Avalon-MM Read Data Converter is simulation only and does not synthesize to HDL.
Chapter 7: Using the Interfaces Library Avalon-MM Interface Blocks Design Example
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3. Select the new_topavalon.mdl file and click Open. Figure 76 shows new_topavalon.mdl.
Figure 76. new_topavalon.mdl Design Example
4. Rename the file by clicking Save As on the File menu. Create a new folder MySystem and save your new MDL file as topavalon.mdl in this folder. 5. Open the Simulink Library Browser. Expand the Altera DSP Builder Blockset and select Avalon Memory-Mapped in the Interfaces library. 6. Drag and drop an Avalon-MM Slave block into the top left of your model. Change the block name to Avalon_MM_Write_Slave. 7. Double-click on the Avalon_MM_Write_Slave block to bring up the Block Parameters dialog box. 8. Select Write for the address type, Signed Integer for the data type, and specify 8 bits for the data width. Turn off the Allow Byte Enable option. 9. Click OK. The Avalon_MM_Write_Slave block redraws with three ports: Address i1:0, Write ibit, and Write Data i7:0.
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Chapter 7: Using the Interfaces Library Avalon-MM Interface Blocks Design Example
10. Connect the ports (Figure 77). 1 You can re-size a block by dragging the resize handles at each corner.
11. Drag and drop another Avalon-MM Slave block into the top right of your model and change the name of this block instance to Avalon_MM_Read_Slave. 12. Double-click on the Avalon_MM_Read_Slave block to bring up the Block Parameters dialog box. 13. Select Read for the address type, Signed Integer for the data type, and specify 8 bits for the data width. 14. Click OK and notice that the Avalon_MM_Read_Slave block redraws with three ports: Address i1:0, Read ibit, and Read Data o7:0. 15. Complete your design by connecting the Avalon_MM_Read_Slave ports (Figure 77). f The default design example uses the Stratix II EP2S60 DSP Development Board. If you have a different board (such as the Cyclone II EP2C35 Development Board), you must replace the board block and analog-to-digital converter blocks by corresponding blocks for the appropriate board. For more information, refer to the Boards Library chapter in the DSP Builder Standard Blockset Libraries section in volume 2 of the DSP Builder Handbook.
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16. Add oscilloscope probes to monitor the signals on the DSP development board. 17. Click Save on the File menu in your model window to save your model. 18. Run a simulation and observe the results on the oscilloscope probes. Coefficient values 1 0 0 0 load into the filter.
2. Click Compare against HDL. This process generates HDL, runs Simulink and ModelSim, and then compares the simulation results. Progress messages issue in the dialog box and completes with a message Exact Match.
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Chapter 7: Using the Interfaces Library Avalon-MM Interface Blocks Design Example
3. Click OK.
c. Click Next in the New Project Wizard, until you get to the Family and Device Settings page. Verify that the selected device matches the FPGA on your DSP development board (if applicable). d. Click Finish to create the Quartus II project. 3. On the Tools menu, click Tcl Scripts and follow these steps: a. Select topavalon_add.tcl in the Project folder. b. Click Run to load your .mdl file and other required files into the Quartus II project. 4. On the Tools menu, click SOPC Builder and set the following parameters in the Create New System dialog box: a. Specify SOPC as the system name. b. Select VHDL for the target HDL. c. Click OK.
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5. Click the System Contents tab in SOPC Builder and set the following options: a. Expand Memories and Memory Controllers. b. Expand On-Chip and double-click On-Chip Memory (RAM or ROM). c. Specify 30 KBytes for the Total Memory size. d. Click Finish to add an on-chip RAM device to the system. e. Double-click Nios II Processor in the System Contents tab to display the MegaWizard interface. f. Set the reset and exception vectors to use onchip_mem and click Finish to add the processor to your system with all other parameters set to their default values. g. Expand Peripherals and Debug and Performance. Double-click on System ID Peripheral and click Finish to accept the default settings. h. Expand Interface Protocols and Serial. Double-click on JTAG UART and click Finish to accept the default settings. i. Expand DSPBuilder Systems and double-click the topavalon_interface module to include it in your Nios II system (Figure 79).
Figure 79. Including Your DSP Builder Design Module in SOPC Builder
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Chapter 7: Using the Interfaces Library Avalon-MM Interface Blocks Design Example
If the memory device, Nios II processor, debug peripheral, interface protocol, and DSP Builder system add in this order, you should not need to set a base address. However, you can click Auto-Assign Base Addresses on the System menu to automatically add a base address if necessary.
6. Click Generate to generate the SOPC Builder system. The system generation may take several minutes. After the system generation in SOPC Builder completes, you can design the rest of your Nios II embedded processor system using the standard Nios II embedded processor design flow. Continue with this tutorial to exercise the system from software using the Nios II processor.
You can ignore all other pin assignments for this tutorial.
Table 71. Pin Assignments for the Stratix II and Cyclone II Development Boards Node Name Direction Location
Stratix II EP2S60 or EP2S60ES DSP Development Board clk reset_n Input Input PIN_AM17 PIN_AG19
Cyclone II EP2C35 DSP Development Board clk reset_n Input Input PIN_N2 PIN_A14
3. Close the Pin Planner. 4. On the Processing menu, click Start Compilation to compile the Quartus II project. 5. When the compilation completes, click Programmer on the Tools menu and click Start in the Quartus II Programmer to program the FPGA device on your development board. 6. Close the Quartus II Programmer window.
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3. Add the test software to the new project as follows: a. Locate the file test_DSP_Block.c in your file system. (<DSP Builder install path>\DesignExamples\Tutorials\SOPCBuilder\SOPCBlock\) b. Right-click on the test_DSP_Block.c file and click Copy. c. Select the test_DSP_Block project folder in the Nios II IDE and paste the test_DSP_Block.c file into the project. 4. Set some of the reduced code footprint options in the Nios II IDE as follows: a. Right-click on the Nios II IDE application project, test_DSP_Block, and click Properties. b. In the Properties dialog box click System Library. c. Turn on Reduced device drivers and Small C library. d. Turn off Support C++. e. Click OK. 5. Run the test_DSP_Block software project in the Nios II IDE by right-clicking on test_DSP_Block and clicking Run As Nios II Hardware. The project compiles and the application code runs on the development board. Observe the following results in the Nios II IDE Console:
LOADING... Coefficient 1 = 1
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For information about using SOPC Builder to create a custom Nios II embedded processor, refer to AN 351: Simulating Nios II Embedded Processor Designs. Completed versions of the topavalon.mdl design for the Cyclone II EP2C35 and Stratix II EP2S60 DSP development boards are available in the <DSP Builder install path>\DesignExamples\Tutorials\SOPCBuilder\SOPCBlock\Finished Examples directory.
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4. When the compilation completes successfully, click OK. 1 The Avalon-MM read and write converter is simulation only and does not synthesize to HDL.
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2. On the File menu in the Quartus II software, click New Project Wizard and set the following options: a. Specify the working directory for your project by browsing to <DSP Builder install path>\DesignExamples\Tutorials\SOPCBuilder\AvalonFIFO. b. Specify a name for your project. This tutorial uses FIFO for the project name. 1 The Quartus II software automatically specifies a top-level design entity that has the same name as the project. This tutorial assumes that the names are the same.
c. Click Finish to create the Quartus II project. 3. On the Tools menu, click Tcl Scripts and set the following options: a. Load your design by selecting sopc_edge_detector_add.tcl in the Project folder. b. Click Run. 4. On the Tools menu, click SOPC Builder to display the Create New System dialog box. a. Specify AvalonFIFO as the system name. b. Select VHDL for the target HDL. c. Click OK. 5. Click the System Contents tab in SOPC Builder and set the following options: a. Expand Memories and Memory Controllers. b. Expand On-Chip and double-click On Chip Memory (RAM or ROM). c. Click Finish to add an on-chip RAM device with default parameters. 6. Double-click the Nios II Processor module in the System Contents tab to display the MegaWizard interface. 7. Set the reset and exception vectors to use onchip_memory2_0 and click Finish to add the processor to your system with all other parameters set to their default values. 8. Expand DSPBuilder Systems in the System Contents tab and double-click the sopc_edge_detector_interface module to include it in your Nios II system. You can now design the rest of your NIOS embedded processor with the standard SOPC Builder design flow. f For more detailed instructions, refer to Instantiating the Design in SOPC Builder on page 712 in the Avalon-MM Interface Blocks Design Example.
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Avalon-ST Interface
All DSP MegaCore functions in the DSP Builder MegaCore Functions library have interfaces that comply with the Avalon Interface Specifications. You can combine multiple MegaCore functions easily because they use a common interface. This section summarizes the features of the Avalon-ST interface. The Avalon Interface Specifications define how to convey data between a source interface and a sink interface. The interface indicates the integrity of the data by a feed forward signal, valid. The specification also defines how the MegaCore functions may stall other blocks (backpressure) or regulate the rate at which you provide data with a feedback sideband signal, ready. You can configure the DSP Builder Avalon-ST Source and Avalon-ST Sink blocks with a ready latency of 0 or 1. The ready latency is the number of cycles that a source must wait after a sink asserts ready so that a data transfer is possible. The source interface provides valid data at the earliest time possible, and it holds that data until sink asserts ready. The ready signal notifies the source interface that it has sampled the data on that clock cycle. For the ready_latency = 0 mode, Figure 712 shows the interaction that occurs between the source interface valid signal and the sink interface ready signal.
Figure 712. Avalon-ST Interface Timing for ready-latency=0
On cycle one, the source provides data and asserts valid even though the sink is not ready. The source waits until cycle two and the sink acknowledges that it samples the data by asserting ready. On cycle three, the source happens to provide data on the same cycle that the sink is ready to receive it and so the transfer occurs immediately. On the fourth cycle, the sink is ready but because the source does not provide any valid data, the data bus is not sampled. A beat is the transfer of one unit of data between a source and sink interface. This unit of data may consist of one or more symbols, so it can support modules that convey more than one piece of information on each valid cycle. Some modules have parallel input interfaces and other instances require serial input interfaces. For example, when conveying an in-phase and quadrature component on the same clock cycle. The choice depends on the algorithm, optimization technique, and throughput requirements.
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Figure 713 gives an example of a data transfer where two symbols are conveyed on each beatan in phase symbol I and a quadrature symbol Q. In this example, each symbol is eight bits wide.
Figure 713. Packetized Data Transfer
The Avalon Interface Specifications also describe several mechanisms to support the transfer of data associated with multiple channels. Altera recommends that you achieve this mechanism with packet based transfers where each packet has a deterministic format and each channel is allocated a specific field (time slot in a packet). Packet transfers require two additional signals that mark the start and the end of the packet. The MegaCore functions have internal counters that count the samples in a packet so they know which channel a particular sample is associated with and synchronize appropriately with the start and end of packet signals. In Figure 713, the in phase and quadrature components associated with three different channels convey between two MegaCore functions.
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Figure 714 shows an example of a generic function that has two input interfaces and performs a transformation on the two input streams.
Figure 714. Generic Function
The Signal Compiler block converts subsystems with blocks from the DSP Builder block libraries into HDL code. Non-DSP Builder blocks, such as encapsulations of your own pre-existing HDL code, require the Signal Compiler block to recognize them as black boxes so that the conversion process does not alter them. There are two types of black-box interface in DSP Builder: implicit and explicit.
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10. Turn on the option to Sort top-level ports by name. 11. Under Generate Simulink Model, click Compile to generate a Simulink simulation model for the imported HDL design.
Figure 81. HDL Import Dialog Box
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Chapter 8: Using Black Boxes for HDL Subsystems HDL Import Design Example
12. Progress messages issue in the HDL Import dialog box ending with the message:
Quartus II Analysis & Synthesis was successful.
13. The HDL Import block in the MyFilter.mdl model updates to show the ports defined in the imported HDL. 14. Click OK to close the HDL Import dialog box. 15. Connect the input and output ports to the symbol (Figure 82). The code generated for the HDL Import block automatically converts to a black box.
Figure 82. Completed Design
16. Click Save on the File menu to save the MyFilter.mdl file.
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6. Double-click on the manual switch connected to the Tsamp block to select the chirp_in stimulusa sinusoidal signal the frequency of which increases at a linear rate with time. 7. Click Start on the Simulation menu in your model window. 8. Double-click on the Scope block to view the simulation results. 9. Press the Autoscale icon to resize the scope. Figure 84 shows the simulation results.
Figure 84. Simulink Simulation Results for the Chirp Stimulus
The HDL import tutorial is complete. You can optionally compile your model for synthesis or perform RTL simulation on your design by following similar procedures to those described in the Getting Started.
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Simulink generic library Simulink blocksets (such as the DSP and Communications blocksets) DSP Builder blockset MATLAB functions S-functions
You must add a Non-synthesizable Input block and a Non-synthesizable Output block around any DSP Builder blocks in the subsystem. The following section shows an example that uses an S-function to describe the simulation models of the HDL code.
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5. Double-click the Subsystem Builder block. The Subsystem Builder dialog box displays (Figure 85).
Figure 85. Subsystem Builder Dialog Box
6. In the dialog box, browse for the fir_vhdl.vhd file and click Build. This action builds the subsystem and adds the signals for the fir_vhdl subsystem to the symbol in your filter8tap.mdl model. The Subsystem Builder dialog box automatically closes. 7. Connect the ports (Figure 86).
Figure 86. filter8tap Design
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8. Double-click on the fir_vhdl symbol. The filter8tap/fir_vhdl subsystem opens (Figure 87).
Figure 87. Library: filter8tap/fir_vhdl Window
The subsystem contains two HDL Input blocks (simulink_sclr and data_in) and a HDL Output block (data_out). Each of these blocks in turn connects to a subsystem input or output. DSP Builder also creates a HDL Entity block to store the name of the HDL file and the names of the clock and reset ports. 1 The clock is handled implicitly and no port is explicitly created in the subsystem.
9. Leave your model window open for use in the next section. In the next section, you build the simulation model that represents the functionality of this block in your Simulink simulations.
5. Click the Edit button to view the code that describes the S-Function.
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If the code does not appear automatically, click Browse and select the Sfir8tap.CPP file.
6. Scroll down in the Sfir8tap.CPP file to the S-function methods section. The following code shows the Simulink C++ S-Mex function code that designs a Simulink filter simulation model:
/*====================* * S-function methods * *====================*/ /* Function: mdlInitializeSizes======================================= * Abstract: * The sizes information is used by Simulink to determine the S-function * block's characteristics (number of inputs, outputs, states, etc.). */ static void mdlInitializeSizes(SimStruct *S) { /* See sfuntmpl.doc for more details on the macros below */ ssSetNumSFcnParams(S, 9); /* Number of expected parameters */
if (ssGetNumSFcnParams(S) != ssGetSFcnParamsCount(S)) { /* Return if number of expected != number of actual parameters */ return; } // Set DialogParameters not tunable const int iMaxssGetSFcnParamsCount = ssGetSFcnParamsCount(S); for (int p=0;p<iMaxssGetSFcnParamsCount;p++) { ssSetSFcnParamTunable(S, p, } if (!ssSetNumInputPorts(S, 1)) return; ssSetInputPortWidth(S, 0, 1); ssSetInputPortDataType(S, 0, SS_DOUBLE); 0);
if (!ssSetNumOutputPorts(S, 1)) return; ssSetOutputPortWidth(S, 0, 1); ssSetOutputPortDataType(S, 0, SS_DOUBLE); ssSetNumContStates(S, 0); ssSetNumDiscStates(S, 1); ssSetNumSampleTimes(S, 1); ssSetNumRWork(S, 0); ssSetNumIWork(S, 0); ssSetNumDWork(S, DYNAMICALLY_SIZED); // reserve element in the ssSetNumModes(S, 0); // pointers vector to store a C++ object
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During simulation, Simulink invokes certain callback methods from the S-function. The callback methods are subfunctions that initialize, update discrete states, and calculate output. Table 81 shows the design example callback methods.
Table 81. S-Function Callback Methods Callback Method mdlInitializeSizes Description Specify the number of inputs, outputs, states, parameters, and other characteristics of the S-function. Initialize the vectors of this S-function. Compute the signals that this block emits. Update the states of the block. Perform any actions required at termination of simulation.
mdlInitializeSampleTimes Specify the sample rates at which this S-function operates. mdlStart mdlOutputs mdlUpdate mdlTerminate
1. At the MATLAB command prompt, type: mex Sfir8tap.CPP r The mex command compiles and links the source file into a shared library executable in MATLAB, Sfir8tap.mexw32. The extension is specific to 32-bit version of MATLAB run in Windows. 2. Close the editor window and click on OK to close the Function Block Parameters dialog box. 3. In the filter8tap/fir_vhdl window, connect the input port of the S-function block to the data_in block, and connect the output port of the S-function block to the data_out block (Figure 88).
Figure 88. S-Function Block Connection
You do not need to connect the simulink_sclr block. The HDL Entity block automatically maps any input ports named simulink_clock in the VHDL entity to the global clock signal, and any input ports named simulink_sclr to the global synchronous clear signal.
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Because the input is a pulse, the simulation results show the impulse response of the 8-tap FIR filter, which translates to the eight coefficient values. You can change the input stimulus to verify the step and random response of the filter.
2. Copy the extra_add.tcl and extra_add_msim.tcl files from the original design directory to the DSPBuilder_filter8tap_import directory. The extra_add.tcl file adds final_add.vhd and four_mult_add.vhd to the Quartus II project, while extra_add_msim.tcl compiles them in ModelSim when your design is run using the TestBench block. The Quartus II software executes any files ending with _add.tcl when it creates the project. ModelSim executes files ending with _add_msim.tcl when it compiles your design testbench.
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A parameterizable custom library block is a Simulink subsystem in which DSP Builder primitives describe the block functionality. This design flow also supports parameterizable hierarchical subsystem structures. Altera provides an example of a custom library block, <DSP Builder install path>\ DesignExamples\Tutorials\BuildingCustomLibrary\top.mdl. (Figure 91).
Figure 91. top.mdl Example
The RamBasedDelay block that top.mdl uses, is an example of a custom parameterizable Simulink block. The library file MyLib.mdl defines it. The RamBasedDelay block has one parameter, Delay.
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5. Click Save on the File menu and save the library file as NewLib.mdl.
3. Double-click the Shift Taps block to open the Block Parameters dialog box. Table 91 shows the parameters to set.
Table 91. Parameters for the Shift Taps Block Parameter Main Tab Number Of Taps Distance Between Taps Optional Ports and Settings Tab Use Shift Out Port Use Enable port: Use Dedicated Circuitry Memory Block Type Off On On Auto 1 10 Value
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4. Click OK to close the Block Parameters dialog box. 5. Add an Input block (In2) from the Simulink Ports & Subsystems library and connect it to the ena port on the Shift Taps block. 6. Rename the blocks (Table 92).
Table 92. Renaming the Blocks Old Name In1 In2 Shift Taps Out1 InDin InEna DRB OutDout New Name
7. Click Save on the File menu. Figure 93 shows the completed DelayFIFO subsystem.
Figure 93. DelayFIFO Subsystem
Figure 94 shows the NewLib library model that now shows the input and output ports defined in the DelayFIFO subsystem.
Figure 94. NewLib Model
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Table 93. Parameters for the Mask Editor Parameter Icon Tab Frame Transparency Rotation Units Drawing Commands Visible Opaque Fixed Autoscale port_label('input',1,'din'); port_label('input',2,'ena'); port_label('output',1,'dout'); fprintf('Delay %d',d) Value
Parameters Tab Prompt Variable Documentation Tab Mask type Mask description SubSystem AlteraBlockSet RAM-Based Delay Element Altera Corporation Delay d
3. Click OK in the Mask Editor dialog box. 4. Double-click on the DelayFIFO block in your NewLib model to display the Block Parameters dialog box. 5. Specify a Delay of 5. 6. Click OK in the Block Parameters dialog box. 7. Click Save on the File menu to save your library model. f For more information about the Mask Editor, refer to the MATLAB Help.
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1. Right-click the DelayFIFO block in the NewLib model and click SubSystem Parameters on the pop-up menu to display the Block Parameters dialog box. 2. In the Read/Write permissions list, select ReadOnly. 1 The ReadWrite option allows edits from both the library and the design. The NoReadOrWrite option does not allow Signal Compiler to generate HDL for the design. If you want to modify a library model, open your model, click Unlock Library on the File menu and change the read and write permissions in the Block Parameters dialog box. Remember to reset ReadOnly after changing the library model. Your changes are automatically propagated to all instances in your design.
3. Click OK to close the Block Parameters dialog box. 4. Click Save on the File menu to save your library model.
3. Save the M-file with the file name slblocks.m in the same directory as NewLib.mdl. The next time that you display the Simulink library browser the custom library is available (Figure 95).
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You can drag and drop a block from your custom library in the same way as from any other library in the Simulink library browser. You can create a custom library with multiple blocks by creating the required blocks in the same library file. f For more information about M-files, refer to the MATLAB Help. A template slblocks.m file with explanatory comments is at <MATLAB install path>\toolbox\ simulink\blocks\slblocks.m.
This command calls automatically when you use either of the commands:
alt_dspbuilder_refresh_hdlimport
or
alt_dspbuilder_refresh_megacore
This chapter describes how to create and build a custom board library to use inside DSP Builder using built-in board components. Each board library is defined by a XML board description file. This board description file contains all the board components and their FPGA pin assignments. DSP Builder supports the following development boards:
Cyclone II DE2 Starter board Cyclone II EP2C35 board Cyclone II EP2C70 board Cyclone III EP3C25 Starter board Cyclone III EP3C120 board Stratix EP1S25 board Stratix EP1S80 board Stratix II EP2S60 board Stratix II EP2S180 board Stratix II EP2SGX90 PCI Express board Stratix III EP3SL150 board
For information about these boards, refer to the DSP Builder Standard Blockset Libraries section in volume 2 of the DSP Builder Handbook.
Predefined Components
Predefined components are in the following folder: <install dir>\quartus\dsp_builder\lib\boardsupport\components There is a single XML file, <component_name>.component, that describes each separate board component. This file defines its data type, direction, bus width, and appearance. The file also contains a brief description of the component.
Component Types
There are three main types of component: single bit, fixed size bus, and selectable single bit.
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Single Bit Type These components have a single bit with one FPGA pin assigned to each component. The components are either inputs or outputs and you cannot change them. DSP Builder offers the following single-bit predefined components:
Red and Green LEDs (LED0 to LED17 and LEDG0 to LEDG8) Software switches (SW0 to SW17) User push buttons (PB0 to PB3) Reset push buttons (IO_DEV_CLRn and USER_RESETN) RS232 receive output and RS232 transmit input pins (RS232Rout and RS232Tin)
Fixed-Size Bus Type These components have a fixed-sized group of same type (either input or output) pins with one FPGA pin assigned to each bit of the bus. DSP Builder offers the following fixed-size bus type predefined components:
12-bit analog-to-digital converter (A2D1Bit12 and A2D2Bit12) 14-bit analog-to-digital converter (A2D1Bit14 and A2D2Bit14) 14-bit digital-to-analog converter (D2A1 and D2A2) 8-bit dual in-line package switch (DipSwitch) 7-Segment display with a decimal point (SevenSegmentDisplay0 to SevenSegmentDisplay1) Simple 7-Segment display without a decimal point (Simple7SegmentDisplay0 to Simple7SegmentDisplay7)
Selectable Single Bit Type These components have a single bit, you can select the pin from a group of predefined FPGA pins. Furthermore, the pin can be set as either input or output. DSP Builder offers the following selectable single-bit predefined components:
Debug pins (DebugA and DebugB) Prototyping pins (PROTO, PROTO1 to PROTO3) Evaluation input pin (EvalIoIn) Evaluation output pin (EvalIoOut)
displayname= Specifies the name of the component, which the board description file references.
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direction= Specifies the direction of the signal. It can have the value of Input or Output. You can omit this attribute for the Selectable Single Bit Type, because it is set later. type= Specifies the data type of the signal. The type can be BIT, INT, or UINT. followed by the size in square brackets. For example, "BIT[1,0]" defines a single bit while "UINT[12,0]" is a 12-bit unsigned integer.
<documentation> text </documentation> This subelement contains text describing the component and one of the following variable that define how the pin name, or list of pin-names appears in the new board library:
%pinname% for single bit type %pinlist% for selectable single bit type %indexedpinliat% for fixed size bus type
icon= specifies the image file name for the component width= specifies the display width for the image file height= specifies the display height for the image file
For components without an image, you can omit the icon display attribute and define a visual representation using the plot and fprintf commands. For example:
<display width="90" height="26"> plot([0 19 20 21 22 21 20 19], [0 0 1 0 0 0 -1 0]); fprintf('EVAL IO OUT \n%pinname% '); </display>
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Header Section
This section contains the following line that defines the XML version and character encoding:
<?xml version="1.0" encoding="UTF-8"?>
In this case, the document conforms to the 1.0 specification of XML and uses the ISO-8859-1 (Latin-1/West European) character set. You should not modify this line.
The last line in the file must be a closing tag for the root element board </board>. The board attributes have the following definitions:
uniquename= A unique name to reference the board. family= Device family of the FPGA on board (assuming only one device is on the board).
The board must contain a displayname subelement containing text that describes the board. For example:
<displayname>Cyclone II XYZ Board</displayname>
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where attribute name defines the name of the component on the board and pin defines the FPGA pin to which the component is connected. The name must match one of the predefined components and you can use it only once per board.
where attribute name defines the name of the component on the board and label defines the name of the component as it appears in Simulink. For a component with width n, there must be n pin subelements. The pin location must be a valid FPGA pin name. The pin ordering is listed from LSB to MSB, with LSB on top of the list.
This element has the same format as the fixed-size bus type, but you can choose each pin element from a specified list of available FPGA pin locations. The configuration element defines the board configuration block. For example:
<configuration icon="dspboard2c35.bmp" width="166" height="144"> <devices jtag-code="0x020B40DD"> <device name="EP2C35F672C6" /> </devices> <!-- Input clock selection list --> <option name="ClockPinIn" label="Clock Pin In"> <pin location="Pin_N2"/> <pin location="Pin_N25"/> <pin location="Pin_AE14"/> <pin location="Pin_AF14"/> <pin location="None"/>
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</option> <!-- Global Reset Pin --> <option name="GlobalResetPin" label="Global Reset Pin"> <pin location="Pin_A14"/> <pin location="Pin_AC18"/> <pin location="Pin_AE16"/> <pin location="Pin_AE22"/> <pin location="None"/> </option> </configuration>
icon = the image file to be used for the board configuration block width = the width of the image height = the height of the image
jtag-code = the JTAG code of the FPGA device device name = the device name of the FPGA used on the board
name = the name of the option (clock or reset pin) label = labels that identifies the pins on the blocks pin location = a list of selectable clock or reset pins
For more examples, refer to any of the existing board description files.
This chapter describes how to implement a state machine in DSP Builder. 1 The State Machine Table block is not available on Linux and is deprecated on Windows. Use the State Machine Editor block in new designs. The design example, fifo_control_logic.mdl, contains a simple state machine to implement the control logic for a first-in first-out (FIFO) memory structure. The design files for this example are in the <DSP Builder install path>\ DesignExamples\Tutorials\StateMachine\StateMachineTable directory. Figure 111 shows the top-level schematic for the FIFO design example.
Figure 111. FIFO Design Example Top-Level Schematic
The state machine in this design example feeds the control inputs of a Dual-Port RAM block and the inputs of an address counter. The state machine has the following operation:
When you assert the push input and the address counter is less than 250, the address counter increments and a byte of data writes to memory. When you assert the pop input and the address counter is greater than 0, the address counter decrements and a byte of data reads from memory. When the address counter is equal to 0, the empty flag asserts When the address counter is equal to 250, the full flag asserts.
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You must save you model and change the default name of the State Machine Table block before you define the state machine properties.
2. Double-click the fifo_controller block to define the state machine properties. The State Machine Builder dialog box appears with the Inputs tab selected. The Inputs tab displays the input names defined for your state machine and provides an interface to allow you to add, and delete input names. 3. Delete the default input names In2, In3, In4, and In5 and enter the following new input names:
count_in pop push You can add or delete inputs but you cannot change an existing input name directly. You cannot delete or change the reset input.
4. Click the States tab. The States tab displays the state names defined for your state machine and provides an interface to allow you to add, change, and delete state names. The States tab also allows you to select the reset state for your state machine. The reset state is the state to which the state machine transitions when you assert the reset input. 1 You must define at least two states for the state machine. You cannot delete or change the name of a state while it is selected as the reset state.
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5. Use the Add, Change, and Delete buttons to replace the default states S1, S2, S3, S4, and S5 with the following states:
6. After specifying the input and state names, click the Conditional Statements tab and use it to describe the behavior of your state machine by adding the statements (Table 111).
Table 111. FIFO Controller Conditional Statements Current State empty empty full full idle idle idle idle pop_not_empty pop_not_empty pop_not_empty pop_not_empty pop_not_empty push_not_full push_not_full push_not_full push_not_full push_not_full Condition (push=1)&(count_in!=250) (push=0)&(pop=0) (push=0)&(pop=0) (pop=1) (pop=1)&(count_in=0) (push=1) (pop=1)&(count_in!=0) (push=1)&(count_in=250) (push=0)&(pop=0) (pop=1)&(count_in=0) (push=1)&(count_in!=250) (pop=1)&(count_in!=0) (push=1)&(count_in=250) (push=0)&(pop=0) (pop=1)&(count_in=0) (push=1)&(count_in!=250) (push=1)&(count_in=250) (pop=1)&(count_in!=0) idle idle pop_not_empty empty push_not_full pop_not_empty full idle empty push_not_full pop_not_empty full idle empty push_not_full full pop_not_empty Next State push_not_full
The Conditional Statements tab displays the state transition table, which contains the conditional statements that define your state machine. 1 There must be at least one conditional statement defined in the Conditional Statements tab.
A conditional statement consists of a current state, a condition that causes a transition to take place, and the next state to which the state machine transitions. The current state and next state values must be state names defined in the States tab, which you can select from a list in the dialog box.
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To indicate in a conditional statement that a state machine always transitions from the current state to the next state, specify the conditional expression to be one.
Figure 113 shows the Conditional Statements tab, after defining the conditional statements for the FIFO controller.
Figure 113. State Machine Builder Conditional Statements Tab
When a state machine is in a particular state, it may need to evaluate more than one condition to determine the next state to which it transitions. The priority of the conditional operator determines the priority if the condition contain only one operator. Table 112 shows the conditional operators you can use to define a conditional expression.
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Table 112. Comparison Operators Supported in Conditional Expressions Operator - (unary) (...) = != > >= < <= & | Description Negative Brackets Numeric equality Not equal to Greater than Greater than or equal to Less than Less than or equal to AND OR 1 1 2 2 2 2 2 2 2 2 Priority -1 (1) in1=5 in1!=5 in1>in2 in1>=in2 in1<in2 in1<=in2 (in1=in2)&(in3>=4) (in1=in2)|(in1>in2) Example
If the conditions contain multiple operators, they are evaluated in the order that you list them in the conditional statements table. Table 113 shows the conditional statements when the current state is idle. The condition (pop=1)&(count_in=0) is higher in the table than the condition (push=1)&(count_in=250), therefore it has higher priority. The condition (pop=1)&(count_in!=0) has the next highest priority and the condition (push=1)&(count_in=250) has the lowest priority.
Table 113. Idle State Condition Priority Current State idle idle idle idle push=1 (pop=1)&(count_in!=0) (push=1)&(count_in=250) Condition (pop=1)&(count_in=0) empty push_not_full pop_not_empty full Next State
1. Use the Move Up and Move Down buttons to change the order of the conditional statements (Table 114).
Table 114. Idle State Condition Priority (Reordered) Current State idle idle idle idle Condition (pop=1)&(count_in=0) (push=1)&(count_in=250) (pop=1)&(count_in!=0) push=1 empty full pop_not_empty push_not_full Next State
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2. Click the Design Rule Check tab. You can use this tab to verify that the state machine you defined in the previous steps does not violate any of the design rules. Click Analyze to evaluate the design rules for your state machine. If a design rule is violated, an error message, highlighted in red, is listed in the Analysis Results box. If error messages appear in the analysis results, fix the errors and rerun the analysis until no error messages appear before simulating and generating VHDL for your design. Figure 114 shows the Design Rule Check tab after clicking Analyze.
Figure 114. State Machine Builder Design Rule Check Tab
3. To save the changes made to your state machine, click OK. The State Machine Builder dialog box closes and returns you to your Simulink design file. The design file automatically updates with the input and output names defined in the previous steps. 1 You may need to resize the block to ensure that the input and state names do not overlap and display correctly.
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You should save you model and change the default name of the State Machine Editor block before you define the state machine properties.
2. Double-click the fifo_controller block to open the State Machine Editor in the Quartus II software (Figure 117).
Figure 117. Quartus II State Machine Editor Window
3. On the Tools menu in the Quartus II State Machine Editor, point to State Machine Wizard and click Create a new state machine design.
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4. The first page of the wizard allows you to choose the reset mode, whether the reset is active-high or active-low, and whether the outputs are registered. Accept the default values (synchronous, active-high, registered outputs) and click Next to display the Transitions page of the wizard. 5. Delete the default state names (state1, state2, state3) and type the following new state names:
6. Delete the default input port names (input1, input2) and type the following new input port names:
count_in[7:0] pop push Do not change the clock and reset port names. The count_in port must be defined as an 8-bit vector to allow count values up to 250.
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The transitions are validated on entry and must conform with Verilog HDL syntax.
Figure 118 shows the Transitions page after you define the states, inputs, and transitions.
Figure 118. State Machine Editor Wizard Transitions Page
8. Click Next to display the Actions page. Delete the default output port name (output1) and enter the following new output port names:
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9. Specify the output logic for each output port by specifying the action conditions to set each output port to 1 when the state is true and 0 for all other states (Table 116).
Table 116. FIFO Controller Output Actions Output Port out_empty out_full out_idle out_pop_not_empty out_push_not_full out_empty out_empty out_empty out_empty out_full out_full out_full out_full out_idle out_idle out_idle out_idle out_pop_not_empty out_pop_not_empty out_pop_not_empty out_pop_not_empty out_push_not_full out_push_not_full out_push_not_full out_push_not_full 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Output Value empty full idle pop_not_empty push_not_full full idle pop_not_empty push_not_full empty idle pop_not_empty push_not_full empty full pop_not_empty push_not_full empty full idle push_not_full empty full idle pop_not_empty In State
Chapter 11: Using the State Machine Library Using the State Machine Editor Block
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Figure 119 shows the Actions page after you define the output ports, and action.
Figure 119. State Machine Editor Wizard Actions Page
10. Click Next to display the Summary page. Check that the summary lists the five states (empty, full, idle, pop_not_empty, and push_not_full), the five input ports (clock, count_in[7:0], pop, push, and reset), and the five output ports (out_empty, out_full, out_idle, out_pop_not_full, and out_push_not_full). 11. Click Finish to complete the state machine definition. The state machine displays graphically in the State Editor window (Figure 1110 on page 1112).
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Chapter 11: Using the State Machine Library Using the State Machine Editor Block
DSP Builder marks the first state that you enter in the wizard as the default state. This state is the empty state and is the state to which the state machine transitions when you assert the reset input.
12. On the Tools menu in the Quartus II State Machine Editor, click Generate HDL File to display the Generate HDL File dialog box. Select VHDL and click OK to confirm your choice. Click Yes to save the fifo_controller.smf file and check that there are no FSM verification errors. 1 There are five warning messages stating that FSM verification skips in each state. You can ignore these messages.
If there are any errors, you can edit the state machine using the Properties dialog boxes that you can display from the right button pop-up menu when you select a state or transition. You can also edit the state machine in table format by clicking the tabs at the bottom of the State Machine Editor window. f For information about editing state machine properties and drawing a graphical state machine, refer to the About the State Machine Editor topic in the Quartus II Help. 13. On the File menu in the Quartus II State Machine Editor, click Exit. The fifo_controller block on your model updates with the input and output ports defined in the state machine.
Chapter 11: Using the State Machine Library Using the State Machine Editor Block
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You may need to resize the block to ensure that the input and state names do not overlap and are displayed correctly.
Figure 1111 shows the updated fifo_controller block for the FIFO design example.
Figure 1111. fifo_controller Block After Closing the State Machine Editor
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Chapter 11: Using the State Machine Library Using the State Machine Editor Block
DSP Builder design requires the following files to store all the components:
The top-level Simulink model <top_level_name>.mdl The import directory DSPBuilder_<top_level_name>_import and its contents. Any source files for imported HDL. Any Intel format hexadecimal memory initialization (.hex) files. Any referenced custom library files. The analyzed Simulink model file <top_level_name>.mdlxml.
When you include the .mdlxml file in a Quartus II project, you do not need to call MATLAB to synthesize the design. You can still synthesize a project without the .mdlxml file, but you must call MATLAB as part of the generation flow. If you do not want Quartus II synthesis to call MATLAB, or are passing the design a user without access to MATLAB, follow one of these steps:
Include both the .mdl and corresponding .mdlxml files in the project, Export HDL and specify the exported HDL as the source with no references to the .mdl or .mdlxml files in the project.
Any design that includes HDL Import, State Machine Editor or MegaCore functions requires the import directory.
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HDL Import
In general, source files that you import with HDL Import are not part of a DSP Builder project. DSP Builder references them in projects that generate with the Export HDL flow as external files, with absolute paths. When you move a design to a new version of the tools or to a location on a different computer, run the alt_dspbuilder_refresh_HDLimport script to ensure the HDL Import blocks are up-to-date. When migrating to a new computer, re-import the HDL to enable hardware generation (although simulation in Simulink may be possible without this step).
MegaCore Functions
The MegaCore IP Library always installs in the same parent directory as the Quartus II installation. This directory is not a subdirectory of the quartus directory but a relative path to an install directory at the same level as the quartus directory. The expected directory structure is: <install_path><QUARTUS_ROOTDIR>\..\ip This feature allows the Export HDL flow to use relative paths, and improves portability. 1 Before the Quartus II software version 8.0, it was possible to install previous versions of the MegaCore IP Library in any specified location. If you use an old version of the MegaCore IP Library in your design, there may still be absolute paths in the generated Quartus II IP (.qip) files that you must modify when you move projects to a different location. The .qip file contains all the assignments and other information that the design requires to process the exported HDL in the Quartus II compiler and generate hardware. When moving a design to a new version of the tools or a different location, run the alt_dspbuilder_refresh_megacore script to ensure that the MegaCore function blocks are up-to-date. Successful migration of designs with MegaCore Functions assumes that the new environment has all the required IP installed. It may be necessary to install the MegaCore IP Library and run the alt_dspbuilder_setup_megacore script.
Exporting HDL
You can export the DSP Builder-generated synthesizable HDL to a Quartus II project and then use the Export tab in the Signal Compiler block to export them (Figure 121).
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You can also export HDL by executing the alt_dspbuilder_exportHDL command in the MATLAB command window. The syntax for the export HDL command is: <exportDir_value> alt_dspbuilder_exportHDL(<model>, <exportDir>) where:
model is the name of the .mdl file to export. This file is always the top-level name in the exported Quartus II project. exportDir is the directory that contains the exported files. If you omit this optional argument, DSP Builder uses the default or previous export directory. exportedDir_value is the return string indicating the output directory containing the newly generated files.
Running this flow creates a set of source files in the export directory, including a .qip file corresponding to the top-level of your design.
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DSP Builder model (.mdl) HDL source files associated with HDL import blocks (if any)maintain same relative path to MDL HDL wrapper files associated with IP MegaCore function blocks (if any) maintain same relative path to the .mdl file (they should be in the DSPBuilder_<mdl name>_import subdirectory) Memory initialization .hex files (if any) Custom library files (if any)
To recreate the project in the new location, follow these steps: 1. If the model contains IP MegaCore function or HDL import blocks, regenerate the auxiliary files (.qip, .entityimport, .simdb) associated with the IP MegaCore function or HDL import block by following these steps: a. HDL importrun the alt_dspbuilder_refresh_HDLimport script to automatically update all the HDL import blocks in the new location. b. IP MegaCore functionsrun the alt_dspbuilder_refresh_megacore script to automatically update all the IP MegaCore function blocks in the new location. Successful migration of design with IP MegaCore functions assumes that you install the required MegaCore IP library on the new environment.
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If the ..\DSPBuilder_<mdl name>_import subdirectory copies and the design files, skip this step.
2. Re-analyze the model by clicking Analyze in the Advanced tab of the Signal Compiler block to regenerate the auxiliary files (.mdlxml, .qip, .ipx) associated with the model.
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These statements specify the relative path to the directory where to locate the .mdl file and where to search for directories containing further .ipx files. The ** means search recursively, and the final * locates all identifiable elements there. You can combine all the search paths into a single .ipx file. For example:
<library> <path path='../../../<module name1>/**/*'/> <path path='../../../<module name2>/**/*'/> ... </library>
Design Example
The following example shows how you can integrate multiple DSP Builder designs into a top-level Quartus II project. Suppose your top-level design consists of the following three DSP Builder models:
fir1.mdlcontaining two Avalon-MM slave interfaces fir2.mdlcontaining multiple HDL import blocks fir3.mdlcontaining one IP MegaCore function block with two Avalon-ST interfaces
In the top-level Quartus II project, there are the following four design files:
top.vhdTop-level wrapper that instantiates the three separate models fir1.qipQuartus IP file for fir1.mdl fir2.qipQuartus IP file for fir2.mdl fir3.qipQuartus IP file for fir3.mdl
Figure 122 on page 127 shows the design example in the Quartus II Project Navigator window. 1 In this example, fir2.qip has an embedded .qip associated with the HDL import block and fir3.qip has an embedded .qip associated with the IP MegaCore function block. To update the IP Librarian search path, create additional directories <project directory>/ip/<module name> and create an .ipx file in each subdirectory. Thus in this design example, create the following directories:
and in each subdirectory, create a text file <module name>.ipx with the following contents:
<library> <path path='../../../<module name>/**/*'/>
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</library>
These .ipx files specify the relative path to the directory, where the .mdl file is located and tell the IP Librarian where to look for the components.
Figure 122. Project Navigator Window in the Quartus II Software
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13. Troubleshooting
Troubleshooting Issues
This chapter contains information about resolving the following DSP Builder issues and error conditions:
Signal Compiler Cannot Checkout a Valid License Loop Detected While Propagating Bit Widths The MegaCore Functions Library Does Not Appear in Simulink The Synthesis Flow Does Not Run Properly DSP Development Board Troubleshooting SignalTap II Analysis Appears to Hang Error if Output Block Connected to an Altera Synthesis Block Warning if Input/Output Blocks Conflict with clock or aclr Ports Wiring the Asynchronous Clear Signal Error Issues when a Design Includes Pre-v7.1 Blocks Creating an Input Terminator for Debugging a Design A Specified Path Cannot be Found or a File Name is Too Long Incorrect Interpretation of Number Format in Output from MegaCore Functions Simulation Mismatch For FIR Compiler MegaCore Function Simulation Mismatch After Changing Signals or Parameters Unexpected Exception Error when Generating Blocks VHDL Entity Names Change if a Model is Modified Algebraic Loop Causes Simulation to Fail Parameter Entry Problems in the DSP Block Dialog Box DSP Builder System Not Detected in SOPC Builder MATLAB Runs Out of Java Virtual Machine Heap Memory ModelSim Fails to Invoke From DSP Builder Unexpected End of File Error When Comparing Simulation Results
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For information about how to obtain a license, refer to Volume 1: Introduction to DSP Builder in the DSP Builder Handbook.
where C4D5_512 is the DSP Builder feature ID. This command outputs the status of the DSP Builder license. For example, if you are using a node locked license:
lmutil - Copyright (C) 1989-2006 Macrovision Europe Ltd. and/or Macrovision Corporation. All Rights Reserved. FLEXnet diagnostics on Mon 8/11/2008 14:36 ----------------------------------------------------License file: c:\qdesigns\license.dat ----------------------------------------------------"C4D5_512A" v0000.00, vendor: alterad uncounted nodelocked license, locked to Vendor-defined "GUARD_ID=T000001297" no expiration date
You receive a message about the hostid if you are using an Altera software guard for licensing. Alternatively, if you are using a floating license:
>> dos('lmutil lmdiag C4D5_512A')
lmutil - Copyright (c) 1989-2006 Macrovision Europe Ltd. and/or Macrovision Corporation. All Rights Reserved. FLEXnet diagnostics on Mon 8/11/2008 10:49 ----------------------------------------------------License file: node@lic_server ----------------------------------------------------"C4D5_512A" v2030.12, vendor: alterad License server: lic_server floating license expires: 31-dec-2030
If the command does not work, your license file may not be set up correctly. For information about how to check your system path and registry settings, refer to The Synthesis Flow Does Not Run Properly on page 135. If your license file has a SERVER line, type the following command in the MATLAB Command Window:
dos('lmutil lmstat -a') r
This command outputs the status of the DSP Builder license in the following format:
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lmutil - Copyright (c) 1989-2006 Macrovision Europe Ltd. and/or Macrovision Corporation. All Rights Reserved. Flexible License Manager status on Mon 8/11/2008 15:36 License server status: [Detecting lmgrd processes...] License server status: node@lic_server License file(s) on shama: /usr/licenses/quartus/license.dat: lic_server: license server UP (MASTER) v10.8 Vendor daemon status (on lic_server): alterad: UP v9.2 Feature usage info: Users of C4D5_512A: (Total of 100 licenses issued; Total of 0 licenses in use)
If the command does not work, your license file may not be set up correctly.
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This command returns the path that the QUARTUS_ROOTDIR environment variable specifies. For example:
C:\altera\81\quartus
quartus/bin matlab/bin
Remove and reinstall DSP Builder. After removing DSP Builder, delete any DSP Builder files or directories that remain in the file system to ensure that you re-install a clean file set.
To avoid this error, include an AltBus block configured as an internal node to specify the bit width in the feedback loop explicitly (Figure 132).
Figure 132. Feedback Loop With AltBus Block as an Internal Node
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Ensure that you set up and connect the board to your PC and you install any necessary drivers. When the board powers up, the CONF_DONE LED illuminates. The CONF_DONE LED turns off and then on when configuration completes successfully. If you do not observe the LED operating in this way, configuration is unsuccessful. You can configure the DSP board manually with an SRAM Object File (.sof), a ByteBlasterMV, ByteBlaster II, ByteBlaster, or USB-Blaster download cable, and the Quartus II Programmer in JTAG mode. Signal Compiler generates the SRAM object file (.sof) file in your working directory.
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The input port renames during HDL conversion. If you want to keep the port aclr, add a Clock block and use it to rename the reset port.
A design may not match the hardware if an asynchronous clear performs during simulation because the aclr cycle may last several clocks - depending on clock speed and the device.
For information about upgrading your designs, refer to Volume 1: Introduction to DSP Builder in the DSP Builder Handbook.
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This problem is caused by corrupted Librarian IP cache and can be resolved by deleting the IP cache directory which is normally located at: C:\Documents and Settings\<user>\.altera.quartus\ip_cache
The direct feedthrough settings for the HDL Import block update after a successful compile of the HDL when this parameter is on. 1 This feature may not generate correct settings when importing low-level LPM-based HDL.
A more direct method of changing the direct feedthrough settings is to modify the InDelayed parameter on HDL Import or MegaCore function blocks, with the following command: set_param(<block name>, 'inDelayed', <feedthrough setting>) For example, if the block is named My_HDL: set_param(<My_HDL>, 'inDelayed', '1 0 0 1') A valid value of this parameter is a series of digits, one for each of the inputs on the block (from top to bottom), with a 0 indicating direct feedthrough, and a 1 indicating that all paths to outputs from this input are registered. 1 Specifying a value of 1 for an input, when it is in fact direct feedthrough, causes Simulink to treat combinational paths as registered, and results in incorrect simulation results.
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Adjust the order in which Simulink exercises all the blocks in a feedback loop, by giving blocks a priority value. This procedure is useful if you know which block is providing the correct initial values. The priority of a block can be set with the General tab in the block properties for a block. A lower value of priority causes DSP Builder to execute a block before a block with a higher value.
For information about how to increase the heap space available to the Java virtual machine, refer to: http://www.mathworks.com/support/solutions/data/1-18I2C.html
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You can verify the ModelSim installation by typing the following command at the MATLAB prompt:
!vsim
This command returns the ModelSim version and the path to the ModelSim preferences Tcl file. If an error message issues or the returned path is incorrect, you may need to move ModelSim to be ahead of any other similar tool in the path. f For information about the supported version of ModelSim, refer to the DSP Builder Installation and Licensing manual.
Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Revision History
The following table shows the revision history for this section.
Date June 2010 Version 1.0 First published. Changes Made
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1. AltLab Library
The blocks in the AltLab library manage design hierarchy and generate RTL VHDL for synthesis and simulation. The AltLab library contains the following blocks:
BP (Bus Probe) Clock Clock_Derived Display Pipeline Depth HDL Entity HDL Import HDL Input HDL Output HIL (Hardware in the Loop) Quartus II Global Project Assignment Quartus II Pinout Assignments Resource Usage Signal Compiler SignalTap II Logic Analyzer SignalTap II Node Subsystem Builder TestBench VCD Sink
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BP (Bus Probe)
The Bus Probe (BP) block is a sink, which you can place on any node of a model. The Bus Probe block does not have any hardware representation and therefore does not appear in the VHDL RTL representation generated by the Signal Compiler block. The Display in Symbol parameter selects the graphical shape of the symbol in your model and the information that is reported there (Table 11).
Table 11. Bus Probe Block Display in Symbol Parameter Shape of Symbol Circle Rectangle Data Reported in Symbol Maximum number of integer bits required during simulation. Maximum or minimum value reached during simulation.
After simulating your model, the Bus Probe block back-annotates the following information in the parameters dialog box for the Bus Probe block:
Maximum value reached during simulation Minimum value reached during simulation Maximum number of integer bits required during simulation
Clock
Use the Clock block in the top level of a design to set the base hardware clock domain. The block name is the name of the clock signal and must be a valid VHDL identifier. A design can have zero or one base clock in a design and an error issues if you try to use more than one base clock. You can specify the required units and enter any positive value with the specified units. However, the clock period must be greater than 1ps but less than 2.1ms. If no base clock exists in your design, a default clock (clock) with a 20-ns real-world period and a Simulink sample time of 1 is automatically created with a default Active Low reset (aclr). 1 To avoid sample time conflicts in the Simulink simulation, ensure that the sample time specified in the Simulink source block matches the sample time specified in the Input block (driven by the Clock block or a derived clock). Place additional clocks in the system by adding Clock_Derived blocks. Each clock must have a unique reset name. As all clock blocks have the same default reset name (aclr) ensure you specify a valid unique name with multiple clocks. You can add reset synchronizer circuitry for this clock domain by specifying the reset type to be either synchronized active low or synchronized active high. When you specify these reset types, DSP Builder adds two extra registers to avoid metastability issues during reset removal.
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Clock_Derived
Use the Clock_Derived block in the top level of a design to add additional clock pins to your design. Specify these clocks as a rational multiple of the base clock for simulation purposes. DSP Builder uses the block name as the name of the clock signal. It must be a valid VHDL identifier. You can specify the numerator and denominator multiplicands calculates the derived clock. However, the resulting clock period should be greater than 1ps but less than 2.1ms. If no base clock is set in your design, DSP Builder creates a 20ns base clock and determines the derived clock period. You must use a Clock block to set the base clock if you want the sample time to be anything other than 1. 1 To avoid sample time conflicts in the Simulink simulation, ensure that the sample time specified in the Simulink source block matches the sample time specified in the Input block (driven by the Clock block or a derived clock). Each clock must have a unique reset name. As all clock blocks have the same default reset name (aclr) ensure you specify a valid unique name with multiple clocks. You can add reset synchronizer circuitry for this clock domain by specifying the reset type to be synchronized active low or synchronized active high. When you specify these reset types, DSP Builder adds two extra registers to avoid metastability issues during reset removal. Table 13 lists the parameters for the Clock_Derived block:
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Table 13. Clock_Derived Block Parameters Name Base Clock Multiplicand Numerator Base Clock Multiplicand Denominator Reset Name Reset Type >= 1 >= 1 User defined Active Low, Active High, Synchronized Active Low, Synchronized Active High On or Off Value Description Multiply the base clock period by this value. The resulting clock period should be greater than 1ps but less than 2.1ms. Divide the base clock period by this value. The resulting clock period should be greater than 1ps but less than 2.1ms. Specify a unique reset name. The default reset is aclr. Specify whether the reset signal is active high or active low.
HDL Entity
Use the HDL Entity block for black-box simulation subsystems that you include in your design with a Subsystem Builder block. The HDL Entity block specifies the name of the HDL file that DSP Builder substitutes for the subsystem and the names of the clock and reset ports for the subsystem. The Subsystem Builder block usually creates this block. Table 14 shows the parameters for the HDL Entity block.
Table 14. HDL Entity Block Parameters Name HDL File Name Clock Name Reset Name HDL takes port names from Subsystem Value Description
User defined Specifies the name of the HDL file that DSP Builder substitutes for the subsystem represented by a Subsystem Builder block. User defined Specifies the name of the clock signal that the black-box subsystem uses. User defined Specifies the name of the reset signal that the black-box subsystem uses. On or Off Turn on to use the subsystem port names as the entity port names instead of the names of the HDL Input and HDL Output blocks.
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HDL Import
Use the HDL Import block to import existing blocks implemented in HDL into DSP Builder. Individually specify the VHDL or Verilog HDL files or define in a Quartus II project file (.qpf). 1 You must save your model file before you can import HDL with the HDL Import block. When you click Compile, a simulation file generates and the block in your model configures with the required input and output ports. The Quartus II software synthesizes the imported HDL or project as a netlist of megafunctions, LPM functions, and gates. DSP Builder may explicitly instantiate the megafunctions and LPM functions in the imported files, or the Quartus II software may infer them. The netlist then compiles into a binary simulation netlist for use by the HDL simulation engine in DSP Builder. When simulating imported VHDL in ModelSim, which includes FIFO buffers, there may be Xs in the simulation results, which may give a mismatch with the Simulink simulation. You should use the FIFO buffer carefully to avoid any overflows or underflows. Examine and eliminate any warnings of Xs that ModelSim reports during simulation before you compare to the Simulink results. The simulator supports many of the common megafunctions and LPM functions although it does not support some. If DSP Builder encounters an unsupported function, it issues an error message after you click Compile and it cannot import the HDL. However, you may be able to rewrite the HDL so that the Quartus II software infers a different megafunction or LPM function. Table 15 shows the parameters for the HDL Import block.
Table 15. HDL Import Block Parameters (Part 1 of 2) Name Import HDL Add Remove Up, Down Value On or Off Description You can import individual HDL files when this option is on. Click to remove the selected file from the list. Click to change the compilation order by moving the selected HDL file up or down the list. The file order is not important when you use the Quartus II software but may be significant when you use other downstream tools (such as ModelSim). Specifies the name of the top level entity in the imported HDL files. When this option is on, you can specify the HDL to import with a Quartus II project file (.qpf). DSP Builder imports the current HDL configuration. To import a different revision, specify the required revision in the Quartus II software. The source files that the Quartus II project uses must be in the same directory as your model file or be explicitly referenced in the Quartus II settings file (.qsf). Error messages issue for any entities that DSP Builder cannot find. Refer to the Quartus II documentation for information about setting the current revision of a project and how to explicitly reference the source files in your design. Click to browse for a Quartus II project file.
.v or .vhd file Click to browse for one or more VHDL files or Verilog HDL files.
Browse
.qpf file
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Table 15. HDL Import Block Parameters (Part 2 of 2) Sort top-level ports by name Compile On or Off Turn on to sort the ports that the top-level HDL file alphabetically defines instead of the order specified in the HDL. Compiles a simulation model from the imported HDL and displays the ports defined in the imported HDL on the block.
Figure 11 shows an example of an imported HDL design implementing a simple adder with four input ports (Input, Input1, Input2, sclrp), and two output ports (Output, Output1).
Figure 11. Typical HDL Import Block
Use std_logic_1164 types to define the input and output interfaces to the imported VHDL. If your design uses any other VHDL type definitions (such as arithmetic or numeric types), you should write a wrapper that converts them to std_logic or std_logic_vector. HDL import only supports single clock designs. If you import a design with multiple clocks, DSP Builder uses one clock as the implicit clock and shows any others as input ports on the Simulink block. 1 Store HDL source files in any directory or hierarchy of directories. Table 16 lists the supported megafunctions and LPM functions.
Table 16. Supported Megafunctions and LPM Functions Megafunctions a_graycounter altaccumulate altmult_add altshift_taps
Note to Table 16:
(1) The lpm_mult LPM function is not supported when configured to perform a squaring operation.
LPM Functions lpm_abs lpm_add_sub lpm_compare lpm_counter lpm_mult (Note 1) lpm_mux lpm_ram_dp
Table 17 on page 17 lists the megafunctions and LPM functions that are not supported.
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Table 17. Unsupported Megafunctions and LPM Functions Megafunctions alt3pram altcam altcdr altclklock altddio altdpram altera_mf_common altfp_mult altlvds altmemmult altmult_accum altpll altqpram altsqrt alt_exc_dpram alt_exc_upcore dcfifo lpm_and lpm_bustri lpm_clshift lpm_constant lpm_decode lpm_divide lpm_ff lpm_fifo lpm_fifo_dc LPM Functions lpm_inv lpm_latch lpm_or lpm_pad lpm_ram_dq lpm_ram_io lpm_rom lpm_shiftreg lpm_xor
HDL Input
Connect the HDL Input block directly to an input node in a subsystem. Use with the Subsystem Builder and HDL Entity blocks for black-box simulation. The type and bit width must match the type and bit width on the corresponding input port in the HDL file referenced by the HDL Entity block. HDL Input blocks are automatically generated by the Subsystem Builder block. You can optionally specify the external Simulink type. If set to Simulink Fixed Point Type, the bit width is the same as the input. If set to Double, the width may be truncated if the bit width is greater than 52. Table 18 shows the HDL Input block parameters.
.
Table 18. HDL Input Block Parameters Name Bus Type Value Signed Integer, Signed Fractional, Unsigned Integer, Single Bit >= 0 (Parameterizable) [].[number of bits] External Type >= 0 (Parameterizable) Description The number format of the bus.
[number of bits].[]
Specify the number of bits to the left of the binary point, including the sign bit. This parameter does not apply to single-bit buses. Specify the number of bits to the right of the binary point. This parameter applies only to signed fractional buses.
Inferred, Specifies whether the external type is inferred from the Simulink block it Simulink Fixed Point Type, is connected to or explicitly set to either Simulink Fixed Point or Double Double type. The default is Inferred.
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Table 19. HDL Input Block I/O Formats (Part 2 of 2) (Note 1) I/O O Simulink (2), (3) O1[LP].[RP] VHDL O1: out STD_LOGIC_VECTOR({LP + RP - 1} DOWNTO 0) Type (4) Explicit
HDL Output
The HDL Output block should be connected directly to an output node in a subsystem. Use with the Subsystem Builder and HDL Entity blocks for black-box simulation. The type and bit width must match the type and bit width on the corresponding output port in the HDL file referenced by the HDL Entity block. HDL Output blocks are automatically generated by the Subsystem Builder block. Table 110 shows the HDL Output block parameters.
Table 110. HDL Output Block Parameters Name Bus Type Value Signed Integer, The number format of the bus. Signed Fractional, Unsigned Integer, Single Bit >= 0 Specify the number of bits to the left of the binary point, including the sign bit. (Parameterizable) This parameter does not apply to single-bit buses. >= 0 Specify the number of bits to the right of the binary point. This parameter applies (Parameterizable) only to signed fractional buses. Description
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Exported ports (allows the use of hardware components connected to the FPGA) Burst and frame modes (improves HIL simulation speed)
This block supports only single clock designs with registered paths in a design. The simulation results may be unreliable for combinational paths. Table 112 shows the parameters specified in page 1 of the HIL dialog box.
Table 112. HIL Block Parameters, Page 1 (Part 1 of 2) Name Select the Quartus II project Select the clock pin Select the reset pin Identify the signed ports Export Select the reset level Value .qpf file Port name Port name Signed or Unsigned On or Off Description Browse for a Quartus II project file ,which describes the hardware design that the HIL block uses. The clock pin name for the hardware design in the Quartus II software. The reset pin name for the hardware design in the Quartus II software. Set the number of bits and select the type (signed or unsigned) of each input and output port in the hardware design. When on, the selected port is exported on an FPGA pin (or on multiple pins for buses). When off (the default), the port is exported to the Simulink model.
Active_High, The reset level that matches the setting in the original design. For designs originated Active_Low from the standard blockset, the reset level is specified in the Clock or Clock_Derived block. If your design uses no clock block, it uses a default clock with reset level active high. For designs originated from the advanced blockset, the reset level is specified in the Signals block. On or Off When on, allows sending data to the FPGA in bursts, which improves the simulation speed, but delays the outputs by the burst length. When Off, it defaults to single-step mode. Specify the length of a burst ("1" is equivalent to disabling burst mode). Use higher values to produce faster simulations (although the extra gain becomes negligible with bigger burst sizes). Use in burst mode when data is sent or received in frames. When on, allows synchronizing of the output data frames to the input data frames. The input port for the synchronization signal in frame mode. The output port for the synchronization signal in frame mode. Specify the sample time period in seconds. (A value of -1 means that the sampling period is inherited from the block connected to the inputs.)
Burst Mode
Burst Length
(Note 1)
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Table 112. HIL Block Parameters, Page 1 (Part 2 of 2) Name Value Description When on, asserts the synchronous clear signal before the simulation starts.
(1) The record size is 3210241024, which is the product of (packet size) (burst length) while the packet size is the larger of the total input data width and the total output data width. For example, for a packet size of 1024 bits, set the burst length to 321024. However, due to the limitations of the JTAG interface, the optimal record size is between 1 to 2 MBPS (depending on the host computer, USB driver and cables). Hence, setting a bigger burst size might not give significant speed up.
The HIL block needs recompilation if you change the Quartus II project, clock pin, or any of the exported ports. Table 113 shows the parameters specified in page 2 of the HIL dialog box.
Table 113. HIL Block Parameters, Page 2 Name FPGA device Compile with Quartus II JTAG Cable Device in chain Scan JTAG Value device name cable name The FPGA device. Click to compile the HIL block with the Quartus II software. The JTAG cable. Click to scan the JTAG interface for all JTAG cables attached to the system (including any remote computers) and the devices on each JTAG cable. The available cable names and device names are loaded into the JTAG Cable and Device in chain list boxes. Click to configure the FPGA. Displays the progress of the compilation. Description
device location The required entry for the location of the device.
Refer to the Using Hardware in the Loop chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook.
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Table 114 shows the Quartus II Global Project Assignment block parameters.
Table 114. Quartus II Global Project Assignment Block Parameters Name Assignment Name Assignment Value Value String String Specify the assignment name. Specify the assignment value with any optional arguments. Any values or arguments that contain spaces or other special characters must be enclosed in quotes. Description
Figure 13 shows an example defining multiple assignments with Quartus II Global Project Assignment blocks.
Figure 13. Assignments With Quartus II Global Project Assignment Blocks
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For example: Pin Name: abc Pin Location: Pin_AA, Pin_AB, Pin_AC assigns abc[0] to Pin_AA, abc[1] to Pin_AB, and abc[2] to Pin_AC To set the pin assignment for a clock, use the name of the Clock block (for example, the default is clock) for the pin name. For example: Pin Name: clock Pin Location: Pin_AM17 To set the pin assignment for a reset, use the name of the reset signal specified in the Clock block (for example the default global reset is aclr) for the pin name. For example: Pin Name: aclr Pin Location: Pin_B4 Table 115 shows the Quartus II Pinout Assignments block parameters.
Table 115. Quartus II Pinout Assignments Block Parameters Name Pin Name Pin Location Value String String Description The pin name must be the exact instance name of the Input or Output block from the IO & Bus library. Pin location value of the FPGA IO. Refer to the Quartus II Help for the pinout values of a device.
Resource Usage
Use the Resource Usage block to check the hardware resources, display timing information, and highlight the critical paths in your design. 1 You must save your model file and run Signal Compiler before you can use the Resource Usage block. The Resource Usage block displays an estimate of the logic, block RAM and DSP blocks resources required by your design.
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You can double-click on the Resource Usage block to display more information about the blocks in your design that generate hardware. f The information that displays depends on the selected device family. Refer to the device documentation for more information. Select the Timing tab and click Highlight path to highlight the critical paths on your design. 1 When the source and destination in the dialog box are the same and you highlight a single block, the critical path is because of the internal function or a feedback loop.
Signal Compiler
Use the Signal Compiler block to create and compile a Quartus II project for your DSP Builder design, and to program your design onto an Altera FPGA. 1 You must save your model file before you can use the Signal Compiler block. Table 116 shows the controls and parameters for the Signal Compiler block.
Table 116. Signal Compiler Block Parameters Settings Page Name Family
Value Stratix , Stratix GX, Stratix II, Stratix II GX, Stratix III, Stratix IV, Arria GX, Arria II GX, Cyclone, Cyclone II, Cyclone III On or Off List of ports connected to the JTAG cable.
Description The Altera device family you want to target. If you use the automated design flow, the Quartus II software automatically uses the smallest device in which your design fits.
Use Board Block to Specify Device Compile Scan JTAG Program Analyze Synthesis Fitter
Turn on to get the device information from the development board block. Click to compile your design. The required JTAG cable port. Click to download your design to the connected development board. Click to analyze the DSP Builder system. Click to run Quartus II synthesis. Click to run the Quartus II Fitter tool. Turn on to enable use of a SignalTap II Logic Analyzer block in your design. Turn on this setting to add extra logic and memory to capture signals in hardware in real time. The required depth for the SignalTap II Logic Analyzer. Specifies the clock to use for capturing data with the SignalTap II feature from a list of available signals. Turn on if you want to use the base clock for the SignalTap II Logic Analyzer. Exports synthesizable HDL to a user-specified directory.
2, 4, 8, 16, 32, 64, 128, 256, 512, 1k, 2K, 4K, 8K User defined On or Off
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Use a Clock or Clock_Derived block to specify the clock and reset signals.
SignalTap Nodes List of SignalTap II node blocks. Change Dont Care, High, Low, Rising Edge, Falling Edge, Either Edge
For detailed instructions on with the SignalTap II Logic Analyzer and SignalTap II Node blocks, refer to the Performing SignalTap II Logic Analysis chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook.
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Figure 15 shows an example with the SignalTap II Node block and the SignalTap II Logic Analyzer block.
Figure 15. Example SignalTap II Analysis Model
SignalTap II Node
Use the SignalTap II Node block with the SignalTap II Logic Analyzer block to capture signal activity from internal Altera device nodes while the system under test runs at speed. The SignalTap II Node block specifies the signals (also called nodes) for which you want to capture activity. The SignalTap II Node block has no parameters. For an example of a design with the SignalTap II Logic Node block, refer to the description of the SignalTap II Logic Analyzer block. f Refer to the Performing SignalTap II Logic Analysis chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook.
Subsystem Builder
The Subsystem Builder block allows you to build black-box subsystems that synthesize user-supplied VHDL and simulate non-DSP Builder Simulink blocks. This alternative to HDL import gives better simulation speed. You can also use this block if you cannot use HDL import because of unsupported megafunctions or LPMs. The subsystem connects the inputs and outputs in the specified VHDL to HDL Input and HDL Output blocks and creates an HDL Entity block, which you can modify if the clock and reset signals are not correctly identified.
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The Subsystem Builder block automatically maps any input ports named simulink_clock in the VHDL entity section to the global VHDL clock signal, and maps any input ports named simulink_sclr in the VHDL entity section to the global VHDL synchronous clear signal. The VHDL entity should be formatted according to the following guidelines:
The VHDL file should contain a single entity Port direction: in or out Port type: STD_LOGIC or STD_LOGIC_VECTOR Bus size:
a(7 DOWNTO 0) is supported (0 is the LSB, and must be 0) a(8 DOWNTO 1) is not supported a(0 TO 7) is not supported
The Verilog HDL module should be formatted according to the following guidelines:
The Verilog HDL file should contain a single module Port direction: input or output Bus size:
input [7:0] a; is correct (0 is the LSB, and must be 0) input [8:1] a; is not supported input [0:7] a; is not supported
To use the Subsystem Builder block, drag and drop it into your model, click Select HDL File, specify the file to import, and click Build. Table 118 shows the Subsystem Builder block parameters.
Table 118. Subsystem Builder Block Parameters Name Select HDL File Build SubSystem Value Description Click to build a subsystem for the selected HDL file.
User defined Browse for the VHDL or Verilog HDL file to import.
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TestBench
The TestBench block controls the generation of a testbench. If the ModelSim executable (vsim.exe) is available on your path, you can load the testbench into ModelSim and compare the results with Simulink. Input and output vectors are generated when you use the Compare against HDL option in the Simple tab or Run Simulink in the Advanced tab. You can optionally launch the ModelSim GUI to visually view the ModelSim simulation. 1 Enabling testbench generation may slow simulation as all input and output values are stored to a file. Table 119 shows the TestBench block parameters.
Table 119. TestBench Block Parameters Name Compare against HDL Generate HDL Run Simulink Run ModelSim Launch GUI Compare Results Mark ModelSim Unknowns (Xs) as Maximum number of mismatches to display Value On or Off Error, Warning, Info >=0 Default = 10 Description Turn on to enable automatic testbench generation. Click to generate HDL, run Simulink and compare the Simulink simulation results with ModelSim. Click to generate a VHDL testbench from the Simulink model. Re-run the Simulink simulation. Load the testbench into the ModelSim simulator. Turn on to launch the ModelSim graphical user interface. Compare the Simulink and ModelSim results. Display ModelSim unknown values as error, warning, or info messages. Errors display in red; warnings in blue; info in green. Specify the maximum number of mismatches to display.
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VCD Sink
The VCD Sink block exports Simulink signals to a third-party waveform viewer. When you run the simulation of your model, the VCD Sink block generates a value change dump (.vcd) <VCD Sink block name>.vcd file, which a third-party waveform viewer can read. To use the VCD Sink block in your Simulink model, perform the following steps: 1. Add a VCD Sink block to your Simulink model. 2. Connect the simulink signals you want to display in a third-party waveform viewer to the VCD Sink block. 3. Run the Simulink simulation. 4. Read the VCD file in the third-party waveform viewer. If you use the ModelSim software to view waveforms, run the script <VCD Sink block path>_vcd.tcl where the path is the hierarchical path of the block in the Simulink model. That is: <model name>_<subsystem names>_<block name> each separated by underscore character. This Tcl script converts VCD files to ModelSim waveform format (.wlf), starts the waveform viewer, and displays the signals. If you use any other third-party viewer, load the VCD file directly into the viewer. The VCD Sink block does not have any hardware representation and therefore does not appear in the VHDL RTL representation created by the Signal Compiler block. Table 120 shows the parameters for the VCD Sink block.
Table 120. VCD Sink Block Parameters Name Number of Inputs Value Description
An integer greater than 0 Specify the number of input ports on the VCD Sink block.
2. Arithmetic Library
The Arithmetic library contains twos complement signed arithmetic blocks such as multipliers and adders. Some blocks have a Use Dedicated Circuitry option, which implements functionality into dedicated hardware in the Altera FPGA devices (that is, in the dedicated DSP blocks of these devices). The Arithmetic library contains the following blocks:
Barrel Shifter Bit Level Sum of Products Comparator Counter Differentiator Divider DSP Gain Increment Decrement Integrator Magnitude Multiplier Multiply Accumulate Multiply Add Parallel Adder Subtractor Pipelined Adder Product SOP Tap Square Root Sum of Products
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Barrel Shifter
The Barrel Shifter block shifts the input data a by the amount set by the distance bus. The Barrel Shifter block can shift data to the left (toward the MSB) or to the right (toward the LSB). The Barrel Shifter block shift data to the left only, or to the right only, or in the direction specified by the optional direction input. The shifting operation is an arithmetic shift and not a logical shift; that is, the shifting operation preserves the input data sign for a right shift although the input sign is lost for a left shift. Table 21 shows the Barrel Shifter block inputs and outputs.
Table 21. Barrel Shifter Block Inputs and Outputs
Direction Input Input Input Input Input Output Data input. Distance to shift.
Description
Direction to shift (0 = shift left, 1 = shift right). Optional clock enable. Optional asynchronous clear. Result after shift.
[number of bits].[] [].[number of bits] Enable Pipeline Infer size of distance port from input port Bit width of distance port Shift Direction Use Enable Port Use asynchronous Clear Port
>= 0 (Parameterizable) Specify the number of bits to the left of the binary point. >= 0 (Parameterizable) Specify the number of bits to the right of the binary point. This field is zero (0) unless Signed Fractional is selected. On or Off On or Off Turn on to pipeline the barrel shifter with a latency of 3. Enabling pipeline, increases latency and may increase the fMAX of your design. Turn off to specify the bit width of the distance port. When on, the design uses the full input bus width.
>= 0 (Parameterizable) Specify the width in bits of the distance port. Defaults to the size of the input port. Shift Left, Shift Right, The direction you want to shift the bits or specify the direction with the Use direction input pin direction input. On or Off On or Off Turn on to use the clock enable input (ena). Turn on to enable the asynchronous clear input. This option is available only when the pipeline option is enabled. If you target devices that support DSP blocks, turn on to implement the functionality in DSP blocks instead of logic elements.
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I/O I
VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) I2: in STD_LOGIC_VECTOR({L2 + R2 - 1} DOWNTO 0) I3: in STD_LOGIC O1: out STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0
O1[L1].[R1]
q is the output result a(i) is the one-bit input data Ci are the signed integer fixed coefficients n is the number of coefficients in the range one to eight
Table 24 on page 24 shows the Bit Level Sum of Products block inputs and outputs.
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Table 24. Bit Level Sum of Products Block Inputs and Outputs Signal Direction Description 1 to 8 ports corresponding to the signed integer fixed coefficient values specified in the block parameters. Optional clock enable. Optional synchronous clear. Result.
Table 26 shows the Bit Level Sum of Products block I/O formats.
Table 26. Bit Level Sum of Products Block I/O Formats I/O I ... Ii[1].[0] ... In[1].[0] I(n+1)[1] I(n+2)[1] O O1[L0].[0]
Notes to Table 26:
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit. (2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit. (3) I1[L].[R] is an input port. O1[L].[R] is an output port. (4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
Simulink (2), (3) I1[1].[0] I1: in STD_LOGIC ... Ii: in STD_LOGIC ... In: in STD_LOGIC I(n+1): in STD_LOGIC I(n+2): in STD_LOGIC
Explicit
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Figure 22 shows an example with the Bit Level Sum of Products block.
Figure 22. Bit Level Sum of Products Block Example
Comparator
The Comparator block compares two Simulink signals and returns a single bit. The Comparator block implicitly understands the input data type (for example, signed binary or unsigned integer) and produces a single-bit output. Table 27 shows the Comparator block inputs and outputs.
Table 27. Comparator Block Inputs and Outputs Signal a b <unnamed> Direction Input Input Output Operand a. Operand b. Result. Description
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Table 29. Comparator Block I/O Formats (Part 2 of 2) (Note 1) I/O O Simulink (2), (3) O1[1] O1: out STD_LOGIC VHDL Type (4) Implicit
Counter
The Counter block is an up/down counter. For each cycle, the counter increments or decrements its output by the smallest amount that DSP Builder can represent with the selected bus type. Table 210 shows the Counter block inputs and outputs.
Table 210. Counter Block Inputs and Outputs Signal data sload sset updown clk_ena ena sclr q Direction Input Input Input Input Input Input Input Output Optional parallel data input. Optional synchronous load signal. Optional synchronous set port. (Loads the specified constant value into the counter.) Optional direction (1 = up; 0 = down). Optional clock enable. (Disables counting and sload, sset, sclr signals.) Optional counter enable. (Disables counting but not sload, sset, and sclr signals.) Optional synchronous clear. (Loads zero into the counter.) Result. Description
27
Table 211. Counter Block Parameters (Part 2 of 2) Name [].[number of bits] Use Modulo Count Modulo Specify Clock Clock Counter Direction Use Synchronous Load Ports Use Synchronous Set Port Set Value Use Clock Enable Port Use Counter Enable Port Use Synchronous Clear Port Value >= 0 (Parameterizable) On or Off User defined (Parameterizable) On or Off User defined Increment, Decrement, Use Direction Port (updown) On or Off On or Off User defined On or Off On or Off On or Off Description Specify the number of bits to the right of the binary point. This field is ignored unless Signed Fractional selected. Turn on to enable the Count Modulo parameter. This option is not available for bit widths greater than 31. Specify the maximum count plus 1. This represents the number of unique states in the counters cycle. Turn on to explicitly specify the clock name. Specify the clock signal name. The direction you want to count or specify the direction with the direction input. Turn on to use the synchronous load inputs (data, sload). Turn on to use the synchronous set input (sset). This option is not available for bit widths greater than 31. Specify the constant value loaded when the design uses the sset input. This value must be less than the Count Modulo value (if used). Turn on to use the clock enable input (clk_ena). Turn on to use the counter enable input (ena). Turn on to use the synchronous clear input (sclr).
I1: in STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0) I2: in STD_LOGIC I3: in STD_LOGIC I4: in STD_LOGIC I5: in STD_LOGIC I6: in STD_LOGIC O1: out STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0)
Explicit
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Differentiator
The Differentiator block is a signed integer differentiator with the equation: q(n) = d(n) - d(n-D) where D is the delay parameter. Use this block for DSP functions such as CIC filters. The equation 1-z-D describes the transfer function that the Differentiator block implements. Table 213 shows the Differentiator block inputs and outputs.
Table 213. Differentiator Block Inputs and Outputs Signal d ena sclr q Direction Input Input Input Output Data input. Optional clock enable. Optional synchronous clear. Result. Description
I1: in STD_LOGIC_VECTOR({L1 - 1} DOWNTO 0) I2: in STD_LOGIC I3: in STD_LOGIC O1: out STD_LOGIC_VECTOR({L1 - 1} DOWNTO 0)
Explicit
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Divider
The Divider block takes a numerator and a denominator and returns the quotient and a remainder with the equation: a = b q + r. q and r are undefined if b is zero. 1 Dividing a maximally negative number by a minimally negative one (-1 if using signed integers), outputs a truncated answer. The numerator and denominator inputs can have different widths but convert to the specified bit width. Table 216 shows the Divider block inputs and outputs.
Table 216. Divider Block Inputs and Outputs Signal a b ena aclr q r Direction Input Input Input Input Output Output Numerator. Denominator. Optional clock enable. Optional asynchronous clear. Quotient. Remainder. Description
[number of bits].[]
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Table 217. Divider Block Parameters (Part 2 of 2) Name [].[number of bits] Number of Pipeline Stages Use Enable Port Use Asynchronous Clear Port Value >= 0 (Parameterizable) 0 to number of bits (Parameterizable) On or Off On or Off Description Specify the number of bits to the right of the binary point. This option applies only to signed fractional formats. When non-zero, adds pipeline stages to increase the data throughput. The clock enable and asynchronous clear ports are available only if the block is registered (that is, if the number of pipeline stages is greater than or equal to 1). Turn on to use the clock enable input (ena). Turn on to use the asynchronous clear input (aclr).
I/O I
VHDL I1: in STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0) I2: in STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0) I3: in STD_LOGIC I4: in STD_LOGIC O1: out STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0) O2: out STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0)
O1[L].[R] O2[L].[R]
Explicit Explicit
DSP
The DSP block consists of one to four multipliers feeding a parallel adder. It is equivalent to the Multiply Add block but exposes extra features (including chaining) that are available only on Stratix IV and Stratix III DSP blocks. The DSP block accepts one to four pairs of multiplier inputs a and b. The operands in each pair are multiplied together. The second and fourth multiplier outputs can optionally be added or subtracted from the total.
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The following equation expresses the block function: res = a0b0 a1b1 [+ a2b2 [ a3b3]] [+ chainin] If there are four multipliers and the input bit widths are both less than or equal to 18, you can optionally enable a chainout adder output (chainout) instead of the normal output (res). If there are four multipliers and the input bit widths are both equal to 18, you can enable a chainout adder input (chainin). Only drive this chainin port from the chainout output of a DSP block at the preceding stage. Other features include:
Parameterizable input and output data widths Optional asynchronous clear and clock enable inputs Optional accumulator synchronous load input Optional shiftin instead of an a input Optional shift out from the a input of the last multiplier Optional saturation overflow outputs Optional registers to pipeline the adder and chainout adder Optional accumulator mode
For more information about multiplier or adder operations, refer to the altmult_add Megafunction User Guide. Table 219 shows the DSP block inputs and outputs.
Table 219. DSP Block Inputs and Outputs Signal a0a3 b0b3 ena chainin aclr accum_sload res shiftouta overflow chainout
Note to Table 219:
(1) Use the chainin port to feed the adder result (chainout) from a previous stage. Do not use for any other signal.
Direction Input Input Input Input Input Input Output Output Output Output Operand a. Operand b. Optional clock enable.
Description
Optional input bus from the preceding stage. (1) Optional reset to zero for the chainout value. Optional asynchronous clear. Optional accumulator synchronous load input. Result. Optional shift out from A input of last multiplier. Optional saturation overflow output. Optional chainout output. (Replaces the res output when enabled.)
zero_chainout Input
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Figure 26 shows a basic multiplier or adder with two inputs where the product is subtracted.
Figure 26. Basic 2-Input Multiplier or Adder
Figure 27 shows a 4-input multiplier or adder with shiftin inputs, registered outputs, rounding and saturation enabled, a chainout adder and saturation overflow outputs.
Figure 27. 4-Input Multiplier or Adder with Chainout Adder
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a Inputs [number of bits].[] >= 0 Specify the number of data a input bits to the left of the binary point, (Parameterizable) including the sign bit. a Inputs [].[number of bits] >= 0 Specify the number of data a input bits to the right of the binary point. (Parameterizable) This option applies only to signed fractional formats. b Inputs [number of bits].[] >= 0 Specify the number of data b input bits to the left of the binary point, (Parameterizable) including the sign bit. b Inputs [].[number of bits] >= 0 Specify the number of data b input bits to the right of the binary point. (Parameterizable) This option applies only to signed fractional formats. Connect Multiplier Input a to shiftin Use Shiftout from a Input of Last Multiplier Output Operation on First Multiplier Pair Output Operation on Second Multiplier Pair Enable Accumulator Mode On or Off On or Off ADD, SUB ADD, SUB On or Off Turn on to connect the multiplier input a to shiftin from the previous multiplier. The design uses separate inputs for each multiplier.) Turn on to create a shiftouta output from the a input of the last multiplier. Add or subtract the product of the first multiplier pair. Add or subtract the product of the second multiplier pair. Turn on to enable accumulator mode. When this option is on, you can select the accumulator direction and use the optional accum_sload input. Add or subtract values in the accumulator. Turn on to use the optional accum_sload input. Turn on to use the chainin input for the chainout adder to add the result from a previous stage. This option is available only if the input bit widths are less than or equal to 18 and the number of multipliers is 4. Turn on to use the chainout output from the chainout adder output instead of the res output. This option is available only if the input bit widths are less than or equal to 18 and the number of multipliers is 4. Turn on to use the zero_chainout input, which dynamically sets the chainout value to zero. When on, the multiplier output bit width is full resolution. When off, you can specify a different output width. Rounding and saturation are available for certain input/output type combinations.
Accumulator Direction Use Accumulator Synchronous Load Input Use Chainout Adder Input (chainin) Use Chainout Adder Output (chainout) Use Zero Chainout Input Full Resolution for Output Result Output [number of bits].[] Output [].[number of bits] Output Rounding Operation Type
On or Off
On or Off On or Off
Specify the number of data output bits to the left of the binary point, >= 0 (Parameterizable) including the sign bit. >= 0 Specify the number of data output bits to the right of the binary point. (Parameterizable) This option applies only to signed fractional formats. None (truncate), Nearest Integer, Nearest Even You can disable rounding (truncate), round to the nearest integer or round to the nearest even.
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Table 220. DSP Block Parameters (Part 2 of 2) Name Output Saturation Operation Type Value None (wrap), Symmetric, Asymmetric Description You can disable (wrap), or enable saturation. Symmetric saturation specifies that the absolute value of the maximum negative number is equal to the maximum positive number. Asymmetric saturation specifies that the absolute value of the maximum negative number is 1 greater than the maximum positive number. Do not enable rounding unless you have enabled saturation. Turn on to use the overflow output for the saturation unit. Turn on to create registers at the data inputs to the multiplier. (Always on if in shiftin mode.) Turn on to create a register at the data output from the multiplier. Turn on to create a register at the output of the adder. (Always on if accumulator mode is enabled.) Turn on to create a register at the output of the chainout adder (if it is used). Registers the shiftouta output (if it is used). Turn on to use the clock enable input (ena) if using registers. Turn on to use the asynchronous clear input (aclr) if using registers.
Use Output Overflow Port Register Data Inputs to the Multiplier(s) Register Output of the Multiplier Register Output of the Adder Register Chainout Adder Register Shiftout Use Enable Port Use User Asynchronous Clear Port
Compilation in the Quartus II software requires that the input bit widths are 18 bits when you use the chainout adder input, output rounding with an output LSB in the range 6 to 21, or output saturation with an output MSB in the range 28 to 43. Table 221 shows the DSP block I/O formats.
Table 221. DSP Block I/O Formats I/O I . In[L1].[R1] I(n+1)[1] I(n+2)[1] where 3 < n < 9 O O12 x [L1]+ ceil(log2(n)).2 x
[R1]
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) In: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) I(n+1): in STD_LOGIC I(n+2): in STD_LOGIC where 3 < n < 9
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Figure 28 shows an example of a basic low-pass filter with two DSP blocks.
Figure 28. DSP Block Example
Gain
The Gain block generates its output by multiplying the signal input by a specified gain factor. You must enter the gain as a numeric value in the Gain block parameter field. The gain factor must be a scalar. 1 The Simulink software also provides a Gain block. If you use the Simulink Gain block in your model, you can use it only for simulation; Signal Compiler cannot convert it to HDL. Table 222 shows the Gain block inputs and outputs.
Table 222. Gain Block Inputs and Outputs Signal d ena aclr <unnamed> Direction Input Input Input Output Data input. Optional clock enable. Optional asynchronous clear. Result. Description
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Signed Integer, The bus number format you want to use for the gain value. Signed Fractional, Unsigned Integer
[Gain value number of bits].[] >= 0 Specify the number of bits to the left of the binary point, including the (Parameterizable) sign bit. [].[Gain value number of bits] >= 0 Specify the number of bits to the right of the binary point. This option (Parameterizable) applies only to signed fractional formats. Number of Pipeline Stages >= 0 The number of pipeline delay stages. The Clock Phase Selection and (Parameterizable) Optional Ports options are available only if the block is registered (that is, if the number of pipeline stages is greater than or equal to 1). User Defined Specify the phase selection with a binary string, where a 1 indicates the phase in which the block is enabled. For example: 1The block is always enabled and captures all data passing through the block (sampled at the rate 1). 10The block is enabled every other phase and every other data (sampled at the rate 1) passes through. 0100The block is enabled on the second phase of and only the second data of (sampled at the rate 1) passes through. That is, the data on phases 1, 3, and 4 do not pass through the block. Use Enable Port Use LPM On or Off On or Off Turn on to use the clock enable input (ena). Turn on to use the asynchronous clear input (aclr). This parameter is for synthesis. When on, the Gain block is mapped to the LPM_MULT library of parameterized modules (LPM) function and the VHDL synthesis tool uses the Altera LPM_MULT implementation. Use Asynchronous Clear Port On or Off
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Table 224. Gain Block I/O Formats (Part 2 of 2) (Note 1) I/O O Simulink (2), (3) O1[L1 + LK].2*max(R1,RK)] (5) VHDL O1: out STD_LOGIC_VECTOR({L1+LK+2*max(R1,RK)-1} DOWNTO 0) Type Implicit
Increment Decrement
The Increment Decrement block increments or decrements a value in time. The output is a signed integer, unsigned integer, or signed binary fractional number. For all number formats, the counting sequence increases or decreases by the smallest representable value; for integer types, the value always changes by 1. Table 225 shows the Increment Decrement block inputs and outputs.
Table 225. Increment Decrement Block Inputs and Outputs Signal ena sclr c Direction Input Input Output Optional clock enable. Optional synchronous clear. Result. Description
Signed Integer, The number format you want to use for the bus. Signed Fractional, Unsigned Integer
<number of bits>.[] >= 0 Select the number of bits to the left of the binary point, including the sign bit. (Parameterizable) [].<number of bits> >= 0 Select the number of bits to the right of the binary point. This option applies only (Parameterizable) to signed fractional formats.
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Table 226. Increment Decrement Block Parameters (Part 2 of 2) Name Direction Starting Value Clock Phase Selection Value Increment, Decrement Count up or down. Description
User Defined Enter the value with which to begin counting. This value is the initial output value (Parameterizable) of the block after a reset. User Defined Specify the phase selection with a binary string, where a 1 indicates the phase in which the block is enabled. For example: 1The block is always enabled and captures all data passing through the block (sampled at the rate 1). 10The block is enabled every other phase and every other data (sampled at the rate 1) passes through. 0100The block is enabled on the second phase of and only the second data of (sampled at the rate 1) passes through. That is, the data on phases 1, 3, and 4 do not pass through the block.
Specify Clock Clock Use Enable Port Use Synchronous Clear Port
Turn on to explicitly specify the clock name. Specify the clock signal name. Turn on if you want to use the clock enable input (ena). Turn on if you want to use the synchronous clear input (sclr).
Type (4)
Explicit
219
Integrator
The Integrator block is a signed integer integrator with the equation: q(n+D) = q(n) + d(n) where D is the delay parameter. Use this block for DSP functions such as CIC filters. The equation z-D/(1-z-D) describes the transfer function that the Integrator block implements. This behavior of this transfer function is slightly different from the more typical 1/(1-z-D). Figure 211 shows the block diagrams for these functions.
Figure 211. Integrator Transfer Functions
The magnitude response of these two functions is the same although their phase response is different. For the typical integrator function, 1/(1-z-D), there is an impulse on the output at time = 0, whereas the output delays by a factor of D for the z-D/(1-z-D) function that the DSP Builder integrator uses. This behavior effectively registers the output and gives a better Fmax performance compared to the typical function where if you chained a row of n integrators together, it is equivalent to n unregistered adder blocks in a row, and is slow in hardware. Table 228 shows the Integrator block inputs and outputs.
Table 228. Integrator Block Inputs and Outputs Signal d ena sclr q Direction Input Input Input Output Data input. Optional clock enable. Optional synchronous clear. Result. Description
220
Table 229. Integrator Block Parameters Name Use Enable Port Value On or Off Description Turn on to use the clock enable input (ena). Turn on to use the synchronous clear input (sclr).
I1: in STD_LOGIC_VECTOR({L1 - 1} DOWNTO 0) I2: STD_LOGIC I3: STD_LOGIC O1: out STD_LOGIC_VECTOR({L1 - 1} DOWNTO 0)
Explicit
Magnitude
The scalar Magnitude block returns the absolute value of the incoming signed binary fractional bus. The Magnitude block has no parameters. Table 231 shows the Magnitude block I/O formats.
Table 231. Magnitude Block I/O Formats (Part 1 of 2) (Note 1) I/O I Simulink (2), (3) I1[L1].[R1] VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) Type (4) Implicit
221
Table 231. Magnitude Block I/O Formats (Part 2 of 2) (Note 1) I/O O Simulink (2), (3) O1[L1].[R1] VHDL O1: out STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) Type (4) Implicit
Multiplier
The Multiplier block supports two scalar inputs (no multidimensional Simulink signals). Operand a is multiplied by operand b and the result r output as the following equation shows: r=ab The differences between the Multiplier block and the Product block are:
The Product block supports clock phase selection while the Multiplier block does not. The Product block uses implicit input port data widths that it inherits from the signals sources, whereas the Multiplier block uses explicit input port data widths that you must specify as parameters. The Product block allows you to use the LPM multiplier megafunction, whereas the Multiplier block always uses the LPM.
222
Specify the number of bits to the left of the binary point for input a (or both input signals if set to have the same width). Specify the number of bits to the right of the binary point for input a (or both input signals if set to have the same width). This option applies only to signed fractional formats. The number of pipeline stages. The ena and aclr ports are available only if the block is registered (that is, if the number of pipeline stages is greater than or equal to 1). Turn on if you want input a and input b to have the same bit width. When off, additional fields are available to specify the number of bits to the left and right of the binary point for input b. Specify the number of bits to the left of the binary point for input b. Specify the number of bits to the right of the binary point for input b. This option applies only to signed fractional formats. When on, the multiplier output bit width is full resolution. When off, you can specify the number of bits for the output. Specify the number of MSBs in the output for an integer bus. Specify the number of LSBs in the output for an integer bus. Specify the number of bits to the left of the binary point for the output r. This option applies only to signed fractional formats. Specify the number of bits to the left of the binary point for the output r. This option applies only to signed fractional formats. Use dedicated multiplier circuitry (if supported by your target device). A value of AUTO means that the Quartus II software uses the dedicated multiplier circuitry based on the width of the multiplier. Turn on to use the clock enable input (ena). Turn on to use the synchronous clear input (aclr).
Both Inputs Have Same Bit Width Input b [number of bits].[] Input b [].[number of bits] Full Resolution for Output Result Output MSB Output LSB Output [number of bits].[] Output [].[number of bits] Use Dedicated Circuitry
>= 0 (Parameterizable) >= 0 (Parameterizable) On or Off >= 0 (Parameterizable) >= 0 (Parameterizable) >= 0 (Parameterizable) >= 0 (Parameterizable) AUTO, YES, NO
On or Off On or Off
223
Table 234. Multiplier Block Input/Output Ports (Note 1) I/O I Simulink (2), (3) I1[L].[R] I2[L].[R] I3[1] I4[1] O O1[Lo].[Ro] O2[Lo].[Ro]
Notes to Table 234:
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit. (2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit. (3) I1[L].[R] is an input port. O1[L].[R] is an output port. (4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
VHDL I1: in STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0) I2: in STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0) I3: STD_LOGIC I4: STD_LOGIC O1: out STD_LOGIC_VECTOR({Lo + Ro - 1} DOWNTO 0) O2: out STD_LOGIC_VECTOR({Lo + Ro - 1} DOWNTO 0)
Explicit Explicit
For more information about multiplier operations, refer to the Multiplier Megafunction User Guide.
Multiply Accumulate
The Multiply Accumulate block consists of a single multiplier feeding an accumulator, which performs the calculation y += a b. The input is signed integer, unsigned integer, or signed binary fractional formats. Table 235 shows the Multiply Accumulate block inputs and outputs.
Table 235. Multiply Accumulate Block Inputs and Outputs (Part 1 of 2) Signal a b sload addsub Direction Input Input Input Input Operand A. Operand B. Synchronous load signal. Optional accumulator direction (1= add, 0 = subtract). Description
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Table 235. Multiply Accumulate Block Inputs and Outputs (Part 2 of 2) Signal ena aclr y Direction Input Input Output Optional clock enable. Optional asynchronous clear. Result. Description
Input A [number of bits].[] >= 0 (Parameterizable) Input A [].[number of bits] >= 0 (Parameterizable) Input B [number of bits].[] >= 0 (Parameterizable) Input B [].[number of bits] >= 0 (Parameterizable) Output Result number of bits Pipeline Register >= 0 (Parameterizable) None, Data Inputs, Multiplier Output, Data Inputs and Multiplier AUTO, YES, NO
Specify the number of data input bits to the left of the binary point for operand A, including the sign bit. Specify the number of data input bits to the right of the binary point for operand A. This option applies only to signed fractional formats. Specify the number of data input bits to the left of the binary point for operand B, including the sign bit. Specify the number of data input bits to the right of the binary point for operand B. This option applies only to signed fractional formats. Specify the number of output bits. Add pipelining to the data inputs, multiplier output, both, or neither.
Select AUTO to automatically implement the functionality in DSP blocks. Select YES or NO to explicitly enable or disable this option. If your target device does not support DSP blocks or you select NO, the functionality implements in logic elements. Add or subtract the result of the multiplier. Turn on to use the direction input (addsub). Turn on to use the clock enable input (ena). Turn on to use the asynchronous clear input (aclr).
Accumulator Direction Use Add/Subtract Port Use Enable Port Use Asynchronous Clear Port
225
Table 237. Multiply Accumulate Block I/O Formats (Note 1) I/O I Simulink (2), (3) I1[L1].[R1] I2[L2].[R2] I3[1] I4[1] I5[1] I6[1] O O1[LO].[RO]
Notes to Table 237:
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit. (2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit. (3) I1[L].[R] is an input port. O1[L].[R] is an output port. (4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) I2: in STD_LOGIC_VECTOR({L2 + R2 - 1} DOWNTO 0) I3: in STD_LOGIC I4: in STD_LOGIC I5: in STD_LOGIC I6: in STD_LOGIC O1: out STD_LOGIC_VECTOR({L0 + R0 - 1} DOWNTO 0)
Explicit
The sload input controls the accumulator feedback path. If the accumulator is adding and sload is high, the multiplier output is loaded into the accumulator. If the accumulator is subtracting, the opposite (negative value) of the multiplier output is loaded into the accumulator. Figure 215 shows an example with the Multiply Accumulate block.
Figure 215. Multiply Accumulate Block Example
Multiply Add
The Multiply Add block consists of two, three, or four multiplier pairs feeding a parallel adder. The operands in each pair are multiplied together and the second and fourth multiplier outputs can optionally be added to or subtracted from the total. The following equation expresses the block function: y = a0b0 a1b1 [+ a2b2 [ a3b3]]] The operand b inputs can optionally be hidden and instead have constant values assigned in the Block Parameters dialog box. The input is a signed integer, unsigned integer, or signed binary fractional formats. Table 238 shows the Multiply Add block inputs and outputs.
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Table 238. Multiply Add Block Inputs and Outputs Signal a0a3 b0b3 ena aclr y Direction Input Input Input Input Output Operand a. Operand b. Optional clock enable. Optional asynchronous clear Result. Description
Specify the number of data input bits to the left of the binary point, including the sign bit. Specify the number of data input bits to the right of the binary point. This option applies only to signed fractional formats. The operation mode of the adder.
Add Add: Adds the products of each multiplier. Add Sub: Adds the second product and subtracts the fourth. Sub Add: Subtracts the second product and adds the fourth. Sub Sub: Subtracts the second and fourth products.
Pipeline Register
No Register, Inputs Only, The elements to pipeline. The clock enable and asynchronous clear Multiplier Only, Adder Only, ports are available only if the block is registered. Inputs and Multiplier, Inputs and Adder, Multiplier and Adder, Inputs Multiplier and Adder On or Off If you target devices that support DSP blocks, turn on to implement the functionality in DSP blocks instead of with logic elements. This option is not available if you select the Unsigned Integer bus type. Turn on to assign the operand b inputs to constant values. Use this option with the Constant Values parameter but is not available when you enable Use Dedicated Circuitry. Type the constant values in this box as a MATLAB array. This option is available only if One Input is Constant is on. Turn on to use the clock enable input (ena). Turn on to use the asynchronous clear input (aclr).
On or Off
227
Table 240. Multiply Add Block I/O Formats I/O I . Ii[L1].[R1] In[L1].[R1] I(n+1)[1] I(n+2)[1] where 3 < n < 9 O O12 x [L1]+ ceil(log2(n)).2 x
[R1]
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) Ii: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) . In: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) I(n+1): in STD_LOGIC I(n+2): in STD_LOGIC where 3 < n < 9
228
Table 241. Parallel Adder Subtractor Block Inputs and Outputs Signal data0dataN ena aclr r Direction Input Input Input Output Operands. Optional clock enable. Optional asynchronous clear Result. Description
Enable Pipeline
On or Off
Table 243 shows the Parallel Adder Subtractor block I/O formats.
Table 243. Parallel Adder Subtractor Block I/O Formats (Part 1 of 2) (Note 1) I/O I . Ii[Li].[LiI] In[Ln].[Rn] I(n+1)[1] I(n+2)[1] Simulink (2), (3) I1[L1].[R1] Ii: in STD_LOGIC_VECTOR({Li + Ri - 1} DOWNTO 0) . In: in STD_LOGIC_VECTOR({Ln + Rn - 1} DOWNTO 0) I(n+1): in STD_LOGIC I(n+2): in STD_LOGIC VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) Type (4) Implicit ... Implicit ... Implicit
229
Table 243. Parallel Adder Subtractor Block I/O Formats (Part 2 of 2) (Note 1) I/O O Simulink (2), (3) O1[max(Li) +
ceil(log2(n))].[max(Ri)]
VHDL
Type (4)
Figure 217 shows an example with the Parallel Adder Subtractor block.
Figure 217. Parallel Adder Subtractor Block Example
Pipelined Adder
The Pipelined Adder block is a pipelined adder and subtractor that performs the following calculation: r = a + b + cin (when addsub = 1) r = a - b + cin -1 (when addsub = 0) Use the optional ovl port an overflow with signed arithmetic or as a carry out with unsigned arithmetic. For unsigned subtraction, the output is 1 when no overflow occurs. Table 244 shows the Pipelined Adder block inputs and outputs.
Table 244. Pipelined Adder Block Inputs and Outputs Signal a b cin addsub ena aclr r ovl Direction Input Input Input Input Input Input Output Output Operand a. Operand b. Optional carry in. Optional control (1= add, 0 = subtract). Optional clock enable. Optional asynchronous clear. Result r. Optional overflow (signed) or carry out (unsigned). Description
230
[number of bits].[] [].[number of bits] Number of Pipeline Stages Direction Use Enable Port Use Asynchronous Clear Port Use Carry In Port Use Overflow / Carry Out Port Use Direction Port
Specify the number of bits to the left of the binary point. Specify the number of bits to the right of the binary point. This option applies only to signed fractional formats. The number of pipeline stages. Use the block as an adder or subtractor. Turn on to use the clock enable input (ena). Turn on to use the asynchronous clear input (aclr). Turn on to use the carry in input (cin). Turn on to use the overflow or carry out output (ovl). Turn on to use the direction input (addsub). 1= add, 0 = subtract.
VHDL I1: in STD_LOGIC_VECTOR({L + R} DOWNTO 0) I2: in STD_LOGIC_VECTOR({L + R} DOWNTO 0) I3: in STD_LOGIC I4: in STD_LOGIC I5: in STD_LOGIC I6: in STD_LOGIC O1: out STD_LOGIC_VECTOR({L + R} DOWNTO 0) O2: out STD_LOGIC
Explicit
231
Product
The Product block supports two scalar inputs (no multidimensional Simulink signals). Operand a is multiplied by operand b and the result output on r as the following equation shows: r=ab The differences between the Product block and the Multiplier block are:
The Product block supports clock phase selection while the Multiplier block does not. The Product block uses implicit input port data widths that are inherited from the signals sources, whereas the Multiplier block uses explicit input port data widths that you must specify as parameters. The Product block allows you to use the LPM multiplier megafunction, whereas the Multiplier block always uses the LPM.
The Simulink software also provides a Product block. If you use the Simulink Product block in your model, you can use it only for simulation. Signal Compiler issues an error and cannot convert the Simulink Product block to HDL. Table 247 shows the Product block inputs and outputs.
Table 247. Product Block Inputs and Outputs Signal a b ena aclr r Direction Input Input Input Input Output Operand a. Operand b. Optional clock enable. Optional asynchronous clear. Result. Description
232
Table 248. Product Block Parameters Name Bus Type Value Description
Inferred, The bus number format that you want to use. Inferred means that the format is Signed Integer, automatically set by the format of the connected signal. Signed Fractional, Unsigned Integer >= 0 (Parameterizable) >= 0 (Parameterizable) >= 0 (Parameterizable) User Defined Specify the number of bits to the left of the binary point. Specify the number of bits to the right of the binary point. This option applies only to signed fractional formats. The Pipeline represents the delay. The clock enable and asynchronous clear ports are available only if the block is registered (that is, if the number of pipeline stages is greater than or equal to 1). This option is available only when the Pipeline value is greater than 0. Specifies the phase selection with a binary string, where a 1 indicates the phase in which the block is enabled. For example: 1The block is always enabled and captures all data passing through the block (sampled at the rate 1). 10The block is enabled every other phase and every other data (sampled at the rate 1) passes through. 0100The block is enabled on the second phase of and only the second data of (sampled at the rate 1) passes through. That is, the data on phases 1, 3, and 4 do not pass through the block.
[number of bits].[] [].[number of bits] Number of Pipeline Stages Clock Phase Selection
Turn on to use the clock enable input (ena). Turn on to use the asynchronous clear input (aclr). When on, the Product block is mapped to the LPM_MULT library of parameterized modules (LPM) function and the VHDL synthesis tool uses the Altera LPM_MULT implementation. When off, the VHDL synthesis tool uses the native * operator to synthesize the product. If your design does not need arithmetic boundary optimizationsuch as connecting a multiplier to constant combinational logic or register balancing optimizationthe LPM_MULT implementation generally yields a better result for both speed and area.
On or Off
Turn on to use the dedicated multiplier circuitry (if supported by your target device). This option is ignored if not supported by your target device.
233
Table 249. Product Block I/O Formats (Part 2 of 2) (Note 1) I/O O Simulink (2), (3) O1[2max(L1,L2].[2max(R1,
R2)]
VHDL
Type (4)
For more information about multiplier operations, refer to the lpm_mult Megafunction User Guide.
SOP Tap
The SOP Tap block performs a sum of products for two or four taps. Use this block to build two or four tap FIR filters, or cascade blocks to create filters with more taps. The SOP Tap block implements with a multiplier-adder, which has registers on the inputs, multipliers and adders. Thus, the result always lags the input by 3 cycles. The dout port is assigned the value of din(n-t) where t is the number of taps. The block has the following equations: For 2 taps: q(n+3) = c0(n)din(n) + c1(n)din(n-1) dout(n+2) = din(n) For 4 taps: q(n+3) = c0(n)din(n) + c1(n)din(n-1) + c2(n)din(n-2) + c3(n)din(n-3) dout(n+4) = din(n) Table 250 shows the SOP Tap block inputs and outputs.
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Table 250. SOP Tap Block Inputs and Outputs Signal din c0, c1, c2, c3 ena aclr q dout Direction Input Input Input Input Output Output Data input. 2 or 4 tap coefficients. Optional clock enable. Optional asynchronous clear. Result. Shifted input data. Description
>= 0 Specify the number of bits. (Parameterizable) 2 or 4 On or Off The number of taps. Turn on to use the clock enable input (ena). Turn on to use the asynchronous clear input (aclr).
I1: in STD_LOGIC_VECTOR({L + R -1} DOWNTO 0) I2: in STD_LOGIC_VECTOR({L + R -1} DOWNTO 0) ... In: in STD_LOGIC_VECTOR({L + R -1} DOWNTO 0) I(n+1): STD_LOGIC I(n+2): STD_LOGIC
O1: out STD_LOGIC_VECTOR({2L + cell(log2(N + 1)) + 2R - 1} DOWNTO 0) Explicit O2: in STD_LOGIC_VECTOR({L + R -1} DOWNTO 0) Explicit
O2
Notes to Table 252:
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit. (2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit. (3) I1[L].[R] is an input port. O1[L].[R] is an output port. (4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
235
Square Root
The Square Root block returns the square root and optional remainder of unsigned integer input data with the equation: q2 + remainder = d where remainder <= 2 q The Square Root block supports sequential mode (when the number of pipeline stages> 0) or combinational mode (when the number of pipeline stages = 0). Assume the radical d is an unsigned integer, and that q and the remainder are always unsigned integers. Table 253 shows the Square Root block inputs and outputs.
Table 253. Square Root Block Inputs and Outputs Signal d en aclr q remainder Direction Input Input Input Output Output Data input. Optional clock enable. Optional asynchronous clear. Result. Optional remainder. Description
Table 254 lists the parameters for the Square Root block.
Table 254. Square Root Block Parameters (Part 1 of 2) Name Input Number of Bits Number of Pipeline Stages Value Description
>= 0 Specify the number of bits of the unsigned input signal. (Parameterizable) >= 0 Specify the number of pipeline stages. The computation is sequential (Parameterizable) when the pipeline is greater than 1 or combinational when the number of pipeline stages is zero. The clock enable and asynchronous clear ports are available only if the number of pipeline stages is greater than or equal to 1. On or Off Turn on to use the clock enable input (ena).
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Table 254. Square Root Block Parameters (Part 2 of 2) Name Use Remainder Port Value On or Off Description Turn on to use the asynchronous clear input (aclr). Turn on to use the remainder input (remainder).
VHDL I1: in STD_LOGIC_VECTOR({L + R} DOWNTO 0) I2: in STD_LOGIC I3: in STD_LOGIC O1: out STD_LOGIC_VECTOR({L + R} DOWNTO 0) O2: out STD_LOGIC_VECTOR({L + R} DOWNTO 0)
Explicit
Sum of Products
The Sum of Products block implements the following expression: q = a(0)C0 + ... + a(i)Ci + ... + a(n-1)Cn-1 where:
q is the output result a(i) is the signed integer input data Ci are the signed integer fixed coefficients n is the number of coefficients in the range one to eight
Table 256 shows the Sum of Products block inputs and outputs.
237
Table 256. Sum of Products Block Inputs and Outputs Signal Direction Description 1 to 8 ports corresponding to the signed integer fixed coefficient values specified in the block parameters. Optional clock enable. Optional asynchronous clear. Result.
Table 257 lists the parameters for the Sum of Products block.
Table 257. Sum of Products Block Parameters Name Input Data Number of Bits Number of Coefficients Coefficients Number of Bits Signed Integer Fixed-Coefficient Values Number of Pipeline Stages Full Resolution for Output Result >= 0 (Parameterizable) 18 >= 1 (Parameterizable) Vector (Parameterizable) >= 0 (Parameterizable) On or Off When on, the multiplier output bit width is full resolution. When off, you can specify the number of bits in the output signal and the number of least significant bits (LSBs) truncated from the output signal. Specify the number of bits in the output signal. Specify the number of LSBs to be truncated from the output signal. Value Description Specify the number of bits to the left of the binary point of all input signals. The number of coefficients. Specify the number of bits to the left of the binary point of all non-variable coefficients represented as a signed integer. Specify the coefficient values for each port as a sequence of signed integers. For example: [-587 -844 -678 -100 367 362 71 -244] Specify the number of pipeline stages.
Output Number of Bits >= 0 (Parameterizable) Output Truncated LSB FPGA Implementation >= 0 (Parameterizable)
Distributed Arithmetic, Use a distributed arithmetic, dedicated multiplier or automatically Dedicated Multiplier determined implementation. Circuitry, Auto On or Off On or Off Turn on to use the clock enable input (ena). Turn on to use the asynchronous clear input (aclr).
238
Table 258. Sum of Products Block I/O Formats I/O I Simulink (2), (3) I1[L].[0] ... In[L].[0] I(n+1) I(n+2) O O1[2L + cell(log2(n +
1))].[2R]
I1: in STD_LOGIC_VECTOR({L - 1} DOWNTO 0) ... In: in STD_LOGIC_VECTOR({L - 1} DOWNTO 0) I(n+1): STD_LOGIC I(n+2): STD_LOGIC
Like Simulink, DSP Builder supports native complex signal types. Use complex number notation to simplify the design of applications such as FFT, I-Q modulation, and complex filters. The Complex Type library contains the following blocks:
Butterfly Complex AddSub Complex Conjugate Complex Constant Complex Delay Complex Multiplexer Complex Product Complex to Real-Imag Real-Imag to Complex
When connecting DSP Builder blocks to blocks from the Complex Type library (for example, connecting AltBus to Complex AddSub), you must use Real-Imag to Complex or Complex to Real-Imag blocks between the blocks. For an example, refer to Figure 32 on page 35.
32
Butterfly
The Butterfly block performs the following arithmetic operation on complex signed integer numbers: A = a + bW B = a - bW where a, b, W, A, and B are complex numbers (type signed integer) such as: a = x + jX b = y + jY W = v + jV A = (x + yv) - YV + j(X + Yv + yV) B = (x - yv) + YV + j(X - Yv - yV) This function operates with full bit width precision. The full bit width precision of A and B is: 2 [input bit width] + 2. The Output Bit Width and Output Truncated LSB parameters specify the bit slice for the output ports A and B. For example, if the input bit width is 16, the output bit width is 16, and the output LSB is 4, then the full precision is 34 bits and the output ports A[15:0] and B[15:0] each contain the bit slice 19:4. Table 31 shows the Butterfly block inputs and outputs.
Table 31. Butterfly Block Inputs and Outputs Signal a b W ena aclr A B Direction Input Input Input Input Input Output Output Data input a. Data input b. Optional input W. Optional clock enable. Optional asynchronous clear. Data Output A. Data Output B. Description
33
Table 32. Butterfly Block Parameters (Part 2 of 2) Name W (real) W (imaginary) Dedicated Multiplier Circuitry Use Enable Port Use Asynchronous Clear Port Value User defined User defined Auto, Yes, No On or Off On or Off Description Specify the value of the real part of the constant W Specify the value of the imaginary part of the constant W. For devices that support multipliers, a value of Auto specifies that the choice is based on the width of the multiplier. Turn on to use the clock enable input (ena). Turn on to use the asynchronous clear input (aclr).
VHDL I1Real: in STD_LOGIC_VECTOR({Li - 1} DOWNTO 0) I1Imag: in STD_LOGIC_VECTOR({Li - 1} DOWNTO 0) I2Real: in STD_LOGIC_VECTOR({Li - 1} DOWNTO 0) I2Imag: in STD_LOGIC_VECTOR({Li - 1} DOWNTO 0) I3Real: in STD_LOGIC_VECTOR({Li - 1} DOWNTO 0) I3Imag: in STD_LOGIC_VECTOR({Li - 1} DOWNTO 0) I4: in STD_LOGIC I5: in STD_LOGIC O1Real: out STD_LOGIC_VECTOR({Lo - 1} DOWNTO 0) O1Imag: out STD_LOGIC_VECTOR({Lo - 1} DOWNTO 0) O2Real: out STD_LOGIC_VECTOR({Lo - 1} DOWNTO 0) O2Imag: out STD_LOGIC_VECTOR({Lo - 1} DOWNTO 0)
34
Complex AddSub
The Complex AddSub block performs addition or subtraction on a specified number of scalar complex inputs. Table 34 shows the Complex AddSub block inputs and outputs.
Table 34. Complex AddSub Block Inputs and Outputs Signal + or ena aclr R Direction Input Input Input Output Complex inputs. Optional clock enable. Optional asynchronous clear. Result. Description
User defined Specify addition or subtraction operation for each port with the characters + and . For example + + implements +a b + c for three ports. DSP Builder implements the block as a tree of 2-input adders. Each consecutive pair of inputs are + +, + or +. However, none of the input adders can have two consecutive subtractions. Thus, + + is valid (as the two input adders are parameterized + and +), + + + is also valid but + + + is not valid. Missing operators are assumed to be +.
Enable Pipeline
On or Off
When this option is on, DSP Builder registers the output from each stage in the adder tree, resulting in a pipeline length that is equal to ceil(log2(number of inputs)).
User Defined When you enable pipeline, you can specify the phase selection as a binary string, where a 1 indicates the phase in which the block is enabled. For example: 1The block is always enabled and captures all data passing through the block (sampled at the rate 1). 10The block is enabled every other phase and every other data (sampled at the rate 1) passes through. 0100The block is enabled on the second phase of and only the second data of (sampled at the rate 1) passes through. That is, the data on phases 1, 3, and 4 do not pass through the block.
On or Off On or Off
Turn on to use the clock enable input (ena). Turn on to use the asynchronous clear input (aclr).
35
I1Real: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0) I1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0) ... InReal: in STD_LOGIC_VECTOR({LPn + RPn - 1} DOWNTO 0) InImag: in STD_LOGIC_VECTOR({LPn + RPn - 1} DOWNTO 0) I(n+1): in STD_LOGIC I(n+2): in STD_LOGIC O1Real: out STD_LOGIC_VECTOR({max(LI,Ln) + max(RI,Rn)} DOWNTO 0)
Implicit
36
Complex Conjugate
The Complex Conjugate block outputs a fixed-point complex conjugate value by performing simple arithmetic operations on the complex inputs. The operation can optionally be conjugate, negative, or negative conjugate. For an input w = x + iy, the block returns:
Conjugate, Negative, Specify the operation to perform. Negative Conjugate On or Off On or Off On or Off Turn on to register the inputs and to enable the optional clock enable and asynchronous clear options. Turn on to use the clock enable input (ena). Turn on to use the asynchronous clear input (aclr).
VHDL I1Real: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0) I1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0) I2: in STD_LOGIC I3: in STD_LOGIC O1Real: in STD_LOGIC_VECTOR({LP1 + RP1} DOWNTO 0) O1Imag: in STD_LOGIC_VECTOR({LP1 + RP1} DOWNTO 0)
Implicit Implicit
37
Figure 33 shows an example with Complex Conjugate blocks to output conjugate, negative and negative conjugate values.
Figure 33. Complex Conjugate Block Example
38
Complex Constant
The Complex Constant block outputs a fixed-point complex constant value. Table 310 shows the Complex Constant block parameters.
Table 310. Complex Constant Block Parameters Name Real Part Imaginary Part Bus Type Value User Defined User Defined Signed Integer, Signed Fractional, Unsigned Integer Description Specify the value of the real part of the constant. Specify the value of the imaginary part of the constant. Specify the number format of the bus.
[number of bits].[] >= 0 (Parameterizable) [].[number of bits] >= 0 (Parameterizable) Specify Clock Clock On or Off User defined
Specify the number of bits to the left of the binary point, including the sign bit. This parameter does not apply to single-bit buses. Specify the number of bits to the right of the binary point. This parameter applies only to signed fractional buses. Turn on to explicitly specify the clock name. Specify the clock signal name.
Figure 34 shows an example with Complex Constant blocks as inputs to a Complex AddSub block.
Figure 34. Complex Constant Block Example
39
Complex Delay
The Complex Delay block delays the incoming data by an amount specified by the Number of Pipeline Stages parameter. The input must be a complex number. Table 312 shows the Complex Delay block inputs and outputs.
Table 312. Complex Delay Block Inputs and Outputs Signal d ena sclr q Direction Input Input Input Output Input data. Optional clock enable. Optional synchronous clear. Delayed output data. Description
310
Table 314. Complex Delay Block I/O Formats (Part 2 of 2) (Note 1) I/O O Simulink (2), (3) O1Real([L1].[R1])Imag([L1].[R1]) VHDL O1Real: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0) O1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
Notes to Table 314:
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit. (2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit. (3) I1[L].[R] is an input port. O1[L].[R] is an output port. (4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
Complex Multiplexer
The Complex Multiplexer block multiplexes N complex inputs to one complex output. The select port sel is a non-complex scalar. Table 315 shows the Complex Multiplexer block inputs and outputs.
Table 315. Complex Multiplexer Block Inputs and Outputs Signal sel 0 to N1 ena aclr unnamed Direction Input Input Input Input Output Non-complex select line. Complex inputs. Optional clock enable. Optional asynchronous clear. Result. Description
311
I1Real: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0) I1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0) I2Real: in STD_LOGIC_VECTOR({LP2 + RP2 - 1} DOWNTO 0) I2Imag: in STD_LOGIC_VECTOR({LP2 + RP2 - 1} DOWNTO 0) I3: in STD_LOGIC I4: in STD_LOGIC I5: in STD_LOGIC
Implicit
Complex Product
The Complex Product block performs output multiplication of two scalar complex inputs. Operand a is multiplied by operand b and the result output on r as the following equation shows: r=ab
312
Table 318 shows the Complex Product block inputs and outputs.
Table 318. Complex Product Block Inputs and Outputs Signal a b ena aclr r Direction Input Input Input Input Output Complex operand a. Complex operand b. Optional clock enable. Optional asynchronous clear. Result. Description
Specify the elements that you want pipelined. The clock enable and No Register, Inputs Only, Multiplier Only, Adder Only, asynchronous clear ports are available only if the block is registered. Inputs and Multiplier, Inputs and Adder, Multiplier and Adder, Inputs Multiplier and Adder On or Off On or Off On or Off Turn on to use the clock enable input (ena). Turn on to use the asynchronous clear input (aclr). If you target devices that support DSP blocks, turn on to implement the functionality in DSP blocks instead of logic elements.
Use Enable Port Use Asynchronous Clear Port Use Dedicated Circuitry
313
Table 320. Complex Product Block I/O Formats (Part 2 of 2) (Note 1) I/O O Simulink (2), (3) O1Real(2 x max(LI,L2)),(2 x max(
RI,R2)) Imag(2 x max(LI,L2)),(2 x max(RI,R 2))
VHDL O1Real: in STD_LOGIC_VECTOR({(2 x max(LI,L2)) + (2 x max(RI,R2)) -1} DOWNTO 0) O1Imag: in STD_LOGIC_VECTOR({(2 x max(LI,L2)) + (2 x max(RI,R2)) -1} DOWNTO 0)
Complex to Real-Imag
The Complex to Real-Imag block constructs a fixed-point real and fixed-point imaginary output from a complex input. Table 321 shows the Complex to Real-Imag block inputs and outputs.
Table 321. Complex to Real-Imag Block Inputs and Outputs Signal c r i Direction Input Output Output Complex input. Real part output. Imaginary part output. Description
Select the number of data input bits to the left of the binary point, including the sign bit. Select the number of data input bits to the right of the binary point. This option applies only to signed fractional formats.
314
I1Real: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0) I1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0) O1Real: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0) O2Imag: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
Real-Imag to Complex
The Real-Imag to Complex block constructs a fixed-point complex output from real and imaginary inputs. Table 324 shows the Real-Imag to Complex block has the inputs and outputs.
Table 324. Real-Imag to Complex Block Inputs and Outputs Signal r i c Direction Input Input Output Real part input. Imaginary part input. Complex output. Description
315
Select the number of data input bits to the left of the binary point, including the sign bit. Select the number of data input bits to the right of the binary point. This option applies only to signed fractional formats.
316
The blocks in the Gate &Control library support gate and other related control functions. The Gate & Control library contains the following blocks:
Binary to Seven Segments Bitwise Logical Bus Operator Case Statement Decoder Demultiplexer Flipflop If Statement LFSR Sequence Logical Bit Operator Logical Bus Operator Logical Reduce Operator Multiplexer Pattern Single Pulse
42
Table 42 shows the 4-bit to 7-bit conversion performed by the Binary to Seven Segments block.
Table 42. Binary to Seven Segments Input Binary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Hex 0 1 2 3 4 5 6 7 8 9 A b C d E F Binary 1000000 1111001 0100100 0110000 0011001 0010010 0000010 1111000 0000000 0010000 0001000 0000011 1000110 1000001 0000110 0001110 Output Decimal 64 121 36 48 25 18 2 120 0 16 8 3 70 33 6 14
43
Table 43. Binary to Seven Segments Display Block I/O Formats (Part 2 of 2) (Note 1) I/O O Simulink (2), (3) O1[7].[0] VHDL O1: in STD_LOGIC_VECTOR(6 DOWNTO 0) Type (4) Explicit
44
[number of bits].[] >= 0 (Parameterizable) [].[number of bits] >= 0 (Parameterizable) Logic Operation AND, OR, XOR
Specify the number of bits to the left of the binary point, including the sign bit. Specify the number of bits to the right of the binary point. Specify the logical operation to perform.
Table 46 shows the Bitwise Logical Bus Operator block I/O formats.
Table 46. Bitwise Logical Bus Operator Block I/O Formats I/O I O Simulink (2), (3) I1[L1].[R1] I2[L1].[R1] O1[L1].[R1]
Notes to Table 46:
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit. (2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit. (3) I1[L].[R] is an input port. O1[L].[R] is an output port. (4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
Figure 42 shows an example with the Bitwise Logical Bus Operator block.
Figure 42. Bitwise Logical Bus Operator Block Example
45
Case Statement
This Case Statement block contains boolean operators, which you can use for combinational functions. The Case Statement block compares the input signal (which must be a signed or unsigned integer) with a set of values (or cases). A single-bit output generates for each case. You can implement multiple cases with a comma (,) to separate each case. A comma at the end of the case values is ignored. You can have multiple conditions for each case with a pipe (|) to separate the conditions. For example, for four cases if the first has two conditions, enter 1|2,3,4,5 in the Case Values box. Table 47 shows the Case Statement block inputs and outputs.
Table 47. Case Statement Block Inputs and Outputs Signal unnamed 0 to n Direction Input Output Data input. A separate output is provided for each case. Description
User defined Specify the values with which you want to compare the input. Use a comma (Parameterizable) between each case and separate conditions by a pipe (|). For example: 1|2|3,4,5|-1,7 Signed Integer, Unsigned Integer Specify the bus number format that you want to use.
>= 0 Specify the number of bits to the left of the binary point, including the sign bit. (Parameterizable) >= 0 Specify the number of bits to the right of the binary point. (Parameterizable) On or Off Turn on if you want pipeline the output result. Turn on if you want the others output signal to go high when all the other outputs are false.
46
Table 49. Case Statement Block I/O Formats (Part 2 of 2) (Note 1) I/O O Oi[1] . On[1]
Notes to Table 49:
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit. (2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit. (3) I1[L].[R] is an input port. O1[L].[R] is an output port. (4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
Simulink (2), (3) O1[1] O1: out STD_LOGIC Oi: out STD_LOGIC . On: out STD_LOGIC
VHDL
The following VHDL code generates from the model in Figure 43:
caseproc:process( input ) begin case input is when "00000001" | "00000010" | "00000011" => r0 <= '1'; r1 <= '0'; r2 <= '0'; r3 <= '0'; r4 <= '0'; when "00000100" => r0 <= '0'; r1 <= '1'; r2 <= '0'; r3 <= '0'; r4 <= '0'; when "00000100" | "00000110" => r0 <= '0';
47
r1 <= '0'; r2 <= '1'; r3 <= '0'; r4 <= '0'; when "00000111" => r0 <= '0'; r1 <= '0'; r2 <= '0'; r3 <= '1'; r4 <= '0'; when others => r0 <= '0'; r1 <= '0'; r2 <= '0'; r3 <= '0'; r4 <= '1'; end case; end process;
The Case Statement block output ports in the VHDL are named r<number> where <number> is auto-generated.
Decoder
The Decoder block is a bus decoder that compares the input value against the specified decoded value. If the values match, the block outputs a 1, if they do not match it outputs a 0. If the specified value is not representable in the data type of the input bus, it is truncated to the data type of the input bus. For example: 5 (binary 101) as a 2 bit unsigned integer results in 1 (binary 01). Table 410 shows the Decoder block inputs and outputs.
Table 410. Decoder Block Inputs and Outputs Signal in match Direction Input Output Data input. Data output (1 = match, 0 = mismatch). Description
[number of bits].[] >= 0 (Parameterizable) [].[number of bits] >= 0 (Parameterizable) Register Output Decoded Value On or Off User defined (Parameterizable)
Specify the number of bits to the left of the binary point. Specify the number of bits to the right of the binary point for the gain. This option is zero (0) unless Signed Fractional is selected. Turn this option on if you want to register the output result. Specify the decoded value for matching.
48
Demultiplexer
The Demultiplexer block is a 1-to-n demultiplexer that uses full encoded binary values. The value of the input d is output to the selected output. All other outputs remain constant. The sel input is an unsigned integer bus. Table 413 shows the Demultiplexer block inputs and outputs.
Table 413. Demultiplexer Block Inputs and Outputs Signal d sel ena sclr 0(n-1) Direction Input Input Input Input Output Data input port. Select control port. Optional clock enable port. Optional synchronous clear port. Output ports. Description
49
Number of Output Data Lines An integer greater than 1 (Parameterizable) Use Enable Port Use Synchronous Clear Port On or Off On or Off
I1: in STD_LOGIC_VECTOR({L + R1 - 1} DOWNTO 0) I2: in STD_LOGIC_VECTOR({L - 1} DOWNTO 0) I3: in STD_LOGIC I4: in STD_LOGIC O1: out STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0) ... On: out STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0)
Implicit Implicit
410
Flipflop
Set the Flipflop block as a D-type flipflop with enable (DFFE) or T-type flipflop with enable (TFFE). If the number of bits is set to more than 1, the block behaves as single-bit flipflops for each bit. For example, for a TFFE flipflop with an n-bit signal, the signal is processed with n 1-bit TFFE flipflops. Table 416 shows the Flipflop block inputs and outputs.
Table 416. Flipflop Block Inputs and Outputs Signal input ena aprn aclrn Q Direction Input Input Input Input Output Data or togggle port. Enable port. Asynchronous reset port. Asynchronous clear port. Output port. Description
DFFE mode:
if (0 == aclrn) Q = 0; else if (0 == aprn) Q = 1; else if (1 == ena) Q = D
TFFE mode:
if (0 == aclrn) Q = 0; else if (0 == aprn) Q = 1; else if (1 == ena) and (1 == T)
Q = toggle
DSP Builder does not support (aclrn == 0) and (aprn == 0). The aclrn port is an active-low asynchronous clear port. When active this sets the output and internal state to 0 for the remainder/duration of the clock cycle. The aprn port is an active-low asynchronous preset port. When active this sets the output and internal state to 1 for the remainder/duration of the clock cycle. Table 417 shows the Flipflop block parameters.
Table 417. Flipflop Block Parameters Name Mode Bus Type Value DFFE or TFFE Signed Integer, Signed Fractional, Unsigned Integer, Single Bit Description Specify the type of flipflop to implement. Specify the bus number format that you want to use.
Specify the number of bits to the left of the binary point. Specify the number of bits to the right of the binary point for the gain. This option is zero (0) unless you select Signed Fractional.
411
I1: in STD_LOGIC_VECTOR({L1 - 1} DOWNTO 0) I2: in STD_LOGIC I3: in STD_LOGIC I4: in STD_LOGIC O1: in STD_LOGIC_VECTOR({L1 - 1} DOWNTO 0)
Explicit
If Statement
The If Statement block outputs a 0 or 1 result based on the IF condition expression. Table 419 shows the If Statement block inputs and outputs.
Table 419. If Statement Block Inputs and Outputs Signal aj n true false Direction Input Input Output Output Input ports. Optional ELSE IF input port. Output port (high when true). Optional ELSE output port (high when false). Description
412
You can build an IF condition expression with the signal values 0 or 1 and any of the permitted operators given in Table 420.
Table 420. Supported If Statement Block Operators Operator & | $ = ~ > < () AND OR XOR Equal To Not Equal To Greater Than Less Than Parentheses Operation
When writing expressions in an If Statement block, ensure that the operators are always operating on the same types. That is, bus signals compare with and operate with bus signals; and booleans (the 'true' or 'false' result of such operations) only compare with and operate with booleans. In other words, the types must be the same on either side of an operator. Treat an If statement expression, 0 and 1, as signals rather than as booleans, otherwise you receive an error at HDL generation of the following form:
Can't determine definition of operator "<mixed operator>" -- found 0 possible definitions
If you receive this error, carefully check the expressions specified in the If Statement blocks. The following examples of bad syntax give errors:
(a>b)&c, where a,b and c are all input values to the If Statement. Here (a>b) returns a boolean ('true' or 'false') and is ANDed with signal c. This operation is ill defined and results in the following error:
Can't determine definition of operator ""&"" -- found 0 possible definitions
((a>b)~0) Again (a>b) returns a boolean ('true' or 'false'). 0 is treated as a signal not a boolean, so the hardware generation fails with an error:
Can't determine definition of operator ""/="" -- found 0 possible definitions"
where /= is the hardware translation of the 'not equal to' operator. Here the ~0 incorrectly means 'not false', and is unnecessary. The correct syntax for this expression is just (a>b).
413
Signed Integer, Signed Fractional, Unsigned Integer Single Bit, Inferred >= 0 (Parameterizable) >= 0 (Parameterizable)
Specify the number of bits to the left of the binary point. Specify the number of bits to the right of the binary point for the gain. This option is zero (0) unless Signed Fractional is selected. This option turns on the false output, which implements an ELSE condition and goes high if the condition evaluated by the If Statement block is false. This option turns on the else input, which implements an ELSE IF input, when you want to cascade multiple IF Statement blocks together or as an enable for the block.
On or Off
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) Ii: in STD_LOGIC_VECTOR({LI + RI - 1} DOWNTO 0) . In: in STD_LOGIC_VECTOR({LN + RN - 1} DOWNTO 0) O1: out STD_LOGIC O2: out STD_LOGIC
Explicit
414
Figure 47 shows an example of the If Statement block, which implements the conditional statement:
Quantizer: if (Input<-4) Output = -100 else if ((Input>=-4) & (Input<10)) Output = 0 else Output = 100
LFSR Sequence
The LFSR Sequence block implements a linear feedback shift register that shifts one bit across L registers. The register output bits shift from LSB to most significant bit (MSB) with the output sout connected to the MSB of the shift register. The register output bits can optionally be XORed or XNORed together. For example, when choosing an LFSR sequence of length eight, the default polynomial is x8 + x4 + x3 + x2 + 1 with the circuitry that Figure 48 shows.
Figure 48. Default LFSR Sequence Block with Length 8 Circuitry
The polynomial is a primitive or maximal-length polynomial All registers are initialized to one The feedback gate type is XOR The feedback structure is an external n-input gate or many to one
You can modify the implemented LFSR sequence by changing the parameter values.
415
For example, after changing the feedback structure to an internal two-inputs gate, DSP Builder implements the circuitry (Figure 49).
Figure 49. Internal 2-Input Gate Circuitry
to:
1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 0 0
Table 423 shows the LFSR Sequence block inputs and outputs.
Table 423. LFSR Sequence Block Inputs and Outputs Signal ena rst sout pout Direction Input Input Output Output Optional reset port. Serial output port for MSB of the LFSR. Optional parallel output port for LFSR unsigned value. Description Optional clock enable port.
Primitive Polynomial User-Defined Array of Tap Sequence Polynomial Coefficients (Parameterizable) Specify Clock Clock Use Parallel Output On or Off User defined (Parameterizable) On or Off
416
Table 424. LFSR Sequence Block Parameters (Part 2 of 2) Name Use Enable Port Use Synchronous Clear Port On or Off On or Off Value Description Turn on to use the clock enable input (ena). Turn on to use the synchronous clear input (sclr).
VHDL I1: in STD_LOGIC I2: in STD_LOGIC O1: out STD_LOGIC O2: out STD_LOGIC_VECTOR(L-1 DOWNTO 0)
Type
AND, OR, XOR, Specify the operator you want to use. NAND, NOR, NOT 116 Specify the number of inputs. This parameter defaults to 1 if the NOT logical (Parameterizable) operator is selected.
417
Table 427 shows the Logical Bit Operator block I/O formats.
Table 427. Logical Bit Operator Block I/O Formats I/O I I1[1] Ii[1] . In[1] O O1[1]
Notes to Table 427:
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit. (2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit. (3) I1[L].[R] is an input port. O1[L].[R] is an output port. (4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
Simulink (2), (3) I1: in STD_LOGIC Ii: in STD_LOGIC . In: in STD_LOGIC O1: out STD_LOGIC
Explicit
Figure 411 shows an example with the Logical Bit Operator block.
Figure 411. Logical Bit Operator Block Example
418
Table 428 shows the Logical Bus Operator block inputs and outputs.
Table 428. Logical Bus Operator Block Inputs and Outputs Signal d q Direction Input Output Input data. Output data. Description
Specify the number of bits to the left of the binary point, including the sign bit. Specify the number of bits to the right of the binary point. Specify the logical operation to perform.
Mask Value
Specify the mask value for an AND, OR, or XOR operation as an unsigned integer representing the required mask, which must have the same number of bits as the input. Specify how many bits you want to shift when you chose a shift or rotate operation. Turn on to preserve the input data sign when right shifting signed data.
Table 430 shows the Logical Bus Operator block I/O formats.
Table 430. Logical Bus Operator Block I/O Formats I/O I O Simulink (2), (3) I1[L1].[R1] O1[L1].[R1] (Note 1) VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) O1: out STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) Type (4) Explicit Explicit
419
Figure 412 shows an example with the Logical Bus Operator block.
Figure 412. Logical Bus Operator Block Example
Specify the number of bits to the left of the binary point, including the sign bit.
420
Table 432. Logical Reduce Operator Block Parameters (Part 2 of 2) Name Value Description Specify the number of bits to the right of the binary point. Specify the logical operation to perform.
[].[number of bits] >= 0 (Parameterizable) Logical Reduction Operation AND, OR, XOR, NAND, NOR
Table 433 shows the Logical Reduce Operator block I/O formats.
Table 433. Logical Reduce Operator Block I/O Formats (Note 1) I/O I O Simulink (2), (3) I1[L1].[R1] O1[1] O1: out STD_LOGIC VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) Type (4) Explicit Explicit
Figure 413 shows an example with the Logical Reduce Operator block.
Figure 413. Logical Reduce Operator Block Example
Multiplexer
The Multiplexer block operates as either a n-to-1 one-hot or full-binary bus multiplexer with one select control. The output width of the multiplexer is equal to the maximum width of the input data lines. The block works on any data type and sign extends the inputs if there is a bit width mismatch. Table 434 shows the Multiplexer block inputs and outputs.
421
Table 434. Multiplexer Block Inputs and Outputs Signal sel 0(n-1) ena aclr <unnamed> Direction Input Input Input Input Output Select control port. Data input ports. Optional enable port. Optional asynchronous clear port. Output port. Description
Number of Input Data Lines An integer greater than 1 (Parameterizable) Number of Pipeline Stages One Hot Select Bus Use Enable Port Use Asynchronous Clear Port On or Off On or Off On or Off
>= 0 (Parameterizable) Specify the number of pipeline stages. Turn on to use one-hot selection for the bus select signal instead of full binary. Turn on to use the clock enable input (ena). This option is available only when the number of pipeline stages is greater than 0. Turn on to use the asynchronous clear input (aclr). This option is available only when the number of pipeline stages is greater than 0.
VHDL I1: in STD_LOGIC_VECTOR({L1 - 1} DOWNTO 0) I2: in STD_LOGIC_VECTOR({L2 + R2 - 1} DOWNTO 0) Ii: in STD_LOGIC_VECTOR({Li + Ri - 1} DOWNTO 0) . In: in STD_LOGIC_VECTOR({Ln + Rn - 1} DOWNTO 0) In+1: STD_LOGIC In+2: STD_LOGIC O1: out STD_LOGIC_VECTOR({max(Li)) + max(Ri) - 1} DOWNTO 0)
Implicit
422
Pattern
The Pattern block generates a repeating periodic bit sequence in time. You can enter the required pattern as a binary sequence. For example, the pattern 01100 outputs the repeating pattern:
0110001100011000110001100011000110001100
You can change the output data rate for a registered block by feeding the clock enable input with the output of the Pattern block. 1 With a sequence of length 1, the Pattern block acts as a constant, holding its output to the specified value at all times. There is no artificial limit to the pattern length. Table 437 shows the Pattern block inputs and outputs.
Table 437. Pattern Block Inputs and Outputs Signal ena sclr <unnamed> Direction Input Input Output Description Optional clock enable port. Optional synchronous clear port. Output data port.
User defined Specify the name of the required clock signal. (Parameterizable)
423
Table 438. Pattern Block Parameters (Part 2 of 2) Name Use Enable Port Value On or Off Description Turn on to use the clock enable input (ena). Turn on to use the synchronous clear input (sclr).
Single Pulse
The Single Pulse block generates a single pulse output signal. The output signal is a single bit that takes only the values 1 or 0. The signal generation type can be an impulse, a step up (0 to 1), or a step down (1 to 0). The output of a impulse starts at 0 changing to 1 after a specified delay and changing to 0 again after a specified length. The output of a step up starts at 0 changing to 1 after a specified delay. The output of a step down starts at 1 changing to 0 after a specified delay. Table 440 shows the Single Pulse block inputs and outputs.
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Table 440. Single Pulse Block Inputs and Outputs Signal ena sclr <unnamed> Direction Input Input output Description Optional clock enable port. Optional synchronous clear port. Output port.
Specify the number of clock cycles for which the output signal is transitional from 0 to 1 for an Impulse type output. Specify the number of clock cycles that occur before the pulse transition. Turn on to explicitly specify the clock name. Specify the name of the required clock signal. Turn on to use the clock enable input (ena). Turn on to use the synchronous clear input (sclr).
VHDL
5. Interfaces Library
Use the blocks in the Interfaces library to build custom logic blocks that support the Avalon Memory-Mapped (Avalon-MM) and Avalon Streaming (Avalon-ST) interfaces. The Interfaces library contains the following blocks:
Avalon-MM Master Avalon-MM Slave Avalon-MM Read FIFO Avalon-MM Write FIFO Avalon-ST Packet Format Converter Avalon-ST Sink Avalon-ST Source
Configurable master and slave blocks that contain the ports required to connect peripherals that use the Avalon-MM bus. Wrapped versions of the Avalon-MM slave that implement an Avalon-MM read FIFO buffer and Avalon-MM write FIFO.
For more information about the Avalon-MM interface, refer to the Avalon Interface Specifications. After you synthesize your model and compile it in the Quartus II software, use SOPC Builder to add it to your Nios II system. Your design automatically appears under the DSP Builder category in the SOPC Builder component browser peripherals listing if the MDL file is in the same directory as the SOPC file. A file mydesign.mdl creates a component mydesign_interface in SOPC Builder.
For the peripheral to appear in SOPC Builder, the working directory for your SOPC Builder project must be the same as your DSP Builder working directory. For information about using SOPC Builder to create Nios II designs, refer to the Nios II Hardware Development Tutorial.
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Figure 51 shows SOPC Builder with an on-chip RAM memory, Nios II processor, and a DSP Builder created peripheral topavalon.
Figure 51. SOPC Builder with DSP Builder Peripheral
Figure 52 shows the design flow with DSP Builder and SOPC Builder.
Figure 52. DSP Builder & SOPC Builder Design Flow
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Avalon-MM Master
The Avalon-MM Master block defines a collection of ports for connection to an SOPC Builder system when your design functions as an Avalon-MM master interface. Table 51 lists the signals supported by the Avalon-MM Master block.
Table 51. Signals Supported by the Avalon-MM Master Block (Part 1 of 2) Signal waitrequest address read readdata write writedata byteenable Direction Input Output Output Input Output Output Output Description This signal forces the master port to wait until you are ready to proceed with the transfer. The address signal represents a byte address but is asserted on word boundaries only. Available with Read or Read/Write address type. Read request signal. Not required if there are no read transfers. If used, also use readdata. Available when Read or Read/Write address type is chosen. Data lines for read transfers. Not required if there are no read transfers. If used, also use read. Available when Write or Read/Write address type is chosen. Write request signal. Not required if there are no write transfers. If used, also use writedata. Available when Write or Read/Write address type is chosen. Data lines for write transfers. Not required if there are no write transfers. If used, also use write. Available when Write or Read/Write address type is chosen and the bit width is greater than 8. Enables specific byte lane(s) during write transfers to memories of width greater than 8 bits. All byteenable lines must be enabled during read transfers. Available when Allow Flow Control is on. Indicates an end-of-packet condition.
endofpacket
Input
54
Table 51. Signals Supported by the Avalon-MM Master Block (Part 2 of 2) Signal Direction Description Available when Allow Pipeline Transfers is on. Use for pipelined read transfers with latency. Indicates that valid data is present on the readdata lines. Available when Allow Pipeline Transfers and Use Flush Signal are on. Can be asserted to clear any pending transfers in the pipeline. Available when Allow Burst Transfers is on. Indicates the number of transfers in a burst. Available when Receive IRQ is on. Indicates when one or more ports have requested an interrupt. Available when Receive IRQ is on and IRQ mode is set to Prioritized. Indicates the interrupt priority. Lower value means higher priority.
readdatavalid Input flush burstcount irq irqnumber Output Output Input Input
The direction in Table 51 refers to the direction in respect of the DSP Builder block interface. Figure 52 shows the Avalon-MM Master block parameters.
Table 52. Avalon-MM Master Block Parameters (Part 1 of 2) Name Specify Clock Clock Address Width Address Type Data Type Value On or Off User defined 132 Read, Write, Read/Write Signed Integer, Signed Fractional, Unsigned Integer >= 0 (Parameterizable) >= 0 (Parameterizable) On or Off On or Off Specifies the clock signal name. Specifies the number of address bits. The address type for the bus. The number format of the bus. Description Turn on to explicitly specify the clock name.
[number of bits].[] [].[number of bits] Allow Byte Enable Allow Flow Control
Specifies the number of bits to the left of the binary point, including the sign bit. Read and write buses must have the same number of bits. Specifies the number of bits to the right of the binary point. This parameter applies only to signed fractional buses. Turn on to use the Byte Enable signal. This option is available when the address type is set to Write or Read/Write and the bit width is greater than 8. Turn on to enable flow control. Flow control allows a slave port to regulate incoming transfers from a master port, so that a transfer only begins when the slave port indicates that it has valid data or is ready to receive data. Turn on to allow pipeline transfers. Pipeline transfers increase the bandwidth for synchronous slave peripherals that require several cycles to return data for the first access, but can return data every cycle thereafter. This option is available when the address type is Read or Read/Write. Turn on to clear any pending transfers in the pipeline. This option is available when Allow Pipeline Transfers is on. Turn on to allow burst transfers. A burst executes multiple transfers as a unit, and maximize the throughput for slave ports that achieves the greatest efficiency when handling multiple units of data from one master port at a time. Specifies the maximum width of a burst transfer. This option is available when Allow Burst Transfers is on.
On or Off
On or Off
232
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Table 52. Avalon-MM Master Block Parameters (Part 2 of 2) Name Receive IRQ IRQ Mode Value On or Off Prioritized, Individual Signals Description Turn on to enable interrupt requests from the slave port. The interrupt request mode. This option is available when Receive IRQ is on.
For general information about Avalon-MM blocks, refer to Avalon Memory-Mapped Blocks on page 51.
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Avalon-MM Slave
The Avalon-MM Slave block defines a collection of ports for connection to an SOPC Builder system when your design functions as an Avalon-MM slave interface. Table 53 lists the signals supported by the Avalon-MM Slave block.
Table 53. Signals Supported by the Avalon-MM Slave Block Signal address read readdata write Direction Output Output Input Output Description Address lines to the slave port. Specifies a word offset into the slave address space. Available when Read or Read/Write address type is chosen. Read-request signal. Not required if there are no read transfers. If used, also use readdata. Available when Read or Read/Write address type is chosen. Data lines for read transfers. Not required if there are no read transfers. If used, also use read. Available when Write or Read/Write address type is chosen. Write-request signal. Not required if there are no write transfers. If used, also use writedata. Available when Write or Read/Write address type is chosen. Data lines for write transfers. Not required if there are no write transfers. If used, also use write. Available when Allow Byte Enable is on and the bit width is greater than 8. Byte-enable signals to enable specific byte lane(s) during write transfers to memories of width greater than 8 bits. If used, also use writedata. Available when Write or Read/Write access is chosen and Allow Flow Control is on. Indicates that the peripheral is ready for a write transfer. Available when Read or Read/Write access is chosen and Allow Flow Control is on. Indicates that the peripheral is ready for a read transfer. Available when Allow Flow Control is on. Indicates an end-of-packet condition. Available when Allow Pipeline Transfers is on and variable read latency is chosen. Marks the rising clock edge when readdata asserts. Available when variable wait-state format is chosen. Use to stall the interface when the slave port cannot respond immediately. Available when Allow Burst Transfers is on. Asserted for the first cycle of a burst to indicate when a burst transfer is starting. Available when Allow Burst Transfers is on. Indicates the number of transfers in a burst. If used, also use waitrequest. Available when Output IRQ is on. Interrupt request. Asserted when a port needs to be serviced. Available when Receive Begin Transfer is on. Asserted during the first cycle of every transfer. Available when Use Chip Select is on. The slave port ignores all other Avalon-MM signal inputs unless chipselect is asserted.
writedata byteenable
Output Output
beginbursttransfer Output burstcount irq begintransfer chipselect Output Input Output Output
The direction in Table 53 refers to the direction in respect of the DSP Builder block interface. Table 54 shows the Avalon-MM Slave block parameters.
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Table 54. Avalon-MM Slave Block Parameters Name Specify Clock Clock Address Width Address Alignment Address Type Data Type Value On or Off User defined 132 Native, Dynamic Read, Write, Read/Write Signed Integer, Signed Fractional, Unsigned Integer >= 0 (Parameterizable) >= 0 (Parameterizable) On or Off On or Off Specifies the clock signal name. Specifies the number of address bits. Use native address alignment or dynamic bus sizing. The address type for the bus. The number format of the bus. Description Turn on to explicitly specify the clock name.
[number of bits].[] [].[number of bits] Allow Byte Enable Allow Flow Control
Specifies the number of bits to the left of the binary point, including the sign bit. Read and write buses must have the same number of bits. Specifies the number of bits to the right of the binary point. This parameter applies only to signed fractional buses. Turn on to use the Byte Enable signal. This option is available only when the address type is set to Write or Read/Write. Turn on to enable flow control. Flow control allows a slave port to regulate incoming transfers from a master port, so that a transfer only begins when the slave port indicates that it has valid data or is ready to receive data. Turn on to allow pipeline transfers. Pipeline transfers increase the bandwidth for synchronous slave peripherals that require several cycles to return data for the first access, but can return data every cycle thereafter. This option is available only when the address type is set to Read or Read/Write. The required wait-state format. Specifies the number of read wait-state cycles. This option is available only when the wait-state format is set to Fixed. Specifies the number of write wait state cycles. This option is available only when the wait-state format is set to Fixed. The required read latency format. This option is available only when Allow Pipeline Transfers is on. Specifies the pipeline read latency. Latency determines the length of the data phase, independently of the address phase. For example, a pipelined slave port (with no wait-states) can sustain one transfer per cycle, even though it may require several cycles of latency to return the first unit of data. This option is available only when Allow Pipeline Transfers is on and Fixed read latency format is set. Turn on to allow burst transfers. A burst executes multiple transfers as a unit, and maximize the throughput for slave ports that achieves the greatest efficiency when handling multiple units of data from one master port at a time. Specifies the maximum width of a burst transfer. This option is available only when Allow Burst Transfer is on. Turn on to enable interrupt requests from the slave port. Turn on to receive begintransfer signals. Turn on to enable the chipselect signal.
On or Off
Wait-State Format
Fixed, Variable
Read Wait-State Cycles 0255 Write Wait-State Cycles 0255 Read Latency Format Read Latency Cycles Fixed, Variable 08
On or Off
Maximum Burst Size Output IRQ Receive BeginTransfer Use Chip Select
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For general information about Avalon-MM blocks refer to Avalon Memory-Mapped Blocks on page 51.
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[number of bits].[] >= 0 (Parameterizable) [].[number of bits] >= 0 (Parameterizable) FIFO Depth >2
Specifies the number of bits to the left of the binary point, including the sign bit. This parameter does not apply to single-bit buses. Specifies the number of bits to the right of the binary point. This parameter applies only to signed fractional buses. Specifies the depth of the FIFO.
510
511
Stall
Input
Ready DataOut
Input Output
DataValid Output
[number of bits].[] >= 0 Specifies the number of bits to the left of the binary point, including the sign bit. (Parameterizable) This parameter does not apply to single-bit buses. [].[number of bits] >= 0 Specifies the number of bits to the right of the binary point. This parameter applies (Parameterizable) only to signed fractional buses. FIFO Depth >2 Specifies the depth of the FIFO buffer.
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513
The PFC performs data mapping on a packet by packet basis, so that there is exactly one input packet on each input interface for one output packet on each output interface. The interface with the longest packet limits the packet rate of the converter. When the PFC has multiple output interfaces, the packets on each output interface are aligned so that the startofpacket signal is presented on the same clock cycle. If each interface supports fixed-length packets, you can select a Multi-Packet Mapping option. The PFC can then map fields from multiple input packets to multiple output packets. The PFC does not support bursts or blocks on its output interfaces. Use the Split Data option to split the input or output data signals across additional ports named data0 through dataN. Each input interface consists of the ready, valid, startofpacket, endofpacket, empty, and data signals. Each output interface has an additional error signal that asserts to indicate a frame delineation error. f For more information about these signal types, refer to the Avalon Interface Specifications. The PFC block does not support Avalon-ST bursts or blocks on its output interfaces. Table 59 lists the signals supported by the Avalon-ST Packet Format Converter block.
Table 59. Signals Supported by the Avalon-ST Packet Format Converter Block (Part 1 of 2) Signal reset_n inX_dataN inX_empty Direction Input Input Input Active-low reset signal. Data input bus for sink interface X. Indicates the number of empty symbols for sink interface X during cycles that mark the end of a packet. Description
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Table 59. Signals Supported by the Avalon-ST Packet Format Converter Block (Part 2 of 2) Signal inX_endofpacket inX_startofpacket inX_valid outY_ready aclr inX_ready outY_dataN outY_empty outY_endofpacket Direction Input Input Input Input Input Output Output Output Output Description This signal marks the active cycle containing the end of the packet for sink interface X. This signal marks the active cycle containing the start of the packet for sink interface X. Indicates DSP Builder can accept data for sink interface X. Indicates that the sink driven by the source interface Y is ready to accept data. Optional asynchronous clear port. Indicates that sink interface X is ready to output data. Data output bus for source interface Y. Indicates the number of empty symbols for source interface Y during cycles that mark the end of a packet. This signal marks the active cycle containing the end of the packet for source interface Y. This signal marks the active cycle containing the start of the packet for source interface Y. Indicates that valid data is available on source interface Y. Indicates an error condition when asserted high.
Table 510 shows the Avalon-ST Packet Format Converter block parameters.
Table 510. Avalon-ST Packet Format Converter Block Parameters Name Number of Sinks Number of Sources Split Data Value 116 116 On or Off Description Specifies the number of sink interfaces X. Specifies the number of source interfaces Y. When on, the data signals on the sink and source interface are split into signals named data0 through dataN with widths corresponding to the specified symbol width. When off, one input packet is matched to one output packet and the input and output packets must have the name number of instances in each field. When on, the PFC maps the input packets to output packets such that all instances of every data field are accounted for. Specifies the number of bits per symbol that all the PFC sink and source interfaces use. Turn on to use the asynchronous clear input (aclr). A quoted string or MATLAB variable that describes the packet format for sink interface X. Specifies the number of symbols per beat for sink interface X. A quoted string or MATLAB variable that describes the packet format for source interface Y. Specifies number of symbols per beat for source interface Y.
Multi-Packet Mapping
On or Off
Symbol Width Use Asynchronous Clear Port Sink Format X Sink X Symbols Per Beat Source Format Y
515
Dest,Source,(Data)128,(CRC)4 indicates a packet that has destination and source address symbols followed by 128 data symbols and 4 CRC symbols. (Red,Green,Blue)100 refers to a frame with 100 repetitions of a symbol of Red, followed by a symbol of Green, followed by a symbol of Blue. Nest repeats, so that (F1,(F2)3,F3)2,F4 is equivalent to (F1,F2,F2,F2,F3)2,F4 or F1,F2,F2,F2,F3,F1,F2,F2,F2,F3,F4.
Use a + instead of a positive integer, such as (Red,Green,Blue)+, to repeat a group an unspecified number of times in a packet. However, such a group must compose the entire packet. Therefore, none of the following examples are valid: A,(B,C)+, (A,B)+,C, or((A)+)2.
516
Table 511 summarizes the packet description syntax for the PFC.
Table 511. Packet Description Syntax Packet Descriptor: Group | (Group)+ where + indicates that the preceding Group is repeated an unknown number of times Group repeatedGroup repeatedGroup | simpleGroup (Group)N where N is a positive integer indicating the number of times the preceding group is repeated simpleGroup FieldName[,Group]
Table 512 shows some example packets. All these examples use the convention <packet description> / <symbols per beat>, so that R,G,B/2 refers to an interface where the packet description is R,G,B and the number of symbols per beat is 2.
Table 512. Packet Description Examples Packet Description / Symbols Per Beat (R,G,B)4 (R,G,B)4/3 Example Packets
(Y,Cr,Y,Cb)/2
((A)2,B,C,(A)2,B,D)3/4
((((A)2,B)2,C)2,D)2
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Figure 511 shows an example of the packet formats for a PFC with two input and two output interfaces.
Figure 511. Example of a Packet Format Converter with Two Input and Two Output Interfaces
Packet Mapping
Packet mapping is the process of determining where the data for each field in each output interface is coming from (as an {input interface, position} pair). To achieve packet mapping, compare the field name strings. For example, the source of data for the Red field in a given output interface is the field on an input interface with the name Red. It is not valid for any field name to exist on multiple-input interfaces; no two input interfaces may have a Red field. It is valid, however, for multiple-output interfaces to have the same field; you may copy the Red data to two or more output interfaces. A single input or output interface can have multiple instances of the same field. For example, Red,Green,Red,Blue represents a packet with two red symbols per packet. The PFC matches the nth instance of a field on an input interface to the nth instance of the same field on an output interface. If an output interface has Blue,Green,Red,Red, the data for the first Red field is taken from the first Red field in the input packet. Each output interface may or may not use a given input field, but unless you set the Multi-Packet Mapping option (and if the input field is used) there must be the same number of instances of the field in each output as there is in the input. For example, Green and Red,Red,Green are both valid, but Red,Green is not.
Multi-Packet Mapping
Set the Multi-Packet Mapping option, so that the PFC is not limited to mapping a single input packet on each port to a single output packet on each port. It can map multiple input packets to multiple output packets. For example, (Red,Green,Blue)2 maps to (Red,Green,Blue)3 by using three input packets for every two output packets.
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The ratio of input fields to output fields must be constant. For example, Red,Red,Green,Blue does not map to (Red,Green,Blue)2 because each output packet requires one input packet for Red, but two input packets for Green and Blue. DSP Builder supports multiple interfaces but the packet ratio must be constant across all {input interface, output interface} pairs. For example, two input interfaces with the formats (Red,Green)2 and Blue map to output interface (Red)6,Blue(3),Green(6) because three input packets are required for two output packets for all input and output pairs. The same inputs do not map to (Red)3,Blue(3),Green(3), because to make two output packets, three of the first input's packets and six of the second input's packets are required. 1 DSP Builder does not support packets of unknown length.
Error Handling
The PFC contains internal counters that keep track of the current position in the packet for each input and uses these counters to detect frame delineation errors. Every time a startofpacket or endofpacket signal asserts on an input interface, the PFC uses its knowledge of the frame structure to ensure that the assertion is on a valid cycle. For PFC variants where the packet size is known, the PFC also checks that the startofpacket and endofpacket signals assert when they should do, and are not missed. The PFC only has a single output error bit to report frame delineation errors. The output error bit asserts on all outputs as soon as DSP Builder detects an error, and it asserts for each output interface independently until an endofpacket asserts for that output interface. After the endofpacket asserts, the PFC presents no more data to that output interface. When all output interfaces stop, the PFC resets and resumes normal operation. The PFC stops independently on the endofpacket signal for each output, and components downstream of the PFC should never see partial frames. While errors assert to the output interfaces and the core is reset, the input interfaces are not back pressured. This action prevents loss of any synchronization between input interfaces by uneven back pressuring during error conditions. When the PFC starts again, it waits until it sees a startofpacket signal for each input interface before accepting data for that interface. It is not possible to guarantee synchronization of output interfaces when frame delineation errors are present. The PFC does not support relaying errors from an upstream component to a downstream component. When simulating the PFC block, connect the reset port to a pulse generator (such as the Single Pulse block in the DSP Builder Gate & Control library) that is configured to output an initial 0, then a 1 for the remainder of the simulation.
Avalon-ST Sink
The Avalon-ST Sink block defines a collection of ports for connection to an SOPC Builder system when your design functions as an Avalon-ST sink.
519
For information about the Avalon-ST interface, refer to the Avalon Interface Specifications. Table 513 lists the signals supported by the Avalon-ST Sink block.
Table 513. Signals Supported by the Avalon-ST Sink Block Signal DataIn Valid Ready startofpacket endofpacket empty Direction Input Input Output Input Input Input Data input bus. Data valid signal that indicates the validity of the input data signals. Data input ready signal. Indicates that the sink can accept data. This signal is available when Use startofpacket is on and marks the active cycle containing the start of the packet. This signal is available when Use endofpacket is on and marks the active cycle containing the end of the packet. This signal is available when Use empty is turned on and the bit width is greater than the symbol width. It specifies how many of the symbols in a packet are empty. For example, a 32-bit wide bus with 8-bit symbols can have an empty value from 0 to 3. Description
The number format of the bus. Signed Integer, Signed Fractional, Unsigned Integer
[number of bits].[] >= 0 Specifies the number of bits to the left of the binary point, including the sign bit. (Parameterizable) Read and write buses must have the same number of bits. [].[number of bits] >= 0 Specifies the number of bits to the right of the binary point. This parameter applies (Parameterizable) only to signed fractional buses. Symbol Width Use endofpacket Use startofpacket Use empty Ready Latency >= 1 On or Off On or Off On or Off 0 or 1 Specifies the symbol width in bits. When this option is on, the endofpacket port is available on the Avalon-ST Sink block. When this option is on, the startofpacket port is available on the Avalon-ST Sink block. When this option is on and the bit width is greater than the symbol width, the empty port is available on the Avalon-ST Sink block. Defines the relationship between assertion or deassertion of the Ready signal and cycles the ones ready for data transfer separately for each interface.
520
Figure 512 shows an Avalon-ST Sink block with all signals enabled.
Figure 512. Avalon-ST Sink Block with All Signals Enabled
Avalon-ST Source
The Avalon-ST Source block defines a collection of ports for connection to an SOPC Builder system when your design functions as an Avalon-ST source. f For information about the Avalon-ST interface, refer to the Avalon Interface Specifications. Table 515 lists the signals supported by the Avalon-ST Source block.
Table 515. Signals Supported by the Avalon-ST Source Block Signal DataOut Valid Ready startofpacket endofpacket empty Direction Output Output Input Output Output Output Data input bus. Data valid signal that indicates the validity of the output data signals. Data output ready signal. Indicates that the source can accept data. This signal is available when the Use startofpacket parameter is on and marks the active cycle containing the start of the packet. This signal is available when the Use endofpacket parameter is on and marks the active cycle containing the end of the packet. This signal is available when Use empty is turned on and the bit width is greater than the symbol width. It specifies how many of the symbols in a packet are empty. For example, a 32-bit wide bus with 8-bit symbols can have an empty value from 0 to 3. Description
Table 516 on page 521 shows the Avalon-ST Source block parameters.
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Table 516. Avalon-ST Source Block Parameters Name Specify Clock Clock Data Type Value On or Off User defined Specifies the clock signal name. Description Turn on to explicitly specify the clock name.
Signed Integer, The number format of the bus. Signed Fractional, Unsigned Integer
[number of bits].[] >= 0 Specifies the number of bits to the left of the binary point, including the sign bit. (Parameterizable) Read and write buses must have the same number of bits. [].[number of bits] >= 0 Specifies the number of bits to the right of the binary point. This parameter applies (Parameterizable) only to signed fractional buses. Symbol Width Use endofpacket Use startofpacket Use empty Ready Latency 1512 On or Off On or Off On or Off 0 or 1 Specifies the symbol width in bits. When this option is on, the endofpacket port is available on the Avalon-ST Source block. When this option is on, the startofpacket port is available on the Avalon-ST Source block. When this option is on and the bit width is greater than the symbol width, the empty port is available on the Avalon-ST Sink block. Defines the relationship between assertion/deassertion of the Ready signal and cycles the ones ready for data transfer separately for each interface.
Figure 513 shows an Avalon-ST Source block with all signals enabled.
Figure 513. Avalon-ST Source Block with All Signals Enabled
522
The blocks in the IO & Bus library manipulate signals and buses to perform operations such as truncation, saturation, bit extraction, or bus format conversion. The IO & Bus library contains the following blocks:
AltBus Binary Point Casting Bus Builder Bus Concatenation Bus Conversion Bus Splitter Constant Extract Bit Global Reset GND Input Non-synthesizable Input Non-synthesizable Output Output Round Saturate VCC
62
AltBus
The AltBus block modifies the bus format of a DSP Builder signal. Only use this block as an internal node in a system, not as an input to or output from the system. If the specified bit width is wider than the input bit width, the bus is sign extended to fit. If it is smaller than the input bit width, you can specify to either truncate or saturate the excess bits. Table 61 shows the AltBus block parameters.
Table 61. AltBus Block Parameters Name Bus Type Value Signed Integer, Signed Fractional, Unsigned Integer, Single Bit The number format of the bus. Description
[number of bits].[] >= 0 (Parameterizable) [].[number of bits] >= 0 (Parameterizable) Saturate Output On or Off
Specifies the number of bits to the left of the binary point, including the sign bit. This parameter does not apply to single-bit buses. Specifies the number of bits to the right of the binary point. This parameter applies only to signed fractional buses. When this option is on, if the output is greater than the maximum positive or negative value to be represented, the output is forced (or saturated) to the maximum positive or negative value, respectively. When off, the MSB is truncated.
Table 63 and Figure 61 on page 63 illustrate how a floating-point number (4/3 = 1.3333) is cast into signed binary fractional format with three different binary point locations.
Table 63. Floating-Point Numbers Cast to Signed Binary Fractional Bus Notation [4].[1] [2].[3] [1].[4]
Note to Table 63:
(1) In this case, more bits are needed to represent the integer part of the number.
VHDL 2 10 -11
63
Figure 62 illustrates the usage of AltBus to convert a 20-bit bus with a ([10].[10]) signed binary fractional format to a 4-bit bus with a [2].[2] signed binary fractional format. In VHDL, this results in extracting a 4-bit bus (AltBus(3 DOWNTO 0)) from a 20-bit bus (AltBus(19 DOWNTO 0)) with the assignment:
AltBus3(3 DOWNTO 0)) AltBus(11 DOWNTO 8))
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You can also perform additional internal bus manipulation with the Altera Bus Conversion, Extract Bit, or Bus Builder blocks.
[number of bits].[] >= 0 Specifies the number of bits to the left of the binary point, including the sign bit. (Parameterizable) [].[number of bits] >= 0 Specifies the number of bits to the right of the binary point. This parameter (Parameterizable) applies only to signed fractional buses. Output Binary Point Position >= 0 Specifies the binary point location of the output. (Parameterizable)
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Table 65. Binary Point Casting Block I/O Formats (Part 2 of 2) (Note 1) I/O O Simulink (2), (3) O1[LO].[RO] VHDL O1: out STD_LOGIC_VECTOR({LO + RO - 1} DOWNTO 0) Type (4) Explicit
Figure 64 shows a design example with the Binary Point Casting block.
Figure 64. Binary Point Casting Block Example
Bus Builder
The Bus Builder block constructs an output bus from single-bit inputs. The output bus is signed integer, unsigned integer, or signed binary fractional format. You can specify the number of bits in each case. The HDL mapping of the Bus Builder block is a simple wire. The input MSB is at the bottom left of the symbol and the input LSB displays at the top left of the symbol. 1 The Bus Builder block does not support sign extension. Instead use a an AltBus block (Figure 63 on page 64). Table 66 shows the Bus Builder block parameters.
Table 66. Bus Builder Block Parameters (Part 1 of 2) Name Bus Type Value Signed Integer, Signed Fractional, Unsigned Integer The number format of the bus. Description
Specifies the number of bits to the left of the binary point, including the sign bit.
66
Table 66. Bus Builder Block Parameters (Part 2 of 2) Name Value Description Specifies the number of bits to the right of the binary point. This parameter applies only to signed binary fractional buses.
(Note 1) VHDL Type (4) Explicit ... Explicit ... Explicit Explicit
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Bus Concatenation
The Bus Concatenation block concatenates two buses. The block has two inputs, a and b. These may be signed integer or unsigned integer. The output width is width(a) + width(b). Input a becomes the MSB part of the output, input b becomes the LSB part. Table 68 shows the Bus Concatenation block parameters.
Table 68. Bus Concatenation Block Parameters Name Output Is Signed Width of Input a Width of Input b Value On or Off >= 1 (Parameterizable) >= 1 (Parameterizable) Description Turn on if the output bus is signed. Specifies the width of the first bus to concatenate. Specifies the width of the second bus to concatenate.
I1: in STD_LOGIC_VECTOR({N1 - 1} DOWNTO 0) I2: in STD_LOGIC_VECTOR({N2 - 1} DOWNTO 0) O1: out STD_LOGIC_VECTOR({N1 + N2 - 1} DOWNTO 0)
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Bus Conversion
The Bus Conversion block extracts a subsection of a bus including bus type and width conversion. If the input is in signed binary fractional format, you should specify a left bit width (number of integer bits) and a right bit width (number of fractional bits) for the output bus. If the input is an integer, specify the input bit to connect to the output LSB. 1 If Input Bit Connected To Output LSB is on, the input bit indexing starts from 0. Do not use this option with signed fractional type or with rounding. Table 610 shows the Bus Conversion block parameters.
Table 610. Bus Conversion Block Parameters Name Bus Type Value Description
Signed Integer, The input bus type for the simulator, VHDL or both. Signed Fractional, Unsigned Integer >= 0 Specifies the number of bits to the left of the binary point including the (Parameterizable) sign bit. >= 0 Specifies the number of bits to the right of the binary point. This parameter (Parameterizable) applies only to signed binary fractional buses.
Output [number of bits].[] >= 0 Specifies the number of bits to the left of the binary point. (Parameterizable) Output [].[number of bits] >= 0 Specifies the number of bit on the right side of the binary point. This (Parameterizable) parameter applies only to signed binary fractional buses. Input Bit Connected to Output LSB Round Saturate >= 0 Specifies the slice of the input bus to use. This parameter designates the (Parameterizable) start point of the slice that is transferred to the output LSB and applies to signed or unsigned integer buses only. On or Off On or Off Turn on to round the output away from zero. When this option is off, the LSM is truncated: <int>(input +0.5). When this option is on, if the output is greater than the maximum positive or negative value to be represented, the output is forced (or saturated) to the maximum positive or negative value, respectively. If off, the MSB is truncated.
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Bus Splitter
The Bus Splitter block splits a bus into single-bit outputs. The output ports are numbered from LSB to MSB. You can specify the bus type that you want to use, and specify the number of bits on either side of the binary point. Table 612 shows the Bus Splitter block parameters.
Table 612. Bus Splitter Block Parameters Name Bus Type Value Signed Integer, Signed Fractional, Unsigned Integer The number format of the bus. Description
Specifies the number of bits to the left of the binary point, including the sign bit. Specifies the number of bits to the right of the binary point. This parameter applies only to signed binary fractional buses.
610
Table 613. Bus Splitter Block I/O Formats (Part 2 of 2) (Note 1) I/O O O1[1] On[1]
Notes to Table 67:
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit. (2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit. (3) I1[L].[R] is an input port. O1[L].[R] is an output port. (4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
VHDL
Constant
The Constant block specifies a constant bus. The options available depend on the selected bus type. Table 614 shows the Constant block parameters.
Table 614. Constant Block Parameters (Part 1 of 2) Name Constant Value Bus Type Value Double (Parameterizable) Signed Integer, Signed Fractional, Unsigned Integer, Single Bit Description Specifies the constant value that is formatted with the specified bus type. The number format of the bus.
Specifies the number of bits to the left of the binary point, including the sign bit. This parameter does not apply to single-bit buses. Specifies the number of bits to the right of the binary point. This parameter applies only to signed fractional buses.
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Table 614. Constant Block Parameters (Part 2 of 2) Name Rounding Mode Value Description
Truncate, The rounding mode. Refer to the description of the Round block for more Round Towards Zero, information about the rounding modes. Round Away From Zero, Round To Plus Infinity, Convergent Rounding Wrap, Saturate On or Off User defined (Parameterizable) The saturation mode. Turn on to explicitly specify the clock name. Specifies the name of the required clock signal.
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Extract Bit
The Extract Bit block reads a Simulink bus in the specified format and outputs the single bit specified. The selected bit is indexed starting from zero for the LSB and increasing to (total bit width - 1) for the MSB. Table 616 shows the Extract Bit block parameters.
Table 616. Extract Bit Block Parameters Name Bus Type Value Signed Integer, Signed Fractional, Unsigned Integer Description Specifies the number format of the bus.
>= 0 (Parameterizable) Specifies the number of bits to the left of the binary point, including the sign bit. >= 0 (Parameterizable) Specifies the number of bits to the right of the binary point.
Select the Bit to be >= 0 (Parameterizable) Specifies the input bit to extract. Extracted From the Bus
Figure 610 shows a design example with the Extract Bit block.
Figure 610. Extract Bit Block Example
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Global Reset
The Global Reset (or SCLR) block provides a single bit reset signal. All signals driven by the block are connected to the global reset for that clock domain. In simulation, this block outputs a constant 0. Table 618 shows the Global Reset block parameters.
Table 618. Global Reset Block Parameters Name Specify Clock Clock On or Off User defined (Parameterizable) Value Description Turn on to explicitly specify the clock name. Specifies the name of the required clock signal.
GND
The GND block is a single bit that outputs a constant 0. Table 620 shows the GND block parameters.
Table 620. GND Block Parameters Name Specify Clock Clock On or Off User defined (Parameterizable) Value Description Turn on to explicitly specify the clock name. Specifies the name of the required clock signal.
614
Input
The Input block defines the input boundary of a hardware system and casts floating-point Simulink signals (from generic Simulink blocks) to signed binary fractional format (feeding DSP Builder blocks). Table 622 shows the Input block parameters.
Table 622. Input Block Parameters Name Bus Type Value Signed Integer, Signed Fractional, Unsigned Integer, Single Bit Description Specifies the number format of the bus.
[number of bits].[] >= 0 (Parameterizable) [].[number of bits] >= 0 (Parameterizable) Specify Clock Clock On or Off User defined (Parameterizable)
Specifies the number of bits to the left of the binary point, including the sign bit. This parameter does not apply to single-bit buses. Specifies the number of bits to the right of the binary point. This parameter applies only to signed fractional buses. Turn on to explicitly specify the clock name. Specifies the name of the required clock signal.
Table 623 on page 615 shows the Input block I/O formats.
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Table 623. Input Block I/O Formats I/O I O Simulink (2), (3) I1[L1].[R1] O1[LP].[RP]
Non-synthesizable Input
The Non-synthesizable Input block marks an entry point to a non-synthesizable DSP Builder system. Use a corresponding Non-synthesizable Output block to mark the exit point. Because DSP Builder registers its own type with Simulink, this block is required when the DSP Builder blocks are not intended to be synthesized. Table 624 shows the Non-synthesizable Input block parameters.
Table 624. Non-synthesizable Input Block Parameters Name Bus Type Value Signed Integer, Signed Fractional, Unsigned Integer, Single Bit Description Specifies the number format of the bus.
[number of bits].[] >= 0 (Parameterizable) [].[number of bits] >= 0 (Parameterizable) Specify Clock Clock On or Off User defined (Parameterizable)
Specifies the number of bits to the left of the binary point, including the sign bit. This parameter does not apply to single-bit buses. Specifies the number of bits to the right of the binary point. This parameter applies only to signed fractional buses. Turn on to explicitly specify the clock name. Specifies the name of the required clock signal.
616
Non-synthesizable Output
The Non-synthesizable Output block marks an exit point from a non-synthesizable DSP Builder system. Use a corresponding Non-synthesizable Input block to mark the entry point. Because DSP Builder registers its own type with Simulink, this block is required when the DSP Builder blocks are not intended to be synthesized. You can also use this block to create an non-synthesizable output from a synthesizable system. You can optionally specify the external Simulink type. If set to Simulink Fixed Point Type, the bit width is the same as the DSP Builder input type. If set to Double, the width may be truncated if the bit width is greater than 52. Table 626 shows the Non-synthesizable Output block parameters.
Table 626. Non-synthesizable Output Block Parameters Name Bus Type Value Inferred, Signed Integer, Unsigned Integer, Signed Fractional, Single Bit Description Specifies the number format of the bus.
[number of bits].[] >= 0 (Parameterizable) [].[number of bits] >= 0 (Parameterizable) External Type
Specifies the number of bits to the left of the binary point, including the sign bit. This parameter does not apply to single-bit buses. Specifies the number of bits to the right of the binary point. This parameter applies only to signed fractional buses.
Inferred, Specifies whether the external type is inferred from the Simulink block it Simulink Fixed Point Type, is connected to or explicitly set to either Simulink Fixed Point or Double Double type. The default is Inferred.
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Output
The Output block defines the output boundary of a hardware system and casts signed binary fractional format (from DSP Builder blocks) to floating-point Simulink signals (feeding generic Simulink blocks). Output blocks map to output ports in VHDL and mark the edge of the generated system. You normally connect these blocks to Simulink simulation blocks in your testbench. Their outputs should not be connected to other Altera blocks. You can optionally specify the external Simulink type. If set to Simulink Fixed Point Type, the bit width is the same as the input. If set to Double, the width may be truncated if the bit width is greater than 52. Table 628 shows the Output block parameters.
Table 628. Output Block Parameters Name Bus Type Value Inferred, Signed Integer, Unsigned Integer, Signed Fractional, Single Bit The number format of the bus. Description
[number of bits].[] >= 0 (Parameterizable) [].[number of bits] >= 0 (Parameterizable) External Type
Specifies the number of bits to the left of the binary point, including the sign bit. This parameter does not apply to single-bit buses. Specifies the number of bits to the right of the binary point. This parameter applies only to signed fractional buses.
Inferred, Specifies whether the external type is inferred from the Simulink block it Simulink Fixed Point Type, is connected to or explicitly set to either Simulink Fixed Point or Double Double type. The default is Inferred.
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Round
The Round block rounds the input to the closest possible representation in the specified output bus format. If the nearest two possibilities are equidistant, you can specify from the available rounding modes:
Truncate: Remove discarded bits without changing the other bits; effectively, specify the lower value. This is the simplest and fastest mode to implement in hardware. Round Towards Zero: Specify the value closer to zero. Round Away From Zero: Specify the value further from zero (round downwards for negative values, upwards for positive values). This was the rounding behavior in DSP Builder version 7.0 and before. When using this mode the maximum positive value overflows the available representation. For example, when rounding from an 8-bit signed input to a 6-bit signed output, 01111111 (127) becomes 100000 (-32). If you use this mode, it is best to use saturation logic to prevent this from happening. Round To Plus Infinity: Specify the higher value. Convergent Rounding: Specify the even value. For a large sample of random input values there is no bias on average the same number of values round upwards as downwards.
When using Simulink fixed-point types, MATLAB supports the following rounding options: Zero, Nearest (equivalent to Round Away From Zero), Ceiling, Floor (equivalent to Truncate), and Simplest. The MATLAB Zero and Ceiling modes round all intermediate values up or down and have no DSP Builder equivalent. This is because the DSP Builder modes (except Truncate) always specify the nearest representable value and the rounding mode applies only to values that are equidistant from two representable values. For example, 0.9 rounds to 1 (for all modes except Truncate) but the MATLAB Zero mode rounds 0.9 to 0. Similarly 0.1 rounds to 0 but the MATLAB Ceiling mode rounds 0.1 to 1. Table 630 shows the Round block parameters.
Table 630. Round Block Parameters (Part 1 of 2) Name Bus Type Value Signed Integer, Signed Fractional, Unsigned Integer >= 2 (Parameterizable) >= 0 (Parameterizable) >= 0 (Parameterizable) The number format of the bus. Description
Specifies the number of bits to the left of the binary point, including the sign bit. This parameter does not apply to single-bit buses. Specifies the number of bits to the right of the binary point. This parameter applies only to signed fractional buses. Specifies how many bits to remove.
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Table 630. Round Block Parameters (Part 2 of 2) Name Rounding Mode Value Truncate, Round Towards Zero, Round Away From Zero, Round To Plus Infinity, Convergent Rounding On or Off On or Off The rounding mode. Description
Turn on if you want to pipeline the function. Turn on to use the clock enable input (ena). Turn on to use the asynchronous clear input (aclr).
(1) These ports are available only when you enable pipeline.
Explicit
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Saturate
The Saturate block limits output to a maximum value. If the output is greater than the maximum positive or negative value to be represented, the output is forced (or saturated) to the maximum positive or negative value, respectively. Alternatively, you can truncate the MSB. Table 632 shows the Saturate block parameters.
Table 632. Saturate Block Parameters Name Input Bus Type Value Signed Integer, Signed Fractional, Unsigned Integer >= 2 (Parameterizable) >= 0 (Parameterizable) >= 0 (Parameterizable) Saturate, Truncate MSB, Enter Saturation Limits Integer (Parameterizable) Description The number format of the bus.
[number of bits].[] [].[number of bits] Number of MSB Bits to Remove Saturation Type
Specifies the number of bits to the left of the binary point, including the sign bit. This parameter does not apply to single-bit buses. Specifies the number of bits to the right of the binary point. This parameter applies only to signed fractional buses. Specifies how many bits to remove. Saturate, truncate, or specify the saturation limits for the output.
Specifies the upper saturation limit when Saturation Type is set to Enter Saturation Limits. Specifies the lower saturation limit when Saturation Type is set to Enter Saturation Limits. Turn on if you want to pipeline the function. Turn on to use the saturation occurred input (sat_flag). Turn on to use the clock enable input (ena). Turn on to use the asynchronous clear input (aclr).
Lower Saturation Limit Integer (Parameterizable) Enable Pipeline Use Saturation Occurred Port Use Enable Port (1) Use Asynchronous Clear Port (1)
Note to Table 630:
(1) These ports are available only when you enable pipeline.
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Simulink (2), (3) I1[L1].[R1] I2: in STD_LOGIC I3: in STD_LOGIC I4: in STD_LOGIC
Explicit
VCC
The VCC block outputs a single-bit constant 1. Table 634 shows the VCC block parameters.
Table 634. VCC Block Parameters Name Specify Clock Clock Value On or Off User defined (Parameterizable) Description Turn on to explicitly specify the clock name. Specifies the name of the required clock signal.
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The Rate Change library contains the following blocks that allow you to control the clock assignment to registered DSP Builder blocks, such as Delay or Increment Decrement blocks:
For information about the Clock and Clock_Derived blocks, refer to Chapter 1, AltLab Library. For information about the Dual-Clock FIFO block, refer to Chapter 9, Storage Library.
Multi-Rate DFF
The Multi-Rate DFF block implements a D-type flipflop and typically specifies sample rate transitions. 1 Simulation of the Multi-Rate DFF block may not match hardware because of limitations in the way DSP Builder simulates multiclock designs. Typically, differences may occur when moving from a slow to a fast clock domain. In such cases, an error message of the following form issues in the MATLAB command window: Warning: simulation will not match hardware If your design allows, increasing the latency of the Multi-Rate DFF block to at least one slow clock period should result in correct simulation results. If the clocks are asynchronous, simulations do not match hardware. Do not use a Multi-Rate DFF block to cross asynchronous clock domains, otherwise data is corrupted or lost. Use a Dual-Clock FIFO block instead to guarantee correct data transfer. Table 71 shows the Multi-Rate DFF block inputs and outputs.
Table 71. Multirate DFF Block Inputs and Outputs Signal d q ena sclr Direction Input Output Input Input Input data port. Output data port. Optional clock enable port. Optional synchronous clear port. Description
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>= 1 Adds more pipeline stages to the block. Increased delay reduces the likelihood of (Parameterizable) metastability. On or Off User specified On or Off On or Off Turn on to use the base clock. Specify the name of the clock signal. Turn on to use the clock enable input (ena). Turn on to use the synchronous clear input (sclr).
Implicit
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PLL
The PLL block generates a clock signal that is based on a reference clock. Phase-locked loops (PLL) have become an important building block of most high-speed digital systems today. Their use ranges from improving timing as zero delay lines to full-system clock synthesis. The Arria, Cyclone, and Stratix series device families offer advanced on-chip PLL features that were previously offered only by the most complex discrete devices. Each PLL has multiple outputs that can source any of the 40 system clocks in the devices to give you complete control over your clocking needs. The PLLs offer full frequency synthesis capability (the ability to multiply up or divide down the clock period) and phase shifting for optimizing I/O timing. Additionally, the PLLs have high-end features such as programmable bandwidth, spread spectrum, and clock switchover. The PLL block generates internal clocks with frequencies that are multiples of the frequency of the system clock. PLLs on the FPGA can simultaneously multiply and divide the reference clock. The PLL block checks the validity of the parameters. 1 If you use a PLL block to define clock signals when there is no Clock block in your design, the PLL-derived clocks might not pass the derived period correctly to the blocks referencing the PLL-derived clock. Always explicitly include a Clock block with a PLL block. The number of PLL internal clock outputs supported by each device family depends on the specific device packaging. f For information about the built-in PLLs, refer to the device handbook for the device family you target. The following restrictions apply when you use a PLL block:
Your design may contain more than one PLL block but they must be at the top level. Each output clock of the PLL has a zero degree phase shift and 50% duty cycle.
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Table 74. PLL Block Parameters (Part 2 of 2) Name Export As Output Pin
Note to Table 74:
(1) Refer to the device documentation for the device family you target.
Value On or Off
Tsamp
The Tsamp block sets the clock domain inherited by all downstream blocks. 1 When you use the Tsamp block, you must select a variable step solver in the Simulink configuration parameters. Unless the downstream clock is an exact, slower multiple of the upstream clock, the simulation results may not match ModelSim; in this case it is better to use a Multi-Rate DFF block. Table 75 shows the Tsamp block inputs and outputs.
Table 75. Tsamp Block Inputs and Outputs Signal <unnamed> <unnamed> Direction Input Output Input data port. Output data port. Description
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This design example is available in the <DSP Builder install path>\DesignExamples \Demos\Filters\Filters\CicFilter directory.
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8. Simulation Library
The Simulation library contains the following simulation-only blocks that do not synthesize to HDL when Signal Compiler runs:
External RAM
The External RAM block is a simulation model of an external RAM. The External RAM block stores and retrieves data from a range of addresses and is compatible with the Avalon-MM interface. f For information about the Avalon-MM interface, refer to Avalon Interface Specifications. This block is not cycle-accurate and a warning issues if you use it in a gate level (cycle-accurate) simulation. 1 If 64 or 128 bit data width is specified, the block attempts to use a Simulink fixed-point license. If you do not have a Simulink fixed-point license., you can only use 8, 16 or 32 bit data widths. For information about fixed-point licenses, refer to the Simulink Help. This is a simulation only block, and does not generate any HDL when Signal Compiler is run. Table 81 shows the External RAM block inputs and outputs.
Table 81. External RAM Block Inputs and Outputs (Part 1 of 2) Signal WriteData WriteAddress ReadAddress Read Write ReadData Direction Input Input Input Input Input Output Description Data lines for write transfers. Not required if there are no write transfers. If used, also use Write. Address lines for write transfers. Address lines for read transfers. Read request signal. Not required if there are no read transfers. If used, also use ReadData. Write request signal. Not required if there are no write transfers. If used, also use WriteData. Data lines for read transfers. Not required if there are no read transfers. If used, also use Read. Stalls the interface when the Avalon-MM interface cannot respond immediately to a write request.
WriteWaitRequest Output
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Table 81. External RAM Block Inputs and Outputs (Part 2 of 2) Signal ReadWaitRequest ReadDataValid Direction Output Output Description Stalls the interface when the Avalon-MM interface cannot respond immediately to a read request. Marks the rising clock edge when ReadData is asserted. Indicates that valid data is present on the ReadData lines.
Description Specifies the number of bits for the data. No other values are supported. 64 and 128 bit data widths require a Simulink fixed-point license. Specifies the number of bits n for the address. Specifies a fixed number of wait states for each write transfer. Specifies the latency for pipelined read transfers.
(Note 1) Specifies the total size of the RAM in bytes (the number of addresses when you use a range of addresses).
12n (Note 1) Specifies an offset for the RAM start address (the start address when you use a range of addresses.
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Table 83 shows the Multiple Port External RAM block inputs and outputs.
Table 83. Multiple Port External RAM Block Inputs and Outputs Signal WriteDataN WriteAddressN WriteEnableN WriteBurstCountN ReadAddressN ReadEnableN ReadBurstCountN Direction Input Input Input Input Input Input Input Description Data lines for write transfers on port N. Address lines for write transfers on port N. Write enable for transfers on port N. Write burst count for transfers on port N. Address lines for read transfers on port N. Read enable for transfers on port N. Read burst count for transfers on port N. Stalls the interface when the Avalon-MM interface cannot respond immediately to a write request on port N. Data lines for read transfers on port N. Marks the rising clock edge when ReadDataN is asserted. Indicates that valid data is present on the ReadDataN lines. Stalls the interface when the Avalon-MM interface cannot respond immediately to a read request on port N.
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Value
Description Specifies the number of write ports. Specifies the number of read ports. Specifies the number of bits for the data. No other values are supported. 64 and 128 bit data widths require a Simulink fixed-point license. Specifies the number of bits n for the address. Specifies a fixed number of wait states for each write transfer. Specifies the latency for pipelined read transfers.
(Note 1) Specifies the total size of the RAM in bytes (the number of addresses when you use a range of addresses).
12n (Note 1) Specifies an offset for the RAM start address (the start address when you use a range of addresses.
9. Storage Library
The Storage library contains the following blocks, which support storage and associated control functions:
Delay Down Sampling Dual-Clock FIFO Dual-Port RAM FIFO Buffer LUT (Look-Up Table) Memory Delay Parallel To Serial ROM Serial To Parallel Shift Taps Single-Port RAM True Dual-Port RAM Up Sampling
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Delay
The Delay block delays the incoming data by an amount specified by the number of pipeline stages. The block accepts any data type as inputs. Table 91 shows the Delay block inputs and outputs.
Table 91. Delay Block Inputs and Outputs Signal <unnamed> ena sclr <unnamed> Direction Input Input Input Output Input data port. Optional clock enable port. Optional synchronous clear port. Output data port. Description
Number of Pipeline User Defined Specify the pipeline length of the block. The delay must be greater than or equal to Stages (Parameterizable) 1. Clock Phase Selection User Defined Specify the phase selection with a binary string, where a 1 indicates the phase in which the Delay block is enabled. For example: 1The block is always enabled and captures all data passing through the block (sampled at the rate 1). 10The block is enabled every other phase and every other data (sampled at the rate 1) passes through. 0100The block is enabled on the second phase of and only the second data of (sampled at the rate 1) passes through. That is, the data on phases 1, 3, and 4 do not pass through the delay block. Use Enable Port Use Synchronous Clear Port Reset To Constant (Non-Zero) Value Reset Value On or Off On or Off On or Off Turn on to use the clock enable input (ena). Turn on to use the synchronous clear input (sclr). Turn on to specify a non-zero reset value. Specifying a reset value increases the hardware resources.
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Table 93. Delay Block I/O Formats (Part 2 of 2) (Note 1) I/O O Simulink (2), (3) O1[L1].[R1] VHDL O1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) Type (4) Implicit
Down Sampling
The Down Sampling block decreases the output sample rate from the input sample rate. The output data is sampled at every Nth cycle where N is the down sampling rate. The output data is then held constant for the next N input cycles. Table 94 shows the Down Sampling block inputs and outputs.
Table 94. Down Sampling Block Inputs and Outputs Signal d q Direction Input Output Input data port. Output data port. Description
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Dual-Clock FIFO
The Dual-Clock FIFO block implements a parameterized, dual-clock FIFO buffer controlled by separate read-side and write-side clocks. 1 The Dual-Clock FIFO block simulation in Simulink is functionally equivalent to hardware, but not cycle-accurate. Table 97 shows the Dual-Clock FIFO block inputs and outputs.
Table 97. Dual-Clock FIFO Block Inputs and Outputs (Part 1 of 2) Signal d wrreq rdreq aclr q rdfull rdempty rdusedw Direction Input Input Input Input Output Output Output Output Data input to the FIFO buffer. Write request control. The d[] port is written to the FIFO buffer. Read request control. The oldest data in the FIFO buffer goes to the q[] port. Optional asynchronous clear input, which flushes the FIFO. Data output from the FIFO buffer. Optional output synchronized to the read clock. Indicates that the FIFO buffer is full and disables the wrreq port. Optional output synchronized to the read clock. Indicates that the FIFO buffer is empty and disables the rdreq port. Optional output synchronized to the read clock. Indicates the number of words that are in the FIFO buffer. Description
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Table 97. Dual-Clock FIFO Block Inputs and Outputs (Part 2 of 2) Signal wrfull wrempty wrusedw Direction Output Output Output Description Optional output synchronized to the write clock. Indicates that the FIFO buffer is full and disables the wrreq port. Optional output synchronized to the write clock. Indicates that the FIFO buffer is empty and disables the rdreq port. Optional output synchronized to the write clock. Indicates the number of words that are in the FIFO buffer.
Number of Words in the FIFO Integer (Parameterizable) Input Bus Type Signed Integer, Unsigned Integer, Signed Fractional >= 0 (Parameterizable) >= 0 (Parameterizable)
Specify the number of bits stored on the left side of the binary point. Specify the number of bits to the right of the binary point. This option applies only to signed fractional formats.
AUTO, M512, M4K, The FPGA RAM type. Some memory types are not available for all M9K, MLAB, M144K device types. Turn on to use the base clock signal for the read-side clock. Specify the read-side clock signal when not using the base clock. Turn on to use the base clock signal for the write-side clock. Specify the write-side clock signal when not using the base clock. Turn on to use the read-side empty port (rdempty). Turn on to use the read-side full port (rdfull). Turn on to use the read-side words port (rdusedw). Turn on to use the write-side empty port (wrempty). Turn on to use the write-side empty port (wrfull). Turn on to use the write-side words port (wrusedw). Turn on to use the asynchronous clear port (aclr). Turn on to register the output ports. This mode is faster but larger. Turn on to implement the FIFO buffer with logic cells only. Turn on to use the show-ahead mode of read-request. User defined On or Off User defined On or Off On or Off On or Off On or Off On or Off On or Off
Use Base Clock for Read Side On or Off Read-Side Clock Use Base Clock for Write Side Write-Side Clock Use Read-Side Synchronized EMPTY Port Use Read-Side Synchronized FULL Port Use Read-Side Synchronized USEDW Port Use Write-Side Synchronized EMPTY Port Use Write-Side Synchronized EMPTY Port Use Write-Side Synchronized USEDW Port Register Output Implement FIFO with logic Cells Only Use Show-Ahead Mode of Read Request
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(Note 1) VHDL Type (4) Explicit Explicit Explicit Explicit Explicit Explicit Explicit Explicit Explicit-optional Explicit-optional
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) I2: in STD_LOGIC I3: in STD_LOGIC O1: out STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) O2: out STD_LOGIC O3: out STD_LOGIC O4: out STD_LOGIC O5: out STD_LOGIC O6: out STD_LOGIC_VECTOR({L2 - 1} DOWNTO 0) O7: out STD_LOGIC_VECTOR({L2 - 1} DOWNTO 0)
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Dual-Port RAM
The Dual-Port RAM block maps data to an embedded RAM (embedded array block, EAB; or embedded system block, ESB) in Altera devices. The read and write ports are separate. The Dual-Port RAM block accepts any data type as input. The input port always registers and the output port can optionally be registered. 1 The input address bus must be unsigned. The clock enable signal (ena) bypasses any output register. Turning on DONT_CARE may give a higher fMAX for your design, especially if the memory implements as a MLAB. When this option is on, the output is not double-registered (and therefore, in the case of MLAB implementation, uses fewer external registers), and you gain an extra half-cycle on the output. The default is off, which outputs old data for read-during-write. f For more information about this option, refer to the Read-During-Write Output Behavior section in the RAM Megafunction User Guide. The contents of the RAM are pre-initialized to zero by default. Use an Intel Hexadecimal (.hex) file or MATLAB array to specify them. Use the Quartus II software to generate a.hex file that must be in your DSP Builder working directory. The data in a standard .hex file is formatted in multiples of eight and the output bit width should also be in multiples of eight. The Quartus II software does allow you to create non-standard .hex files but pads 1's to the front for negative numbers to make them multiples of eight. Thus, large numbers with less bits may be treated as negative numbers. A warning issues if you specify a non-standard .hex file. If you require a different bit width, you should set the output bit width to the same as that in the .hex file but use an AltBus block to convert to the required bit width. DSP Builder supports 32-bit addressing with extended linear address records in the .hex file. f For instructions on creating this file, refer to Creating a Memory Initialization File or Hexadecimal (Intel-Format) File in the Quartus II Help. The MATLAB array parameter must be a one dimensional MATLAB array with a length less than or equal to the number of words. Specify the array from the MATLAB workspace or directly in the MATLAB Array box. Table 910 shows the Dual-Port RAM block inputs and outputs.
Table 910. Dual-Port RAM Block Inputs and Outputs Signal d rd_add wr_add wren ena q_a Direction Input Input Input Input Input Output Input data port. Read address bus. Write address bus. Write enable. Optional clock enable port Output data port. Description
98
Specify the number of bits stored on the left side of the binary point. Specify the number of bits to the right of the binary point. This option applies only to signed fractional formats. The FPGA RAM memory block type. Some RAM memory types are not available for all device types. If you specify M-RAM, the RAM is always initialized to unknown in the hardware and simultaneous read/writes to the same address also give unknown in hardware. Simulink does not modify the unknowns , and comparisons with ModelSim shows differences. If the memory block type is set to AUTO, setting DONT_CARE gives more flexibility in RAM block placement. If the implementation is set to MLAB, the design uses fewer external registers, because the output is not double registered, and the resulting memory block can often be run at a higher fMax. However, the output in hardware when reading from and writing to the same address is unpredictable. In ModelSim simulation, unknowns (X) are output when reading from and writing to the same address. The Simulink simulation is unchanged whether or not you use this option, but a warning message issues on every simultaneous read/write to the same address. If you compare the simulation results to ModelSim, you see mismatches associated with any read/write to the same address events. When this option is set, ensure that the same address is not read from and written to at the same time or that your design does not depend on the read output in these circumstances. By default this option is off, and data is always read before write. Specify the initialization. If Blank is selected, the contents of the RAM are pre-initialized to zero. Specify the name of a .hex file, which must be in your DSP Builder working directory. For example: input.hex. DSP Builder supports 32-bit addressing with extended linear address records in the .hex file. Specify a one-dimensional MATLAB array with a length less than or equal to the number of words. For example: [0:1:15] Turn on to register the output port. Turn on to use the optional clock enable input (ena).
Use DONT_CARE when reading from and writing to the same address
On or Off
99
Table 911. Dual-Port RAM Block Parameters (Part 2 of 2) Name Clock Phase Selection Value User Defined Description Specify the phase selection with a binary string, where a 1 indicates the phase in which the block enables. For example: 1The block is always enabled and captures all data passing through the block (sampled at the rate 1). 10The block is enabled every other phase and every other data (sampled at the rate 1) passes through. 0100The block is enabled on the second phase of and only the second data of (sampled at the rate 1) passes through. That is, the data on phases 1, 3, and 4 do not pass through the block.
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) I2: in STD_LOGIC_VECTOR({L2 - 1} DOWNTO 0) I3: in STD_LOGIC_VECTOR({L3 - 1} DOWNTO 0) I4: in STD_LOGIC I5: in STD_LOGIC O1: out STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
Explicit
910
FIFO Buffer
The FIFO block implements a parameterized, single-clock FIFO buffer. 1 Reading an empty FIFO buffer may give unknown (X) in hardware. Table 913 shows the FIFO block inputs and outputs.
Table 913. FIFO Block Inputs and Outputs Signal d rreq sclr q full usdw Direction Input Input Input Output Output Output Data input to the FIFO buffer. Write request control. The d[] port is written to the FIFO buffer. Read request control. The oldest data in the FIFO buffer goes to the q[] port. Optional synchronous clear port that flushes the FIFO. Data output from the FIFO buffer. Indicates that the FIFO buffer is full and disables the wrreq port. Indicates that the FIFO buffer is empty and disables the rreq port. Indicates the number of words that are in the FIFO buffer. Description
wrreq Input
empty Output
[number of bits].[] [].[number of bits] Memory Block Type Use Synchronous Clear Port Implement FIFO with logic Cells Only
Specify the number of bits stored on the left side of the binary point including the sign bit. Specify the number of bits stored on the right side of the binary point. This option applies only to signed fractional.
AUTO, M512, M4K, The RAM block type. Some memory types are not available for all device M9K, MLAB, M144K types. On or Off On or Off Turn on to use the synchronous clear port (sclr). Turn on to implement the FIFO buffer with logic cells only. Turn on to use the show-ahead mode of read-request.
911
Simulink (2), (3) I1[L1].[R1] I2: in STD_LOGIC I3: in STD_LOGIC I4: in STD_LOGIC
O1: out STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) O2: out STD_LOGIC O3: out STD_LOGIC O4: out STD_LOGIC_VECTOR({L2 - 1} DOWNTO 0)
Explicit
912
Specify the number of data bits stored on the left side of the binary point including the sign bit. Specify the number of data bits stored on the right side of the binary point. This field must be a one-dimensional MATLAB array with a length smaller than 2 to the power of the address width. A warning is given if the values in the MATLAB array cannot be exactly represented in the chosen data format. Turn on to use the optional clock enable input (ena). Turn on to register the output result. When on, the look-up table implements as case conditions with the lpm_rom library of parameterized modules (LPM) function. You should turn on this option for large look-up tables, for example, greater than 8 bits. The input address always registers when this option is on. When register address is on, the input address bus generates. If you use LPM, the input address is always registered.
Register Address
On of Off
Memory Block Type AUTO, M512, M4K, The RAM block type. Some memory types are not available for all device types. M9K, MLAB, M144K
913
Memory Delay
The Memory Delay block implements a shift register that uses the Altera devices embedded memory blocks, when possible. You should typically use this block for delays greater than 3. Table 921 shows the Memory Delay block inputs and outputs.
Table 918. Memory Delay Block Inputs and Outputs Signal d ena sclr q Direction Input Input Input Output Input data port. Optional clock enable port. Optional synchronous clear port. Output data port. Description
Specify the number of data bits stored on the left side of the binary point including the sign bit. Specify the number of data bits stored on the right side of the binary point. When non-zero, adds pipeline stages to increase the data throughput. The clock enable and synchronous clear ports are available only if the block is registered (that is, if the number of pipeline stages is greater than or equal to 1).
AUTO, M512, M4K, The RAM block type. Some memory types are not available for all M9K, MLAB, M144K device types. On or Off Turn on to use the clock enable input. Turn on to use the synchronous clear port (sclr).
914
Implicit
Parallel To Serial
The Parallel To Serial block takes a bus input on load and outputs the individual bits one cycle at a time with either the MSB or LSB first. You can specify to continually output the last bit until the last load. For example, if input is an 8-bit unsigned integer value 1 the output is:
0 ... 0 ... 0 ... 0 ... 0 ... 0 ... 0 ... 1 ... 1 ... 1 ... 1 ............ <--------------- data values ---------------->|<- last bit repeated until next load ->
Alternatively, if this option is off, you can output 0 after the data has finished, that is, for the same example:
0 ... 0 ... 0 ... 0 ... 0 ... 0 ... 0 ... 1 ... 0 ... 0 ... 0 ............ <--------------- data values ---------------->|<----- zeros until next load ---->
915
Table 921 shows the Parallel To Serial block inputs and outputs.
Table 921. Parallel To Serial Block Inputs and Outputs Signal d load ena sclr sd Direction Input Input Input Input Output Parallel input port. Load port. Optional clock enable port. Optional synchronous clear port. Serial output port. Description
[number of bits].[] >= 0 (Parameterizable) [].[number of bits] >= 0 (Parameterizable) Serial Bit Order Repeat Last Bit Until Next Load Use Enable Port Use Synchronous Clear Port MSB First, LSB First On or Off On or Off On or Off
Specify the number of bits stored on the left side of the binary point. Specify the number of bits stored on the right side of the binary point. This option applies only to signed fractional formats. Transmit the MSB or LSB first. Turn on to repeat the last bit until the next load. Turn on to use the clock enable input. Turn on to use the synchronous clear port (sclr).
Simulink (2), (3) I1[L1].[R1] I2: in STD_LOGIC I3: in STD_LOGIC I4: in STD_LOGIC O1: out STD_LOGIC
Explicit
916
ROM
The ROM block maps data to an embedded RAM (embedded array block, EAB; or embedded system block, ESB) in Altera devices, with read-only access. The ROM block can store any data type. The address port is registered, and you can optionally register the data output port. 1 The input address bus must be Unsigned. The clock enable signal (ena) bypasses any output register. The contents of the ROM are pre-initialized from an Intel Hexadecimal (.hex) format file, or from a MATLAB array. Use the Quartus II software to generate a .hex file that you must save in your DSP Builder working directory. The data in a standard .hex file is formatted in multiples of eight and the output bit width should also be in multiples of eight. The Quartus II software does allow you to create non-standard .hex files but pads 1's to the front for negative numbers to make them multiples of eight. Thus, large numbers with less bits may be treated as negative numbers. A warning issues if you specify a non-standard .hex file. If you require a different bit width, you should set the output bit width to the same as that in the .hex file but use an AltBus block to convert to the required bit width. DSP Builder supports 32-bit addressing with extended linear address records in the .hex file. f For instructions on creating a .hex file, refer to Creating a Memory Initialization File or Hexadecimal (Intel-Format) File in the Quartus II Help. The MATLAB array parameter must be a one dimensional MATLAB array with a length less than or equal to the number of words. Specify the array from the MATLAB workspace or directly in the MATLAB Array box.
917
[number of bits].[] >= 0 (Parameterizable) [].[number of bits] >= 0 (Parameterizable) Memory Block Type Initialization Input HEX File
Specify the number of bits stored on the left side of the binary point including the sign bit. Specify the number of bits stored on the right side of the binary point. This option applies only to signed fractional formats.
AUTO, M512, M4K, The RAM block type. Some memory types are not available for all device types. M9K, MLAB, M144K From HEX file, From MATLAB array User defined Specify whether the ROM is initialized from a .hex file or from a MATLAB array. Specify the name of a.hex file that must be in your DSP Builder working directory. For example: input.hex. DSP Builder supports 32-bit addressing with extended linear address records in the .hex file.
MATLAB Array Register output Port Use Enable Port Clock Phase Selection
Specify a one-dimensional MATLAB array with a length less than or equal to the number of words. For example: [0:1:15] Turn on to register the output port. Turn on to use the optional clock enable input (ena). Specify the phase selection with a binary string, where a 1 indicates the phase in which the block is enabled. For example: 1The block is always enabled and captures all data passing through the block (sampled at the rate 1). 10The block is enabled every other phase and every other data (sampled at the rate 1) passes through. 0100The block is enabled on the second phase of and only the second data of (sampled at the rate 1) passes through. That is, the data on phases 1, 3, and 4 do not pass through the delay block.
918
Figure 99 shows an example with the ROM block that reads a 2568 ramp waveform .hex file.
Figure 99. ROM Block Example
Serial To Parallel
The Serial To Parallel block implements a serial (input sd) to parallel bus conversion (output d). Treat the input bit stream as either MSB first, or LSB first. Table 927 shows the Serial To Parallel block inputs and outputs.
Table 927. Serial To Parallel Block Inputs and Outputs Signal sd ena sclr d Direction Input Input Input Output Serial input port. Optional clock enable port. Optional synchronous clear port. Parallel output port. Description
919
[number of bits].[] >= 0 (Parameterizable) [].[number of bits] >= 0 (Parameterizable) Serial Bit Order Use Enable Port Use Synchronous Clear Port On or Off On or Off
Specify the number of bits stored on the left side of the binary point including the sign bit. Specify the number of bits stored on the right side of the binary point. This option applies only to signed fractional formats. Turn on to use the clock enable input. Turn on to use the synchronous clear port (sclr).
Explicit
920
Shift Taps
The Shift Taps block implements a shift register that you can use for filters or convolution. In Stratix IV, Stratix III, Stratix II, Stratix II GX, Stratix GX, Arria GX, Arria II GX, Cyclone III, Cyclone II, and Cyclone devices, the block implements a RAM-based shift register that is useful for creating very large shift registers efficiently. The block outputs occur at regularly spaced points along the shift register (that is, taps). In Stratix devices, this block implements in the small memory. Table 930 shows the Shift Taps block inputs and outputs.
Table 930. Shift Taps Block Inputs and Outputs Signal d ena t0tn sout Direction Input Input Output Output Data input port. Optional clock enable port. Output ports for taps 0n. Optional shift out port. Description
AUTO, M512, M4K, The RAM block type. Some memory types are not available for all device types. M9K, MLAB, M144K
921
Table 932. Shift Taps Block I/O Formats (Part 2 of 2) (Note 1) I/O O . Oi[L1].[R1] On[L1].[R1] On+1[1]
Notes to Table 932:
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit. (2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit. (3) I1[L].[R] is an input port. O1[L].[R] is an output port. (4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
VHDL O1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) Oi: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) . On: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) On+1: out STD_LOGIC
Explicit
Single-Port RAM
The Single-Port RAM block maps data to an embedded RAM (embedded array block, EAB; or embedded system block, ESB) in Altera devices. A single read/write port allow simple access. The Single-Port RAM block accepts any type as data input. The input port is registered, and the output port can optionally be registered. The input address bus must be Unsigned. The clock enable signal (ena) bypasses any output register. The contents of the RAM are pre-initialized to zero by default. Use an Intel Hexadecimal (.hex) file or a MATLAB array to specify them.
922
Use the Quartus II software to generate a .hex file that must be in your DSP Builder working directory. The data in a standard .hex file is formatted in multiples of eight and the output bit width should also be in multiples of eight. The Quartus II software does allow you to create non-standard .hex files but pads 1's to the front for negative numbers to make them multiples of eight. Thus, large numbers with less bits may be treated as negative numbers. A warning issues if you specify a non-standard .hex file. If you require a different bit width, you should set the output bit width to the same as that in the .hex file but use an AltBus block to convert to the required bit width. DSP Builder supports 32-bit addressing with extended linear address records in the .hex file. f For instructions on creating this file, refer to Creating a Memory Initialization File or Hexadecimal (Intel-Format) File in the Quartus II Help. The MATLAB array parameter must be a one dimensional MATLAB array with a length less than or equal to the number of words. Specify the array from the MATLAB work-space or directly in the MATLAB Array box. Table 933 shows the Single-Port RAM block inputs and outputs.
Table 933. Single-Port RAM Block Inputs and Outputs Signal d addr wren ena q_a Direction Input Input Input Input Output Input data port. Address bus. Write enable. Optional clock enable port Output data port. Description
[number of bits].[] >= 0 (Parameterizable) [].[number of bits] >= 0 (Parameterizable) Memory Block Type AUTO, M512, M4K, M-RAM, M9K, MLAB, M144K
Specify the number of bits stored on the left side of the binary point. Specify the number of bits to the right of the binary point. This option applies only to signed fractional formats. The FPGA RAM memory block type. Some memory types are not available for all device types. If you specify M-RAM, the RAM is always initialized to unknown in the hardware and simultaneous read/writes to the same address also give unknown in hardware. The unknowns are not modeled in Simulink, and comparisons with ModelSim shows differences. Specify the initialization. If Blank is selected, the contents of the RAM are pre-initialized to zero.
Initialization
923
Table 934. Single-Port RAM Block Parameters (Part 2 of 2) Name Input HEX File Value User defined Description Specify the name of a .hex file that must be in your DSP Builder working directory. For example: input.hex. DSP Builder supports 32-bit addressing with extended linear address records in the .hex file. MATLAB Array Register output Port Use Enable Port Clock Phase Selection User defined (Parameterizable) On or Off On or Off User Defined Specify a one-dimensional MATLAB array with a length less than or equal to the number of words. For example: [0:1:15] Turn on to register the output port. Turn on to use the optional clock enable input (ena). Specify the phase selection with a binary string, where a 1 indicates the phase in which the block is enabled. For example: 1The block is always enabled and captures all data passing through the block (sampled at the rate 1). 10The block is enabled every other phase and every other data (sampled at the rate 1) passes through. 0100The block is enabled on the second phase of and only the second data of (sampled at the rate 1) passes through. That is, the data on phases 1, 3, and 4 do not pass through the delay block.
VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) I2: in STD_LOGIC_VECTOR({L2 - 1} DOWNTO 0) I3: in STD_LOGIC I4: in STD_LOGIC O1: out STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
Explicit
924
925
The input address bus must be Unsigned. The clock enable signal (ena) bypasses any output register. c If you write to the same address simultaneously with the a and b inputs, the data written to the RAM is indeterminate (corrupt). In ModelSim simulations, the data at this address is set to Unknown (all bits X). In DSP Builder simulation, the data at this address is set to zero, and a warning is given:
"Warning: True Dual-Port RAM: simultaneous a and b side writing to address <addr>. Memory contents at this address will be Unknown (X) in hardware."
If this data is read, DSP Builder warns that you are reading corrupt data:
"Warning: True Dual-Port RAM: <a|b>-side reading corrupt RAM data at address <addr>. Memory contents at this address will be Unknown (X) in hardware."
If you execute a testbench comparison to hardware, you may get simulation mismatches if you are making use of corrupt data in your design or outputting the read memory contents to a pin. Table 936 shows the True Dual-Port RAM block inputs and outputs.
Table 936. True Dual-Port RAM Block Inputs and Outputs Signal data_a addr_a wren_a data_b addr_b wren_b ena q_a q_b Direction Input Input Input Input Input Input Input Output Output Input data port a Address bus a. Write enable a Input data port b Address bus b Write enable b Optional clock enable port Output data port a Output data port b Description
Specify the number of bits stored on the left side of the binary point. Specify the number of bits to the right of the binary point. This option applies only to signed fractional formats.
926
Table 937. True Dual-Port RAM Block Parameters (Part 2 of 2) Name Memory Block Type Value AUTO, M512, M4K, M-RAM, M9K, MLAB, M144K Description The FPGA RAM memory block type. Some memory types are not available for all device types. If you specify M-RAM, the RAM is always initialized to unknown in the hardware and simultaneous read/writes to the same address give unknown in hardware. The unknowns are not modeled in Simulink, and comparisons with ModelSim shows differences. If the memory block type is set to AUTO, setting DONT_CARE gives more flexibility in RAM block placement. If the implementation is set to MLAB, the design uses fewer external registers, because the output is not double registered, and the resulting memory block can often be run at a higher fMax. However, the output in hardware when reading from and writing to the same address is unpredictable. In ModelSim simulation, unknowns (X) are output when reading from and writing to the same address. The Simulink simulation is unchanged whether or not you use this option, but a warning message issues on every simultaneous read/write to the same address. If you compare the simulation results to ModelSim, you see mismatches associated with any read/write to the same address events. When this option is set, ensure that the same address is not read from and written to at the same time or that your design does not depend on the read output in these circumstances. By default this option is off, and data is always read before write. Specify the initialization. If Blank is selected, the contents of the RAM are pre-initialized to zero. Specify the name of an .hex file, which must be in your DSP Builder working directory. For example: input.hex. DSP Builder supports 32-bit addressing with extended linear address records in the .hex file. MATLAB Array Register output Ports Use Enable Port Clock Phase Selection User defined (Parameterizable) On or Off On or Off User Defined Specify a one-dimensional MATLAB array with a length less than or equal to the number of words. For example: [0:1:15] Turn on to register the output ports. Turn on to use the optional clock enable input (ena). Specify the phase selection with a binary string, where a 1 indicates the phase in which the block is enabled. For example: 1The block is always enabled and captures all data passing through the block (sampled at the rate 1). 10The block is enabled every other phase and every other data (sampled at the rate 1) passes through. 0100The block is enabled on the second phase of and only the second data of (sampled at the rate 1) passes through. That is, the data on phases 1, 3, and 4 do not pass through the block.
Use DONT_CARE when reading from and writing to the same address
On or Off
927
Table 938 shows the True Dual-Port RAM block I/O formats.
Table 938. True Dual-Port RAM Block I/O Formats I/O I Simulink (2), (3) I1[L1].[R1] I2[L2].[0] I3[L2].[0] I4[L1].[R1] I5[L2].[0] I6[L2].[0] I7[1] I8[1] O O1[L1].[R1]
Notes to Table 912:
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit. (2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit. (3) I1[L].[R] is an input port. O1[L].[R] is an output port. (4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) I2: in STD_LOGIC_VECTOR({L2 - 1} DOWNTO 0) I3: in STD_LOGIC_VECTOR({L3 - 1} DOWNTO 0) I4: in STD_LOGIC_VECTOR({L4 + R4 - 1} DOWNTO 0) I5: in STD_LOGIC_VECTOR({L5 - 1} DOWNTO 0) I6: in STD_LOGIC_VECTOR({L6 - 1} DOWNTO 0) I7: in STD_LOGIC I8: in STD_LOGIC O1: out STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
Explicit
Figure 913 shows an example with the True Dual-Port RAM block.
Figure 913. True Dual-Port RAM Block Example
928
Up Sampling
The Up Sampling block increases the output sample rate from the input sample rate. The output data is sampled every N cycles where N is equal to the up sampling rate. The output holds this value for 1 cycle, then for the next N-1 cycles the output is zero. Table 939 shows the Up Sampling block inputs and outputs.
Table 939. Up Sampling Block Inputs and Outputs Signal d q Direction Input Output Input data port. Output data port. Description
Table 101 shows the parameters that you can e set in the State Machine wizard.
Table 101. State Machine Wizard Parameters Name Which reset mode do you want to use Reset is active-high Register the output ports Value Synchronous, Asynchronous On, Off On, Off Description Specifies whether the state machine has a synchronous or asynchronous reset. Turn on to uses an active-high reset or off if you want an active-low reset. Turn on to register the state machine output ports.
102
Table 101. State Machine Wizard Parameters Name States Input ports State transitions Value user specified user specified user specified Description You can specify any number of state names that must be valid HDL identifiers. You can specify any number of input port names that must be valid HDL identifiers. You can specify any number of conditional statements for the transitions between source and destination states. Turn on to always transition to the source state if not all transition conditions are specified. You can specify any number of output port names that must be valid HDL identifiers. You can specify actions assigned to each output port.
Transition to source On, Off state if not specified Output ports Action conditions user specified user specified
Use Verilog HDL syntax to specify the conditional statements that you specify for state transitions and output actions. Table 102 shows the operators you can use to define a conditional expression.
Table 102. State Machine Editor Operators Operator ~ (unary) (...) == != > >= < <= & | Negative Brackets Numeric equality Not equal to Greater than Greater than or equal to Less than Less than or equal to AND OR Description 1 1 2 2 2 2 2 2 2 2 Priority ~in1 (1) in1==5 in1!=5 in1>in2 in1>=in2 in1<in2 in1<=in2 (in1==in2)&(in3>=4) (in1==in2)|(in1>in2) Example
A conditional statement consists of a source state, a condition that causes a transition to take place, and the destination state to which the state machine transitions. The source state and destination state values must be valid state names, which you can select from a drop down list in the wizard. The state machine description is saved in a <block name>.smf file when you close the state machine wizard. The syntax of each conditional statement is automatically checked on entry and the completed state machine is validated when you generate HDL to ensure that the state machine is functionally correct. f For more information including procedures for drawing a graphical state machine, refer to the About the State Machine Editor topic in the Quartus II Help. When you exit from the State Machine Editor, the generated HDL is compiled in the Quartus II software and the ports updated on the block in your Simulink model. Figure 102 shows an example of the default state machine that the State Machine Editor wizard creates and includes in a simple Simulink model.
103
For more information, refer to the Using the State Machine Editor Block chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook.
The default state machine has five inputs and five states. Each state is represented by an output. While the state machine is operating, an output is assigned a logic level 1 if its respective state is equal to the current state. All other outputs are assigned a logic level 0. The inputs and outputs are represented as integers in Simulink. In VHDL, the input and output are represented as standard logic vectors. 1 The State Machine Table block is not available on Linux and is deprecated on Windows. Use the State Machine Editor block in new designs.
104
The State Machine Builder dialog box allows you to specify the inputs, states, and conditional statements, which control the transitions between the states. Table 103 shows the controls available in the State Machine Builder dialog box.
Table 103. State Transition Table Block Controls Name Add Change Value Description Adds the specified input name, state name, or conditional statement to the table. Allows you to change the selected state name or conditional statement. Do not use this option in the Inputs tab. You cannot change an input name or state name that the design uses in a conditional statement. Deletes the selected input name, state name or conditional statement. You cannot delete an input or state that the design uses in a conditional statement. This option is available in the States tab and allows you to specify the reset state from a list of specified state names. You can change the reset state but you cannot delete or change the name of the reset state. Available in the Conditional Statements tab and allows you to change the transition priority when there is more than one condition leaving a state by moving the conditional statement up or down the list. Available in the Design Rule Check tab to validate your state machine table.
state name
Table 104 shows the operators that you can use to define a conditional expression.
Table 104. State Machine Table Operators Operator - (unary) (...) = != > >= < <= & | Negative Brackets Numeric equality Not equal to Greater than Greater than or equal to Less than Less than or equal to AND OR Description 1 1 2 2 2 2 2 2 2 2 Priority -1 (1) in1=5 in1!=5 in1>in2 in1>=in2 in1<in2 in1<=in2 (in1=in2)&(in3>=4) (in1=in2)|(in1>in2) Example
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A conditional statement consists of a current state, a condition that causes a transition to take place, and the next state to which the state machine transitions. The current state and next state values must be state names defined in the States tab, which you can select from drop down list in the dialog box. 1 To indicate in a conditional statement that a state machine always transitions from the current state to the next state, specify the conditional expression to be one. Figure 105 shows the dialog box that specifies a simple state transition table with the default inputs and states.
Figure 105. Simple State Transition Table
When VHDL generates, the expression strings for the port names are replaced by signals named <port name>_sig. Specify at least one transition for each state. Otherwise, the block does not generate legal VHDL. You may experience problems when using very large input signals (greater than 225).
At least two states must be defined At least two conditional statements must be defined All input port names must be unique All state names must be unique
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A single reset state must exist A reset input port must exist All current state and next state values must be valid All conditional statements must be syntactically correct
Figure 106 shows an example with the State Machine Table block as a FIFO controller.
Figure 106. Example With the State Machine Table Block
For more information, refer to the Using the State Machine Table Block chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook.
The Boards library supports DSP development platforms for the following prototyping boards:
Cyclone II DE2 Board Cyclone II EP2C35 DSP Board Cyclone II EP2C70 DSP Board Cyclone III EP3C25 Starter Board Cyclone III EP3C120 DSP Board Stratix EP1S25 DSP Board Stratix EP1S80 DSP Board Stratix II EP2S60 DSP Board Stratix II EP2S180 DSP Board Stratix II EP2S90GX PCI Express Board Stratix III EP3SL150 DSP Board
These development boards provide an economical solution for hardware and software verification that enables you to debug and verify both functionality and design timing. When combined with DSP intellectual property (IP) from Altera or from the Altera Megafunction Partners Program (AMPPSM), you can solve design problems that formerly required custom hardware and software solutions.
Board Configuration
When targeting a development board, your design must contain the corresponding board configuration block at the top hierarchical level. The configuration block properties allow you to specify from a list of available pins to use for the clock and global reset connections. It also displays details of the hardware device on the board. The other blocks available for each board provide connections to the controls on each board such as LEDs, push buttons, switches, 7-segment displays, connectors, analog-to-digital converters (ADC), and digital-to-analog converters (DAC). By using these blocks, you do not need to make pin assignments to connect the board components.
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For detailed information about the Cyclone II DE2 board, refer to Alteras Development and Education Board on the Altera website. Figure 112 shows the design example for the Cyclone II DE2 board.
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Table 112. Cyclone II EP2C35 DSP Board Blocks (Part 2 of 2) Block Display0 and Display1 Description Controls two simple user-definable seven-segment LED displays (U32, U33).
SW2SW5, Controls four user-definable push-button switches (SW2SW5, and user reset USER_RESETN push-button SW6). You can optionally specify the clock signal.
For information about setting up the board, refer to the DSP Development Kit, Cyclone II Getting Started User Guide. For information about supported hardware features, refer to the Cyclone II DSP Development Board Reference Manual. Figure 113 shows the design example for the Cyclone II EP2C35 DSP board.
Figure 113. Design Example for the Cyclone II EP2C35 DSP Board
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Table 113. Cyclone II EP2C70 DSP Board Blocks Block A2D_1 and A2D_2 D2A_1 and D2A_2 Dip Switch LED0LED7 PROTO and PROTO1 Display0 and Display1 SW2SW5, USER_RESETN Description Controls the 14-bit signed analog-to-digital converters. You can optionally specify the clock signal. Controls the 14-bit unsigned digital-to-analog converters. Controls the user-definable dual in-line package switch (S1). You can optionally specify the clock signal. Controls eight user-definable LEDs (D2D9). Santa Cruz connectors, which control the prototyping area I/O. You can optionally specify Input or Output node type, specify the input clock signal, and specify the pin location for each connector (J15, J22, J23). Controls two simple user-definable seven-segment LED displays (U32, U33). Controls four user-definable push-button switches (SW2SW5, and the user reset push-button SW6). You can optionally specify the clock signal.
For information about setting up the board, refer to the DSP Development Kit, Cyclone II Getting Started User Guide. For information about supported hardware features, refer to the Cyclone II DSP Development Board Reference Manual. Figure 114 shows the design example for the Cyclone II EP2C70 DSP board.
Figure 114. Design Example for the Cyclone II EP2C70 DSP Board
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For information about setting up the board, refer to the Cyclone III FPGA Starter Kit User Guide. For information about supported hardware features, refer to the Cyclone III FPGA Starter Board Reference Manual. Figure 115 shows the design example for the Cyclone III EP3C25 starter board.
Figure 115. Design Example for the Cyclone III EP3C25 Starter Board
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Table 115. Cyclone III EP3C120 DSP Board Blocks Block Display0 A2D_1_HSMC_A, A2D_1_HSMC_B, A2D_2_HSMC_A, A2D_2_HSMC_B D2A_1_HSMC_A, D2A_1_HSMC_B, D2A_2_HSMC_A, D2A_2_HSMC_B Dip Switch LED0LED7 PB0PB3, CPU_RESETN Controls the 14-bit unsigned digital-to-analog converters on the optional high speed mezzanine cards (HSMC). Description User defined 4-digit seven-segment LED display (U30). Controls 14-bit signed analog-to-digital converters on the optional high speed mezzanine cards (HSMC). You can optionally specify the clock signal.
Controls the user-definable dual in-line package switch (SW6). You can optionally specify the clock signal. Controls eight user-definable LEDs (D26D33). Controls four user-definable push-button switches (S1S4) and the CPU reset push-button (S5). You can optionally specify the clock signal.
For information about setting up the board, and supported hardware features, refer to the Cyclone III Development Board, Reference Manual. There are four design examples for the Cyclone III EP3C120 DSP board:
Test3C120Board_Leds.mdl: This design tests the LEDs and push-button switches on the main development board. Test3C120Board_QuadDisplay.mdl: This design tests the 7-segment display on the main development board. Test3C120Board_HSMA.mdl: This design tests the analog-to-digital and digital-to-analog converters on the daughtercard connected to HSMC port A. Test3C120Board_HSMB.mdl: This design tests the analog-to-digital and digital-to-analog converters on the daughtercard connected to HSMC port B.
Figure 116 shows the test design for the LEDs and push buttons.
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Figure 116. LED and Push-button Design Example for the Cyclone III EP3C120 DSP Board Blocks
Figure 117 shows the test design for the 7-segment display.
Figure 117. 7-Segment Display Design Example for the Cyclone III EP3C120 DSP Board Blocks
Figure 118 shows the test design for a high speed mezzanine card.
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Figure 118. HSMC Design Example for the Cyclone III EP3C120 DSP Board Blocks
Figure 118 shows the test design for the daughtercard connected to HSMC port A. The test design for the daughtercard connected to HSMC port B is very similar.
These assignments enable you to use the programmer pins as I/O. 2. Assign signals to the output enable pins for both channels of the analog-to-digital converters (A2D1_OEB and A2D2_OEB) and tie them to GND. 3. Assign signals to the SPI bus interface signals for the chip in static mode (ADA_SPI_CSB and ADA_SPI_CSB) and tie them to VCC. When these signal are pulled high, set the following signals: AD_SCLK:
High: Twos complement output (for FIR or similar) Low: Straight binary from near midrange
AD_SDIO:
High: Duty cycle stabilizer (DCS) enabled to lower jitter Low: DSC disabled
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4. Open a Quartus II project and configure a PLL to produce the required output clocks: a. Create a new block design file (for example, pll_clkout.bdf) and use the MegaWizard Plug-in Manager to add an ALTPLL megafunction. b. Configure the PLL with a 50MHz input clock (inclk0) and no other optional inputs. (Turn off areset.) Turn on Create locked output. Add two additional output clocks with 180 and 270 degrees phase shift from the input clock (c1 and c2) and clock multiplication factor of 2. Figure 119 shows the completed block design file. 1 Each output clock is negated in the block editor to produce a the signals pclk0p, pclk0n, pclk1p, and pclk1n.
c. Click Create HDL File for Current File on the File menu. 5. Import the PLL into the test design model: a. Add a Subsystem Builder block to your model. Double-click on the block and browse for the HDL file created in step 4c then click Build to create the subsystem. b. Open the subsystem (pll_clkout) and remove the default input port. Specify the clock name (such as clkin_50) in the block parameters for the HDL Entity block. This name should match the clock name in the .bdf file. c. Assign appropriate pin assignments for the four output clocks on the test design model (Figure 1110.)
Figure 1110. PLL Subsystem
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For information about setting up the board, refer to the DSP Development Kit, Stratix & Stratix Professional Edition Getting Started User Guide. For information about the supported hardware features, refer to the Stratix EP1S25 DSP Development Board Data Sheet. Figure 1111 shows the design example for the Stratix EP1S25 DSP board.
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Figure 1111. Design Example for the Stratix EP1S25 DSP Board
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Block A2D_1 and A2D_2 D2A_1 and D2A_2 DEBUGA and DEBUGB Dip Switch EVAL IO IN and EVAL IO OUT LED0 and LED1 PROTO
Description Controls the 12-bit signed analog-to-digital converters (U10, U30). You can optionally specify the clock signal. Controls the 14-bit unsigned digital-to-analog converters (U21, U23) Mictor connectors, which control debugging ports A and B. You can optionally specify Input or Output node type, specify the input clock signal, and specify the pin location for each port (J9, J10). Controls the user-definable dual in-line package switch (SW3). You can optionally specify the clock signal. Controls the evaluation input and outputs. You can optionally specify the clock signal for EVAL IO IN and specify the pin location for each input or output (JP7, JP19, JP22, JP20, JP21, JP24, JP8). Controls two user-definable LEDs (D6, D7). Expansion connector, which controls the prototyping area I/O. You can optionally specify Input or Output node type, specify the input clock signal, and specify the pin locations (J20, J21, J24). Controls the RS232 serial receive output and transmit input (J8). You can optionally specify the clock signal for RS232 TIN. Controls a dual user-definable seven-segment LED display (D4). Controls three user-definable push-button switches (SW0SW2). You can optionally specify the clock signal.
For information about setting up the board, refer to the DSP Development Kit, Stratix & Stratix Professional Edition Getting Started User Guide. For information about the supported hardware features, refer to the Stratix EP1S80 DSP Development Board Data Sheet. Figure 1112 shows the design example for the Stratix EP1S80 DSP board.
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Figure 1112. Design Example for the Stratix EP1S80 DSP Board
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Table 118. Stratix EP2S60 DSP Board Blocks (Part 2 of 2) Block PROTO2 Description Mictor connector, which controls the debugging port. You can optionally specify Input or Output node type, specify the input clock signal, and specify the pin location for each port (J20). External analog-to-digital converter interface connector. You can optionally specify Input or Output node type, specify the input clock signal, and specify the pin location for each port (J5, J6). Controls a dual user-definable seven-segment LED display (U12, U13). Controls four user-definable push-button switches (SW4SW7). You can optionally specify the clock signal.
PROTO3
For information about setting up the board, refer to the DSP Development Kit Getting Started User Guide. For information about the supported hardware features, refer to the Stratix II DSP Development Board Reference Manual. Figure 1113 shows a test design with the SignalTap II and EP2S60 DSP board blocks. The 7-segment display and LEDs on the board respond to user-controlled switches and the value of the incrementer.
Figure 1113. Design Example for the Stratix II EP2S60 DSP Board
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Description Controls the 12-bit signed analog-to-digital converters (U1, U2). You can optionally specify the clock signal. Controls the 14-bit unsigned digital-to-analog converters (U14, U15) Controls the board reset push-button switch (SW8). You can optionally specify the clock signal. Controls eight user-definable LEDs (D1D8). Santa Cruz connectors, which controls the prototyping area I/O. You can optionally specify Input or Output node type, specify the input clock signal, and specify the pin locations (J23 J25, J26J28). Mictor connector, which controls the debugging port. You can optionally specify Input or Output node type, specify the input clock signal, and specify the pin location for each port (J20). External analog-to-digital converter interface connector. You can optionally specify Input or Output node type, specify the input clock signal, and specify the pin location for each port (J5, J6). Controls a dual user-definable seven-segment LED display (U12, U13). Controls four user-definable push-button switches (SW4SW7). You can optionally specify the clock signal.
PROTO3
For information about setting up the board, refer to the DSP Development Kit Getting Started User Guide. For information about the supported hardware features, refer to the Stratix II EP2S180 DSP Development Board Reference Manual. Figure 1114 shows the design example for the Stratix II EP2S180 DSP board. The 7-segment display and LEDs on the board respond to user-controlled switches and the value of the incrementer.
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Figure 1114. Design Example for the Stratix II EP2S180 DSP Board
For information about setting up the board, refer to the PCI Express Development Kit, Stratix II GX Edition, Getting Started User Guide. For information about the supported hardware features, refer to the Stratix II GX PCI Express Development Board, Reference Manual. Figure 1115 shows the design example for the Stratix II EP2S90GX PCI Express board.
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Figure 1115. Design Example for the Stratix II EP2S90GX PCI Express Board
Controls the user-definable dual in-line package switch (SW5). You can optionally specify the clock signal.
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Table 1111. Stratix III EP3SL150 DSP Board Blocks (Part 2 of 2) Block LED0LED7 PB0PB3, CPU_RESETN Description Controls eight user-definable LEDs (D20D27). Controls four user-definable push-button switches (S2S5) and the CPU reset push-button (S6). You can optionally specify the clock signal.
For information about setting up the board and the supported hardware features, refer to the Stratix III Development Board, Reference Manual. Altera provides the following design examples for the Stratix III EP3SL150 DSP board:
Test3S150Board_Leds.mdl: tests the LEDs and push-button switches on the main development board. Test3S150Board_QuadDisplay.mdl: tests the 7-segment display on the main development board. Test3S150Board_HSMA.mdl: tests the analog-to-digital and digital-to-analog converters on the daughtercard connected to HSMC port A. Test3S150Board_HSMB.mdl: tests the analog-to-digital and digital-to-analog converters on the daughtercard connected to HSMC port B.
Figure 1116 shows the test design for the LEDs and push-button switches.
Figure 1116. LED and Push-button Design Example for the Stratix III EP3SL150 DSP Board Blocks
Figure 1117 shows the test design for the 7-segment display.
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Figure 1117. 7-Segment Display Design Example for the Stratix III EP3SL150 DSP Board Blocks
Figure 1118 shows the test design for a high speed mezzanine card.
Figure 1118. HSMC Design Example for the Stratix III EP3SL150 DSP Board Blocks
Figure 1118 shows the test design for the daughtercard connected to HSMC port A. The test design for the daughtercard connected to HSMC port B is very similar.
The MegaCore Functions library contains blocks that represent parameterizable IP that installs with the Quartus II software. DSP Builder supports the following Altera DSP IP:
CICimplements a cascaded integrator-comb) filter. f For more information, refer to the CIC MegaCore Function User Guide.
FFTimplements a high performance fast Fourier transform or inverse FFT processor. f For more information, refer to the FFT MegaCore Function User Guide.
FIRimplements a finite impulse response filter. f For more information, refer to the FIR Compiler User Guide.
NCOimplements a customized numerically controlled oscillator. f For more information, refer to the NCO MegaCore Function User Guide.
Reed-Solomonimplements a forward error correction encoder or decoder. f For more information, refer to the Reed-Solomon Compiler User Guide.
ViterbiImplements a high performance Viterbi decoder. f For more information, refer to the Viterbi Compiler User Guide.
When you double-click on a MegaCore function block, the MegaWizard Plug-In starts. The MegaWizard interface allows you to generate all the files required to integrate a parameterized MegaCore function variation into your DSP Builder model.
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DSP Builder provides a variety of tutorials and design examples, which you can learn from or use as a starting point for your own design. Altera supplies the following tutorials:
Amplitude Modulation HIL Frequency Sweep Switch Control Avalon-MM Interface Avalon-MM FIFO HDL Import Subsystem Builder Custom Library State Machine Table
CIC Interpolation (3 Stages x75) CIC Decimation (3 Stages x75) Convolution Interleaver Deinterleaver IIR Filter 32 Tap Serial FIR Filter MAC based 32 Tap FIR Filter Color Space Converter Farrow Based Resampler CORDIC, 20 bits Rotation Mode Imaging Edge Detection Quartus II Assignment Setting Example SignalTap II Filtering Lab SignalTap II Filtering Lab with DAC to ADC Loopback Cyclone II DE2 Board Cyclone II EP2C35 DSP Board Cyclone II EP2C70 DSP Board Cyclone III EP3C25 Starter Board Cyclone III EP3C120 DSP Board (LED/PB) Cyclone III EP3C120 DSP Board (7-Seg)
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Cyclone III EP3C120 DSP Board (HSMC A) Cyclone III EP3C120 DSP Board (HSMC B) Stratix EP1S25 DSP Board Stratix EP1S80 DSP Board Stratix II EP2S60 DSP Board Stratix II EP2S180 DSP Board Stratix II EP2S90GX PCI Express Board Stratix III EP3SL150 DSP Board (LED/PB) Stratix III EP3SL150 DSP Board (7-Seg) Stratix III EP3SL150 DSP Board (HSMC A) Stratix III EP3SL150 DSP Board (HSMC B)
The following additional design examples demonstrate how you can combine blocks from the advanced and standard blocksets in a single design:
To view the design examples, type demo at the MATLAB command prompt. The Demos tab opens in the Help window displaying a list of design examples. Select DSP Builder Blockset in the Help window to expand the list (Figure 131) and click on an entry to display an overview of each design.
Figure 131. DSP Builder Design Example Demos
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You can display the model corresponding to each design example by clicking Run this demo in the Help window. For example, if you click Run this demo for the HIL example, the model design window opens displaying the HIL frequency sweep model (Figure 132).
Figure 132. Hardware in the Loop Example Model
The <DSP Builder install path>\DesignExamples\Tutorials\ directory contains the getting started tutorials and design examples. f For more information, refer to the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook. You can also access simple example models for most of the blocks in the DSP Builder blockset that correspond to the examples in the block descriptions. Many of these example blocks include Simulink Scope blocks that display the output waveforms when you simulate the models. Access these examples in the directory <DSP Builder install path>\DesignExamples\Tutorials\UnitBlocks
Amplitude Modulation
The Getting Started Tutorial uses the amplitude modulation design example to demonstrate the DSP Builder design flow. The design example is a modulator that has a sine wave generator, a quadrature multiplier, and a delay element. The example model is singen.mdl. f For more information about this design, refer to the Getting Started Tutorial chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook.
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Switch Control
This design example shows how you can use blocks to control the switches on a DSP Development board and how to perform the SignalTap II analysis in DSP Builder. The example model is switch_control.mdl. f For more information about this design, refer to the SignalTap II Design Example in the Performing SignalTap II Logic Analysis chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook.
Avalon-MM Interface
This example consists of a 4-tap FIR filter with variable coefficients. The coefficients load with an Avalon-MM write slave while an off-chip source supplies the input data through an analog-to-digital converter. The design example sends filtered output data off-chip through a digital-to-analog converter. You can include the design as an SOPC Builder peripheral to the Avalon-MM bus. The example model is topavalon.mdl. f For more information about this design, refer to the Avalon-MM Interface Blocks in the Using the Interfaces Library chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook. The design example uses a Stratix II EP2S60 DSP development board but you can configure the design for other boards (for example, the Cyclone II EP2C35 development board). Altera provide alternative design examples in the CII and SII subdirectories under the <DSP Builder install path>\DesignExamples\Tutorials\SOPCBuilder\SOPCBlock\Finished Examples directory.
Avalon-MM FIFO
This design example consists of a Prewitt edge detector with one Avalon-MM Write FIFO buffer and one Avalon-MM Read FIFO buffer. DSP Bu idler uses an additional slave port as a control port. You can include the design as an SOPC Builder peripheral to the Avalon-MM bus. The example model is sopc_edge_detector.mdl. f For more information about this design, refer to Avalon-MM FIFO Buffer in the Using the Interfaces Library chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook.
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HDL Import
This design example is a template design that you can use to create a simple, implicit, black-box model with the HDL Import block. The example model is empty_MyFilter.mdl. f For more information about this design, refer to HDL Import in the Using Black-Box Designs for HDL Subsystems chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook.
Subsystem Builder
This design example allows you to create a simple, explicit, black-box model with the Subsystem Builder block. The example model is filter8tap.mdl. f For more information about this design, refer to Subsystem Builder in the Using Black-Box Designs for HDL Subsystems chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook.
Custom Library
This design example shows how you can use a custom library block to implement a parameterizable Simulink block. The example model is top.mdl. f For more information and procedures to create your own library block, refer to the Using Custom Library Blocks chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook.
Demonstration Designs
The <DSP Builder install path>\DesignExamples\Demos\ directory contains additional design examples.
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IIR Filter
This design example illustrates how to implement an order 2 IIR filter with a direct form two structure. The coefficients compute with the MATLAB function butter, which implements a Butterworth filter, with an order of two and a cutoff frequency of 0.4. This function creates floating-point coefficients, which are scaled in the design with the Gain block. The example model is topiir.mdl.
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plot(FpCoef,'o'); title('Fixed-point scaled coefficient value'); ImpulseData = zeros(1,1000); ImpulseData(1) = 100; h = conv(ImpulseData,FpCoef); fftplot(h); title('FIR Frequency response'); FirSamplingPeriod=1;
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This design example illustrates a Farrow resampler. You can simulate its performance in MATLAB, change it as required for your application, generate VHDL and synthesize the model to Altera devices. The design example has an input clock rate identical to the system clock. For applications where the input rate is much lower than the system clock, time sharing should be implemented to achieve a cost effective solution. The example model is FarrowResamp.mdl. f For more information about this design, click on the Doc symbol in the design model window.
Chapter 13: Design Examples SignalTap II Filtering Lab with DAC to ADC Loopback
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Chapter 13: Design Examples Cyclone III EP3C120 DSP Board (7-Seg)
For a description of this board, refer to Cyclone III EP3C120 DSP Board on page 116.
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Chapter 13: Design Examples Stratix III EP3SL150 DSP Board (HSMC B)
For a description of this board, refer to Stratix III EP3SL150 DSP Board on page 1118.
This appendix lists the blocks in each of the libraries in the Altera DSP Builder blockset.
AltLab
The AltLab library includes the following blocks:
BP (Bus Probe) Clock Clock_Derived Display Pipeline Depth HDL Entity HDL Import HDL Input HDL Output HIL (Hardware in the Loop) Quartus II Global Project Assignment Quartus II Pinout Assignments Resource Usage Signal Compiler SignalTap II Logic Analyzer SignalTap II Node Subsystem Builder TestBench VCD Sink
Arithmetic
The Arithmetic library includes the following blocks:
Barrel Shifter Bit Level Sum of Products Comparator Counter Differentiator Divider DSP
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Gain Increment Decrement Integrator Magnitude Multiplier Multiply Accumulate Multiply Add Parallel Adder Subtractor Pipelined Adder Product SOP Tap Square Root Sum of Products
Complex Type
The Complex Type library includes the following blocks:
Butterfly Complex AddSub Complex Conjugate Complex Constant Complex Delay Complex Multiplexer Complex Product Complex to Real-Imag Real-Imag to Complex
Binary to Seven Segments Bitwise Logical Bus Operator Case Statement Decoder Demultiplexer Flipflop If Statement LFSR Sequence
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Logical Bit Operator Logical Bus Operator Logical Reduce Operator Multiplexer Pattern Single Pulse
Interfaces
The Interfaces library includes the following blocks:
Avalon-MM Master Avalon-MM Slave Avalon-MM Read FIFO Avalon-MM Write FIFO Avalon-ST Packet Format Converter Avalon-ST Sink Avalon-ST Source
IO & Bus
The IO & Bus library includes the following blocks:
AltBus Binary Point Casting Bus Builder Bus Concatenation Bus Conversion Bus Splitter Constant Extract Bit Global Reset GND Input Non-synthesizable Input Non-synthesizable Output Output Round Saturate VCC
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Rate Change
The Rate Change library includes the following blocks:
Storage
The Storage library includes the following blocks:
Delay Down Sampling Dual-Clock FIFO Dual-Port RAM FIFO Buffer LUT (Look-Up Table) Memory Delay Parallel To Serial ROM Serial To Parallel Shift Taps Single-Port RAM True Dual-Port RAM Up Sampling
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Boards
The Boards library includes blocks that support the following development boards:
Cyclone II DE2 Board Cyclone II EP2C35 DSP Board Cyclone II EP2C70 DSP Board Cyclone III EP3C25 Starter Board Cyclone III EP3C120 DSP Board Stratix EP1S25 DSP Board Stratix EP1S80 DSP Board Stratix II EP2S60 DSP Board Stratix II EP2S180 DSP Board Stratix II EP2S90GX PCI Express Board Stratix III EP3SL150 DSP Board
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Index
Symbols
.hex file 122 .mdl file 13 .mdlxml file 121 .qar file 121 .qip file 122
Avalon-ST Packet Format Converter block 512 Avalon-ST Sink block 518 Avalon-ST Source block 520
B
Barrel Shifter block 22 Binary Point Casting block 64 Binary to Seven Segments block 42 Bit Level Sum of Products block 23 Bit width design rule 34 Bitwise Logical Bus Operator block 43 Black box 322 Explicit 81 HDL import Walkthrough 81 Implicit 81 Subsystem Builder Walkthrough 86 Using HDL import 81 Using SubSystem Builder 81 Boards library 111 Bus Builder block 65 Bus Concatenation block 67 Bus Conversion block 68 Bus Probe (BP) block 12 Bus Splitter block 69 Butterfly block 32
A
Advanced blockset interoperability 13 alt_dspbuilder_createComponentLibrary Create component library command 106 alt_dspbuilder_exportHDL command 123 alt_dspbuilder_refresh_hdlimport Update HDL command 325 alt_dspbuilder_refresh_megacore Update MegaCore command 42 alt_dspbuilder_refresh_user_library_blocks Update user libraries command 96 alt_dspbuilder_setup_megacore Setup MegaCore command 41 alt_dspbuilder_verifymodel Comparision command 322 AltBus block 62 Altera Quartus II software 12 Integration with MATLAB 13 AltLab library 11 Arithmetic library 21 asynchronous clear signal wiring 136 Automatic flow 319 Avalon-MM interface Features 12 FIFO walkthrough 716 Interface blocks walkthrough 78 Master block 74 Read FIFO 77 Slave block 72 SOPC Builder integration 71 Write FIFO 76 Avalon-MM Master block 53 Avalon-MM Read FIFO block 59 Avalon-MM Slave block 56 Avalon-MM Write FIFO block 511 Avalon-ST interface Features 12 Packet Format Converter 722 Packet formats 721 SOPC Builder integration 720
C
Case Statement block 45 Clock Setting a derived clock 22 Setting the base clock 22 Clock block 12 Clock_Derived block 13 Clocking 38 Assignment 311 Categories 311 Clock enable signal 38 Configuration parameters 23 Global reset 317 HDL simulation models 316 Multiple clock domains 39 Sampling period 38 Simulink simulation model 316 Single clock domain 38 Timing relationships 318 Using a PLL block 314
Index2
Using advanced PLL features 315 Using Clock and Clock_Derived blocks 310 Comments Adding to a block 322 Comparator block 25 Complex AddSub block 34 Complex Conjugate block 36 Complex Constant block 38 Complex Delay block 39 Complex Multiplexer block 310 Complex Product block 311 Complex to Real-Imag block 313 Complex Type library 31 Constant block 610 Controlling synthesis and compilation 319 Counter block 26 Custom library Adding to the library browser 95 Creating a library model file 91 Walkthrough 91 Cyclone II DE2 DSP board 112 Cyclone II EP2C35 DSP board 113 Cyclone II EP2C70 DSP board 114 Cyclone III EP3C120 DSP board 116 Cyclone III EP3C25 DSP board 116
Creating a new board description 101 predefined components 101 Supported boards 101 Troubleshooting 135 Dual-Clock FIFO block 94 Dual-Port RAM block 97
E
Error message Data type mismatch 136 Design includes pre-v7.1 blocks 136 Loop while propagating bit widths 134 Output connected to Altera block 135 Unexpected end of file 1310 When generating blocks 137 Example designs 32 tap FIR filter 136 Amplitude modulation 133 Avalon-MM Blocks 134 Avalon-MM FIFO 134 CIC decimation 136 CIC interpolation 136 Color space converter 137 Combined blocksets 1312 Convolution interleaver deinterleaver 136 CORDIC, 20 bits rotation mode 138 Custom Library 135 Custom library block 91 Cyclone II DE2 board 139 Cyclone II EP2C35 board 139 Cyclone II EP2C70 board 139 Cyclone III EP3C120 board (7-seg display)
1310
D
Data width propagation 34 Decoder block 47 Delay block 92 Demultiplexer block 48 Design flow 21 Control using Signal Compiler 319 Overview 21 Using a State Machine Editor block 117 Using a State Machine Table Block 112 Using Hardware in the loop 51 Using MegaCore functions 42 Design rules 31 Bit width 34 Frequency 38 Signal Compiler 319 Device family support Standard blockset 11 Differentiator block 28 Digital signal processing (DSP) 13 Display Pipeline Depth block 14 Divider block 29 Down Sampling block 93 DSP block 210 DSP development board Board description file 104 Component description file 102 Creating a board library 106
Cyclone III EP3C120 board (HSMC A) 1310 Cyclone III EP3C120 board (HSMC B) 1310 Cyclone III EP3C120 board (LED/PB) 139 Cyclone III EP3C25 starter board 139 Farrow based resampler 137 Getting started tutorial 24 Hardware in the loop 53 HDL Import 135 HDL import 81 HIL frequency sweep 133 IIR filter 136 Imaging edge detection 138 MAC based 32 tap FIR filter 137 Quartus II assignment setting 138 SignalTap II 62 SignalTap II filtering lab 138 SignalTap II filtering lab with loopback 139 SOPC Builder peripheral 78 State machine example 111 State Machine Table 135 Stratix EP1S25 board 1310
Index3
Stratix EP1S80 board 1310 Stratix II EP2S180 board 1311 Stratix II EP2S60 board 1311 Stratix II EP2S90GX PCI Express board 1311 Stratix III EP3SL150 board (7-seg display) 1311 Stratix III EP3SL150 board (HSMC A) 1311 Stratix III EP3SL150 board (HSMC B) 1312 Stratix III EP3SL150 board (LED/PB) 1311 Subsystem Builder 135 Switch Control 134 External RAM block 81 Extract Bit block 612
Input block 614 Integrator block 219 Interfaces library 51 IO & Bus library 61
L
LFSR Sequence block 414 Library AltLab 11 Arithmetic 21 Boards 111 Complex Type 31 Gate & Control 41 Interfaces 51 IO & Bus 61 MegaCore Functions 121 Rate Change 71 Simulation 81 State Machine Functions 101 Storage 91 Logical Bit Operator block 416 Logical Bus Operator block 417 Logical Reduce Operator block 419 LUT (Look-Up Table) block 911
F
FIFO block 910 Flipflop block 410 Frequency Design Rules 38
G
Gain block 215 Gate & Control library 41 Generating a Testbench 217 Global Reset (or SCLR) block 613 GND block 613
M H
Hardware in the loop (HIL) 12 Burst & frame modes 56 Design flow 51 Overview 51 Requirements 52 Troubleshooting 510 Walkthrough 53 HDL Simulation model 316 HDL Entity block 14 HDL export 122 HDL import Black box 81 Features 12 Updating 324 Walkthrough 81 HDL Import block 15 HDL Input block 17 HDL Output block 18 Hierarchical design 320 HIL (Hardware in the Loop) block 19 How to Contact Altera Info1 Magnitude block 220 Manual flow 319 MATLAB 12 Integration with 13 Opening the Simulink library browser 24 Using a base or masked subsystem variable 32 Using a MATLAB array to initilize a block 322 MegaCore function 13 Design flow 42 Design issues 413 Device family 414 Generating a variation 43 Installing 41 Instantiating 42 OpenCore Plus evaluation 41 Optimizing 43 Parameterizing 43 Signal Compiler 414 Simulating 43 Simulating in the tutorial design 48 Updating variations 42 Version numbers 41 Walkthrough 43 MegaCore Functions library 121 Memory block types 11 Memory Delay block 913 Model
I
If Statement block 411 Increment Decrement block 217
Index4
Creating 24 Performing RTL simulation 217 Simulating in Simulink 215 ModelSim Comparison with Simulink 322 Simulation fllow 319 Using a Tcl file to add commands 327 Multiple Port External RAM block 83 Multiplexer block 420 Multiplier block 221 Multiply Accumulate block 223 Multiply Add block 225 Multi-Rate DFF block 71
R
Rate Change library 71 Real-Imag to Complex block 314 Release information 11 Reset Asynchronous 317 global 317 Resource usage Analyzing 325 Resource Usage block 112 ROM block 916 Round block 618
N
Naming conventions 31 Nios II Support 12 Using the Nios II IDE 715 Non-synthesizable Input block 615 Non-synthesizable Output block 616 Notation Binary point location 33 Fixed-point 32
S
Saturate block 620 Serial To Parallel block 918 Shift Taps block 920 Signal Compiler 319 Adding to a model 216 Enabling SignalTap II options 66 License 131 Synthesis and compilation flows 319 Signal Compiler block 113 Signal data type display format 324 SignalTap II Design flow 61 Walkthrough 62 SignalTap II logic analyzer 61 Features 12 Performing logic analysis 61 Signal Compiler options 66 Trigger conditions 67 SignalTap II Logic Analyzer block 114 SignalTap II Node block 115 Simulation Setting the Simulink solver 23 Using ModelSim 217 Using Simulink 215 Simulation flow 319 Simulation library 81 Simulation model HDL 316 Simulink Comparison with ModelSim 322 Integration with 13 Solver 316 Single Pulse block 423 Single-Port RAM block 921 Solver Setting simulation parameters 23
O
Output block 617
P
Packet Format Converter Avalon-ST 722 Parallel Adder Subtractor 227 Parallel To Serial block 914 Pattern block 422 Pipeline depth display 324 Pipelined Adder block 229 PLL block 73 PLL clocks device support 314 Port data type display format 324 Product block 231
Q
Quartus II assignments Adding to block entity names 327 Quartus II constraints Adding to a model 323 Quartus II project Adding a DSP Builder design 220 Integration of multiple models 125 Quartus II Project Global Assignment block 111
Index5
SOP Tap block 233 SOPC Builder Interfaces library 71 Support 12 SOPC builder Instantiating your design 712 Square Root block 235 State machine Implementing 111 State Machine Editor Walkthrough 117 State Machine Editor block 101 State Machine Functions library 101 State Machine table Walkthrough 112 State Machine Table block 103 Storage library 91 Stratix EP1S25 DSP board 1111 Stratix EP1S80 DSP board 1113 Stratix II EP2S180 DSP board 1115 Stratix II EP2S60 DSP board 1114 Stratix II EP2S90GX PCI Express board 1117 Stratix III EP3SL150 DSP board 1118 Subsystem Builder Walkthrough 86 Subsystem Builder block 115 Sum of Products block 236 Sum of Products Tap block 233
Adding to a model 217 TestBench block 117 True Dual-Port RAM block 924 Tsamp block 74 Tutorial Getting started 24 Typographic Conventions Info1
U
Up Sampling block 928
V
VCC block 621 VCD Sink block 118
W
Walkthrough Avalon-MM FIFO 716 Avalon-MM interface blocks 78 Black box HDL import 81 Subsystem Builder 86 Custom library 91 Hardware in the loop 53 MegaCore function 43 SignalTap II 62 State Machine Editor 117 State Machine Table 112 Warning message I/O blocks conflict with clock or aclr ports 136
T
TestBench
Index6
Additional Information
Typographic Conventions
The following table shows the typographic conventions that this document uses.
Visual Cue Bold Type with Initial Capital Letters bold type Meaning Indicates command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box. For GUI elements, capitalization matches the GUI. Indicates directory names, project names, disk drive names, file names, file name extensions, dialog box options, software utility names, and other GUI labels. For example, \qdesigns directory, d: drive, and chiptrip.gdf file. Indicates document titles. For example, AN 519: Stratix IV Design Guidelines. Indicates variables. For example, n + 1. Variable names are enclosed in angle brackets (< >). For example, <file name> and <project name>.pof file. Initial Capital Letters Subheading Title
Courier type
Indicates keyboard keys and menu names. For example, Delete key and the Options menu. Quotation marks indicate references to sections within a document and titles of Quartus II Help topics. For example, Typographic Conventions. Indicates signal, port, register, bit, block, and primitive names. For example, data1, tdi, and input. Active-low signals are denoted by suffix n. For example, resetn. Indicates command line commands and anything that must be typed exactly as it appears. For example, c:\qdesigns\tutorial\chiptrip.gdf. Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword SUBDESIGN), and logic function names (for example, TRI).
Info2
Visual Cue 1., 2., 3., and a., b., c., and so on.
Meaning Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets indicate a list of items when the sequence of the items is not important. The hand points to information that requires special attention. A caution calls attention to a condition or possible situation that can damage or destroy the product or your work. A warning calls attention to a condition or possible situation that can cause you injury. The angled arrow instructs you to press Enter. The feet direct you to more information about a particular topic.
1 c w r f
Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Contents
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Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Copying a Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Running a Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 ModelIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
General Primitive Library Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Essential Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 Testbench Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 Top-Level Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 Primitive Subsystem Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 Verification Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 Using Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 Vector Utils Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 Other Vector BlocksSimulink Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 Implementing Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 Flow Control Using Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 Forward Flow Control Using Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 Flow Control Using FIFO Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 Flow Control and Back Pressure Using FIFO Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 Safe Operation of FIFO Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 Flow Control using Simple Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 Flow Control Using the ForLoop Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 Using Loop or ForLoop Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 Building System Components with Avalon-ST Interface Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 Extending the Interface Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 Adding More Ports to the Avalon-ST Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 Adding Custom Text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 Using ModelPrim Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 Interfaces as Subsystem Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 Interfaces as Scheduling Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 ModelPrim Subsystem Designs to Avoid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 Common Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 ModelPrim Blocks Outside Primitive Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 Converting Blocks and Specifying Output Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 Floating-Point Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 Converting Between Floating- and Fixed-Point Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 Interacting with Other Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 Floating Point Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 Floating-Point Type Propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 Special Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 Floating Point Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 Generated Testbenches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
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The DDC Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Signals Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Source Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Sink Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Tool Interface Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 DDCChip Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Primary Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Merge Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 NCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Mixer Scale Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 DecimatingCIC and Scale Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Decimating FIR Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 Simulating the Design in Simulink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 Exploring the Generated Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 Compiling with the Quartus II Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
Chapter 7. Folding
Using Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Folded Subsystem without Time Division Demultiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Folded Subsystem with TDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Effects of Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Effects on Manual Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Effects on Combinational Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Chapter 1. Introduction
Base Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 FFT Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Filter Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Waveform Synthesis Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ModelBus Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
vii
ModelPrim Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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ix
Interpolating FIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Typical Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Updated Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 Single-Rate FIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 Typical Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 Updated Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
December 2010
1x
xi
December 2010
1xii
Compare Greater Than (CmpGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 Compare Less Than (CmpLT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 Compare Not Equal (CmpNE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 Constant (Const) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 Convert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722 CORDIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727 Count Leading Zeros (CLZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 Dual Memory (DualMem) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730 Demultiplexer (Demux) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733 ForLoop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734 Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735 General Purpose Input (GPIn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 General Purpose Output (GPOut) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 Left Shift (LShift) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
xiii
Look-Up Table (Lut) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740 Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 Maximum Value (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 Minimum Value (Min) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 Multiply (Mult) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 Multiplexer (Mux) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 NAND Gate (Nand) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 NOR Gate (Nor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 NOT Gate (Not) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 OR Gate (Or) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 Sample Delay (SampleDelay) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
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Subtract (Sub) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754 Synthesis Information (SynthesisInfo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 Updated Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756 XNOR Gate (Xnor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757 XOR Gate (Xor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
Additional Information
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info1
The following table shows the revision dates for the sections in this volume.
Section DSP Builder Advanced Blockset User Guide DSP Builder Advanced Blockset Libraries Version 2.0 2.0 Date December 2010 December 2010 Part Number HB_DSPA_ADV_UG-2.0 HB_DSPA_ADV_LIB-2.0
Altera Corporation
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Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Revision History
The following table shows the revision history for this section.
Date December 2010 Version 2.0
Rectangular nested loop Triangular nested loop Sequential loops Partial loops Folded color space converter Folded single-stage IIR filter Folded 3-stage IIR filter Folded primitive FIR filter Hybrid direct form and transpose form FIR filter Digital predistortion forward path Run-time configurable decimating and interpolating half-rate FIR filter Matrix initialization of vector memories Matrix initialization of LUT Vector initialization of sample delay
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The DSP Builder advanced blockset adds specialized Simulink libraries to the MATLAB design environment that allow you to implement DSP designs quickly and easily. The advanced blockset is based on a high-level synthesis technology that optimizes the high-level, untimed netlist into low level, pipelined hardware for your target Altera FPGA device and clock rate. DSP Builder writes out the hardware as plain text VHDL, with scripts that integrate with the Quartus II software and the ModelSim simulator. The combination of these features allows you to create a design without needing detailed device knowledge, and generate a high quality implementation that runs on a variety of FPGA families with different hardware architectures. By specifying your desired clock frequency, you can solve timing closure issues by generating register transfer level (RTL) code that pipelines to meet your goal. Filters in the blockset automatically use a high-clock rate to increase folding, and reduce hardware size. 1 The DSP Builder advanced blockset uses Simulink fixed-point types for all operations. You can use the advanced blockset entirely independently of the DSP Builder standard blockset, or you can embed its blocks in top-level DSP Builder designs that use the standard blockset. f For information about interoperability with the DSP Builder standard blockset, refer to Chapter 8, DSP Builder Standard and Advanced Blockset Interoperability.
Libraries
The advanced blockset comprises the following Simulink libraries:
Base blocks FFT blockset Filters (ModelIP) ModelBus ModelPrim ModelVectorPrim Waveform synthesis (ModelIP)
For more information about the advanced blockset libraries, refer to the DSP Builder Advanced Blockset Libraries section in volume 3 of the DSP Builder Handbook.
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Base Blocks
The top-level design of a DSP Builder advanced blockset design is a testbench and must include Control and Signals blocks. A design may include any number of subsystems that can combine blocks from the DSP Builder advanced blockset with blocks from the MATLAB Simulink libraries. The functional subsystem containing a Device block marks the top-level of the FPGA device and specifies the target device that the generated hardware uses. Altera provides other blocks to control and view the signals in your design, and to automatically load your design into the ModelSim simulator or the Quartus II software.
Control Block
The Control block traverses your design, synthesizes the individual primitive or ModelIP blocks into RTL, and maintains an internal data flow representation of your design. Simulink simulation uses the internal representation of your design example and to write out the RTL and scripts for other tools. A single Control block must be present in your top-level model. 1 DSP Builder applies globally the options in the Control block to your design. Hardware Generation Options in the Control block specify whether hardware generates for your design example and the location of the generated RTL. You can also create automatic RTL testbenches for each subsystem in your design example and specify the depth of signals that DSP Builder includes when your design example simulates in ModelSim. Memory-Mapped Bus Interface You can specify the address and data bus widths that the memory-mapped bus interface use and specify whether DSP Builder stores the high-order byte of the address in memory at the lowest address and the low-order byte at the highest address (big endian), or the high-order byte at the highest address and the low-order byte at the lowest address (little endian). Memory and Multiplier Trade-Off Options When your design synthesizes to logic, DSP Builder creates delay blocks, whether explicitly from primitive delays, or in the ModelIP blocks. DSP Builder tries to balance the implementation between logic elements (LEs) and block memories (M512, M4K, M9K, or M144K). The trade-off depends on the target FPGA family, but as a guideline the trade-off is set to minimize the absolute silicon area the design uses. For example, if a block of RAM occupies the silicon area of two logic array blocks (LABs), the design implements delay that requires more than 20 LEs (two LABs) as a block of RAM. There may be cases when you want to influence this trade-off.
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Table 11describes the memory and multiplier threshold trade-offs and provides some usage examples.
Table 11. Memory and Multiplier Trade-Offs CDelay RAM Block Threshold Description Default (1) Usage Trade-off between simple delay LEs and small ROM blocks. If any delay's size is such that the number of LEs is greater than this parameter, the design implements the delay as a block RAM. 20 bits. To make more delays use block RAM, enter a lower number. For example a value in the range 20 to 30. To use fewer block memories, enter a larger number. For example 100. To never use block memory for simple delays, set to a very large number, such as 10,000. Implement delays of length less than 3 cycles in LEs because of the block RAM behavior. This threshold only applies to implementing simple delays in memory blocks or LEs. You cannot push back dual memories into LEs. DSP Builder builds some ModelIP blocks with dual memories, for example dual and multirate filters; these blocks always use some memory blocks, regardless of the value of this threshold. CDualMem Dist RAM Threshold Description Trade-off between small and medium RAM blocks. This threshold is similar to the CDelay RAM Block Threshold except that it applies only to the dual-port memories in the ModelPrim library. Implement any dual-port memory in a block memory, rather than LEs, but for some device families there may be different sizes of block memory available. The threshold value determines which medium size RAM memory blocks to use instead of small memory RAM blocks. For example, the threshold that determines whether to use M9K blocks rather than MLAB blocks on Stratix III and Stratix IV devices. Default (1) Usage 1,280 bits. Use Stratix III devices with the default threshold value (-1), to implement dual memories greater than 1,280 bits as M9Ks and implement dual memories less than or equal to 1,280 bits as MLABs. If you change this threshold to a lower value such as 200, implement dual memories greater than 200 bits as M9Ks and implement dual memories less than or equal to 200 bits as MLABs. For families with only one type of memory block (for example Cyclone II with only M4K, or Cyclone III with only M9K) this threshold has no effect.
Notes
Trade-off between medium and large RAM blocks. For larger delays, implement memory in medium block RAM (M4K, M9K) or use larger M-RAM blocks (M512K, M144K). 1,000,000 bits. If the number of bits in a memory or delay is greater than this threshold, DSP Builder uses M-RAM for the implementation. If you set a large value such as the default of 1,000,000 bits, M-RAM blocks are never used.
Hard Multiplier Threshold Description Trade-off between hard and soft multipliers. For devices that support hard multipliers or DSP blocks, use these resources instead of a soft multiplier made from LEs. For example, a 2-bit 10-bit multiplier consumes very few LEs. The hard multiplier threshold value corresponds to the number of LEs that save a multiplier. If the hard multiplier threshold value is 100, you are allowing 100 LEs. Therefore, an 1818 multiplier (that requires approximately 182 = 350 LEs) does not transfer to LEs because it requires more LEs than the threshold value. However, DSP Builder implements a 164 multiplier that requires approximately 64 LEs as a soft multiplier with this setting.
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Table 11. Memory and Multiplier Trade-Offs Default (1) Usage The default (1) means always use hard multipliers. With this value, DSP Builder implements 2418 as two 1818 multipliers. Set a value of approximately 300 to keep 1818 multipliers hard, but transform smaller multipliers to LEs. DSP Builder implements A 2418 multiplier as 618 + 1818, so this setting builds the hybrid multipliers that are required. Set a value of approximately 1000 to implement the multipliers entirely as LEs. Essentially you are allowing a high number (1000) of LEs to save an 1818 multiplier. Set a values of approximately 10 to implement a 2416 multiplier as a 3636 multiplier. With this value, you are not even allowing the adder to combine the two multipliers, therefore the system has to burn a 3636 multiplier in a single DSP block. Notes DSP Builder converts multipliers with a single constant input into balanced adder trees. This occurs automatically where the depth of the tree is not greater than 2. If the depth is greater than 2, DSP Builder compares the hard multiplier threshold with the estimated size of the adder tree, which is generally much lower than the size of a full soft multiplier. If DSP Builder combines two non-constant multipliers followed by an adder into a single DSP block, DSP Builder does not convert the multiplier into LEs, even if there is a large threshold.
Signals Block
Each design example must have a Signals block, which you should place at the top level of your model. The Signals block specifies the details for the clocks and resets that drive the generated logic. The DSP Builder advanced blockset uses a single system clock to drive the main datapath logic, and, optionally, a second bus clock to provide an external processor interface. The rationale for this is that it is most efficient to drive the logic at as high a clock rate as possible. The standard DSP Builder blockset is better for managing multiple clock domains for example, when interfacing to external logic. The Signals block provides a mechanism to name the clock, reset, and memory bus signals that the RTL uses, and also provides information about the clock rate. This information is important for the following reasons:
To calculate the ratio of sample rate to clock rate determine the amount of folding (or time-division multiplexing) in the ModelIP filters. To determine the pipelining required at each stage of logic. For example, the design modifies the amount of pipelining that hard multipliers uses, and pipelines long adders into smaller adders based on the absolute clock speed in relation to the FPGA family and speed-grade you specify in the device block.
Cyclone device families do not support a separate bus clock due to the limited multiple clock support in block RAMs on those devices. For this reason, you must de-activate the separate bus clock option for the Signals block when using Cyclone device families.
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Device Block
The Device block marks a particular Simulink subsystem as the top-level of an FPGA device and allows you to specify the target device and speed grade for the device. The DSP Builder advanced blockset supports the following target Altera device families: Stratix, Stratix GX, Stratix II, Stratix II GX, Stratix III, Stratix IV, Cyclone II, Cyclone III, and Arria II GX. All blocks in subsystems below this level of hierarchy, become part of the RTL design. All blocks above this level of hierarchy become part of the testbench.
FFT Blockset
The FFT Blockset library contains common blocks that support fast Fourier transform (FFT) design. It also includes several blocks that support the Radix-22 algorithm. f For information about the Radix-22 algorithm, refer to A New Approach to Pipeline FFT Processor Shousheng He & Mats Torkleson, Department of Applied Electronics, Lund University, Sweden.
ModelPrim Blocks
The ModelPrim library allows you to create fast efficient designs captured in the behavioral domain rather than the implementation domain by combining primitive functions. For example, you can use a Delay block and let DSP Builder decide how to implement that delay. You do not need to understand the details of the underlying FPGA architecture, as the primitive blocks automatically map into efficient FPGA constructs. Most arithmetic and memory ModelPrim blocks allow you to use Simulink 1-D vector (array) and complex types. A design that uses a vector input of width N is the same as connecting N copies of the block with a single scalar connection to each. Signals that pass through a single ChannelIn, ChannelOut, GPIn, or GPOut block line up correctly in time at their boundaries. However, DSP Builder does not specify the timing relationship between different sets of inputs and outputs, and does not guarantee any fixed relationship if you change clock frequencies or devices. You should use the protocol described in Protocol for Connecting IP on page 110 to decode outputs, rather than exact clock counting where possible. You can design and debug quickly with zero-latency blocks, without tracking block latencies around your design. DSP Builder displays and calculates the additional latency that your design requires to meet timing constraints as a parameter on the ChannelOut block. Parameters on the ChannelIn and ChannelOut blocks allow the control of automated folding for the primitive subsystems. Folding allows DSP Builder to implement the design with fewer expensive resources, such as multipliers, at the expense of a little more logic by sharing them when the sample rate is below the clock rate. f For more information on folding, refer to Folding on page 71.
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Inherit via internal rule: the number of integer and fractional bits is equal to the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Inherit via internal rule with word growth: the number of fractional bits is equal to the maximum of the number of fractional bits in the input data types. The number of integer bits is the maximum of the number of integer bits in the input data types plus one. This additional word growth allows for subtracting the most negative number from 0, which exceeds the maximum positive number that DSP Builder can store in the number of bits of the input. Specify via dialog: additional fields that allow you to set the output type of the block explicitly. Boolean: the output type is Boolean.
In general, you can set the output type of a primitive block to Inherit via internal rule, or Inherit via internal rule with word growth. The type propagates through your design naturally, with blocks potentially growing the word length where necessary. If there are loops in your design, use the dialog box to specify the output type for at least one block in the loop. f For information about the options that DSP Builder supports by each block, refer to the ModelPrim Library chapter in the DSP Builder Advanced Blockset Libraries section in volume 3 of the DSP Builder Handbook. Using the Specify via Dialog Option Specifying the output type with the dialog box is a casting operation. This operation does not preserve the numerical value, just the underlying bits and never adds hardware to a blockjust changes the interpretation of the output bits. For example, a Mult block with both input data types specified as sfix16_En15 naturally has an output type of sfix32_En30. If you specify the output data type as sfix32_En28, the output numerical value is effectively multiplied by four, and a 1*1 input gives an output value of 4. If you specify output data type of sfix32_En31, the output numerical value is effectively divided by two and a 1*1 input gives an output value of 0.5. If you want to change the data type format in a way that preserves the numerical value, use a Convert block, which adds the corresponding hardware. Adding a Convert block directly after a primitive block allows you to specify the data type in a way that preserves the numerical value. For example, a Mult block followed by a Convert block, with input values 1*1 always gives output value 1.
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SynthesisInfo Block
The ModelPrim library includes a SynthesisInfo block that sets the synthesis mode and labels a subsystem described by primitive blocks as the top-level of a synthesizable subsystem tree. DSP Builder flattens and synthesizes the subsystem, and all those below as a unit. If no SynthesisInfo block is present, the style defaults to WYSIWYG and DSP Builder issues error messages if there is insufficient delay. The inputs and outputs to this subsystem become the primary inputs and outputs of the RTL entity that creates. After you run a Simulink simulation, the online Help page for the SynthesisInfo block updates to show the latency, port interface, and estimated resource utilization for the current primitive subsystem. 1 The SynthesisInfo block can be at the same level as the Device block (if the synthesizable subsystem is the same as the generated hardware subsystem). However, it is often convenient to create a separate subsystem level that contains the Device block. Refer to the design examples for some examples of design hierarchy. Two styles of operation exist during synthesis: WYSIWYG and Scheduled. WYSIWYG Style WYSIWYG is the default style of operation. Use when you want full control over the pipelining in a system. A Delay primitive must follow every primitive that requires registering (such as an adder or multiplier). The preceding block absorbs the delay primitive to satisfy its delay requirements. DSP Builder issues error messages if there is insufficient delay. 1 The primitive logic blocks (And, Or, Nand, Not, Nor, Xnor, Xor) and the Simulink Mux and Demux blocks do not require a register. Scheduled Style The Scheduled style of operation uses a pipelining and delay distribution algorithm that creates fast hardware implementations from an easily described untimed block diagram. This style takes full advantage of the automatic pipelining capability. 1 Altera recommends the Scheduled style of operation. The algorithm performs the following operations: 1. Reads in and flattens your design example for any subsystem that contains a SynthesisInfo block. 2. Builds an internal graph to represent the logic. 3. Based on the absolute clock frequency requested, adds enough pipeline stages to meet that clock frequency. For example, you may pipeline long adders into several shorter adders. This additional pipelining helps reach high clock frequencies. Consider the following two main cases:
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The simpler case is feed-forward. When no loops exist, feed-forward datapaths are balanced to ensure that all the input data reaches each functional unit in the same cycle. After analysis, DSP Builder inserts delays on all the non-critical paths to balance out the delays on the critical path. The case with loops is more complex. DSP Builder creates all loops with a delay to avoid combinational loops that Simulink cannot analyze. Typically, one or more lumped delays exist. Preserve the delay around the loop for correct operation, therefore the functional units borrow delays from the lumped delay that need them. Because loops can intersect or be nested with each other, observe a set of simultaneous constraints. The synthesis engine solves these constraints, distributes delay around the functional units as required, and leaves any residual delay as lumped delay elements. When there is insufficient delay to distribute, an error generates. The following list gives the delay requirements for some typical blocks:
Boolean logic operations: 0 delay Adders: 1 delay, but potentially more at higher clock rates Two input multiplexers: 1 delay with potentially more for large number of inputs and at high clock rates Multipliers: 3 cycles or 4 at higher clock rates
When you select the Scheduled style, you can optionally specify a latency constraint limit that can be a workspace variable or expression but must evaluate to a positive integer.
ModelBus Blocks
The ModelBus library provides memories and registers that you can access in your DSP datapath with an external interface. You can use these blocks to configure coefficients or run-time parameters and to read calculated values. This library also includes blocks that you can use to simulate the bus interface in the Simulink environment.
ModelIP Blocks
The ModelIP libraries include parameterizable multichannel filters and waveform synthesis blocks that allow you to quickly create designs for digital front-end applications. Altera provides the ModelIP blocks in the following libraries:
The Filters library contains several decimating and interpolating cascaded integrator-comb (CIC), and finite impulse response (FIR) filters including single-rate, multi-rate, and fractional-rate FIR filters. The Waveform Synthesis library contains a numerically controlled oscillator (NCO), complex mixers, and real mixers.
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After you run a Simulink simulation, DSP Builder updates the online Help page for each ModelIP block to show specific design documentation describing its implementation in your design. This information typically includes the latency, port interface, and resource utilization. For the blocks in the Filters library, the updated Help page also includes details of the parameterization, input and output data formats, and memory interface. To display the latency that a ModelIP block adds, add the %<latency> parameter as annotation on the block. After you run a simulation, the added latency shows as a text annotation below the block. 1 You cannot use latency constraints with folding.
ModelIP blocks designs, such as the FIR and CIC filters. These blocks are 100% cycle accurate and the Simulink behavior represents exactly the RTL behavior. You can turn on display of the latency added by each block. Synthesized primitive block designs from the ModelPrim library. These blocks are 100% cycle accurate at their boundaries, therefore interfacing to other blocks is straightforward. The primitive blocks are untimed circuits, so are not cycle accurate. In fact, there is not even a one-to-one mapping between the blocks in the Simulink model and the blocks implement your design in RTL. It is this decoupling of design intent from design implementation that gives the productivity benefits. The boundary between the untimed block and the outsized, cycle accurate block is the ChannelOut block. This block models the additional delay that the RTL introduces, so that data going in to the ChannelOut block delays internally, before DSP Builder presents it externally. The latency of the block displays on the ChannelOut mask.
You can also use primitive blocks outside of synthesizable subsystems, to create glue logic around other subsystems. The Boolean logic and delay blocks are cycle accurate, but other primitive blocks are not.
To read the added latency value for a ModelIP block (or for the ChannelOut ModelIP block), select the block and type the following command:
get_param(gcb, 'latency')
You can also use this command in an M-script. For example when you want to use the returned latency value to balance delays with external circuitry. 1 If you use an M-script to get this parameter and set latency elsewhere in your design, by the time it updates and sets on the ModelIP block, it is too late to initialize the delays elsewhere. You must run your design twice after any changes to make sure that you have the correct latency. If you are scripting the whole flow, your must run once with end time 0, and then run again immediately with the desired simulation end time.
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For more information about latency, refer to Latency Management on page 61.
The design example uses just the three data, valid, and channel signals to connect the FilterSystem and ChanView block.
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In the FIR filters, the valid signal is an enable. Therefore if the sample rate is less than or equal to the value you specify in the dialog box, data can pass more slowly to the filter. Use this feature when the sample rates of the filters are not all divisible by the clock rate. 1 Always, take care to generate the first valid signal when there is some real data and to connect this signal throughout the design. The valid signal is a stream synchronization signal. In primitive subsystems, DSP Builder guarantees all signals that connect to ChannelOut blocks line up in the same clock cycle. That is, the delays on all paths from and to these blocks balance. However, you must ensure all the signals arrive at a ChannelIn block in the same clock cycle. The ModelIP blocks follow the same rules. Thus it is easy to connect ModelIP and primitive subsystems. The ModelIP filters all use the same protocol with an additional simplificationDSP Builder produces all the channels for a frame in a multichannel filter in adjacent cycles, which is also a requirement on the filter inputs. If a FIR filter needs to use flow control, pull down the valid signal between frames of datajust before you present channel 0 data. The same <data, valid, channel> protocol connects all CIC and FIR filter blocks and all subsystems with primitive blocks. The blocks in the Waveform Synthesis library support separate real and complex (or sine and cosine) signals. The design may require some splitting or combining logic when using the mixer blocks. Use a primitive subsystem to implement this logic. Figure 12 shows how a splitter extracts the real and imaginary channels when connecting a CIC or FIR filter to the ComplexMixer. Similarly, use a combiner when connecting the output from a mixer to a downstream filter.
Figure 12. Connecting a Filter to a ComplexSampleDelay
For an example that connects a CIC Filter, NCO, and ComplexSampleDelay blocks, refer to 16-Channel DUC on page 28. For an example that connects NCO, Real Mixer, and CIC Filter blocks, refer to 16-Channel DUC on page 28.
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Time-Division Multiplexing
Use time-division multiplexing to optimize hardware utilization. The time-division multiplexed (TDM) factor (or folding factor) is the ratio of the clock rate to the sample rate. By clocking a ModelIP block faster than the sample rate, you can re-use the same hardware. For example, by implementing a filter with a TDM factor of 2 and an internal clock multiplied by 2, you can halve the required hardware (Figure 13).
Figure 13. TDM to Save Hardware Resource
To achieve the TDM factor, the design requires a serializer and deserializer before and after the reused hardware block to control the timing. The ratio of system clock frequency to sample rate determines the amount of resource saving except for a small amount of additional logic for the serializer and deserializer. Table 12 shows the estimated resources for a 49-tap symmetric FIR filter.
Table 12. Example Resource Saving for a 49-Tap Single rate FIR Filter Clock Rate (MHz) 72 144 288 72 Sample Rate (MSPS) 72 72 72 36 Logic 2230 1701 1145 1701 Multipliers 25 13 7 13 Memory Bits 0 468 504 468 TDM Factor 1 2 4 2
When the sample rate equals the clock rate, because the filter is symmetric you just need 25 multipliers. When you increase the clock rate to 2 sample rate, the number of multipliers the design requires drops by half to 13. When the clock rate is set to 4 sample rate, the number of multipliers the design requires drops to 7. If the clock rate stays the same while the new data sample rate is only 36 MSPS (million samples per second), the resource consumption is the same as for the 2 sample rate case.
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You can implement the TDM factor automatically in primitive subsystems where the sample rate is less than the clock rate by enabling folding (refer to Folding on page 71).
Multichannel Operation
To build multichannel systems directly use the required channel count, rather than create a single channel system and scale it up. The block diagrams use vectors of wires to scale without cutting and pasting multiple blocks. 1 Each channel is an independent data source. An IF Modem design requires two channels for the complex pair from each antenna. The ModelIP blocks are vectorizable, if data going into a block is a vector requiring multiple instances of, for example a FIR filter, DSP Builder creates multiple FIR blocks in parallel behind a single ModelIP block. If a decimating filter requires a smaller vector on the output, data from individual filters use the TDM factor onto the output vector automatically, to avoid using glue filters for custom logic. Consider the following two cases:
ModelIP blocks typically take a channel count as a parameter. This is simple to conceptualize. DSP Builder numbers the channels 0 to (N-1), and you can uses the channel indicator at any point to filter out some channels. To merge two streams, DSP Builder creates some logic to multiplex the data. Sequence and counter blocks regenerate valid and channel signals. Primitive Subsystems. The primitive subsystems contain ChannelIn and ChannelOut blocks, but do not have explicit support for multiple channels. To create multichannel logic, draw out the logic required for your design to create a single channel version. To transform to a multichannel system, increase all the delays by the channel count required. Use a mask variable to create a parameterizable component. For an example, refer to the Multi-Channel IIR Filter on page 219.
Vectorized Inputs
The data inputs and outputs for the ModelIP blocks can be vectors, which is useful when the clock rate is insufficiently high to carry the total aggregate data. For example, 10 channels at 20 MSPS require 1020 = 200 MSPS aggregate data rate. If the system clock rate is set to 100 MHz, two wires carry this data, and so the Simulink model uses a vector of width 2. This approach is unlike traditional methods because you do not need to manually instantiate two ModelIP blocks and pass a single wire to each in parallel. Each ModelIP block internally vectorizes. DSP Builder uses the same paradigm on outputs, where it represents high data rates on multiple wires as vectors. Each ModelIP block determines the input and output wire counts, based on the clock rate, sample rate, and number of channels.
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Any rate changes in the ModelIP block affect the output wire count. If there is a rate change, such as interpolating by two, the output aggregate sample rate doubles. DSP Builder packs the output channels into the fewest number of wires (vector width) that supports that rate. For example, an interpolate by two FIR filter may have two wires at the input, but three wires at the output. The ModelIP block performs any necessary multiplexing and packing. The blocks connected to the inputs and outputs must have the same vector widths, which Simulink enforces. Resolve vector width errors by carefully changing the sample rates. 1 Most ModelPrim blocks also accept vector inputs.
Channelization
Use the following variables to determine the number of wires and the number of channels each wire carries by parameterization:
ClockRate is the system clock frequency. SampleRate is the data sample rate per channel (MSPS). ChanCount is the number of channels. 1 Channels are enumerated from 0 to ChanCount 1.
The Period (or TDM factor) is the ratio of the clock rate to the sample rate and determines the number of available time slots: Period = max(1, floor(ClockRate/SampleRate))
The number of channel wires the design requires to carry all the channels is the number of channels divided by the TDM factor (except for supersampled filters): ChanWireCount = WiresPerChannel WireGroups
The number of channels carried per wire is the number of channels divided by the number of channels per wire: ChanCycleCount = ceil(ChanCount/WireGroups) 1 The channel signal counts through 0 to ChanCycleCount 1.
The WireGroups is the number of wire groups to carry all the channels regardless of channel rate: WireGroups = ceil(ChanCount / Period);
Figure 14 on page 115 shows how a TDM factor of 3 combines two input channels into a single output wire (ChanCount = 2, ChanWireCount = 1, ChanCycleCount = 2). If the number of channels is greater than the period, multiple wires are required. Each ModelIP block in your design is internally vectorized to build multiple blocks in parallel.
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Figure 15 on page 115 shows how a TDM factor of 3 combines four input channels into two wires (ChanCount = 4, ChanWireCount = 2, ChanCycleCount = 2).
Figure 14. Channelization for Two Channels with a TDM Factor of 3
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The generated Help page for the block shows the input and output data channel format that the FIR or CIC filter use after you have run a Simulink simulation. DSP Builder uses the channel signal for synchronization and scheduling of data. It specifies the channel data separation per wire. The channel signal counts from 0 to ChanCycleCount 1 in synchronization with the data. Thus, for ChanCycleCount = 1, the channel signal is the same as the channel count, enumerated 0 to ChanCount 1. For more than a single data wire, it is not equal to the channel count on data wires, but specifies the synchronous channel data alignment across all the data wires. For example, Figure 16 shows the case for four channels of data on one data wire with no invalid cycles.
Figure 16. Four Channels on One Wire
For a single wire, the channel signal is the same as a channel count. However, for ChanWireCount > 1, the channel signal specifies the channel data separation per wire, rather than the actual channel number: it counts from 0 to ChanCycleCount 1 rather than 0 to ChanCount 1. Figure 17 shows four channels on two wires with no invalid cycles.
Figure 17. Four Channels on Two Wires
The channel signal remains a single wire, not a wire for each data wire. It counts over 0 to ChanCycleCount 1, Figure 18 shows four channels simultaneously on four wires.
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Simulink shows the ModelIP block as a single block, but the data input and output wires from the ModelIP blocks show as a vector with multiple dimension. Multiple wires accommodate all the channels and the Simulink model uses a vector of width 2 (Figure 19).
Figure 19. Simulink and Hardware Representations of a Single Rate FIR Filter
To display the ChanWireCount in Simulink, point to Port/Signal Displays in the Format menu and click Signal Dimensions. For more information about channelization in a real design, refer to AN 544: Digital Modem Design with the DSP Builder Advanced Blockset.
Memory-Mapped Interfaces
DSP Builder includes a pipelined memory-mapped interface for all the programming registers in a design. For example, in the demo_ddc design, these registers include coefficient registers for filters, control registers for NCO frequencies, and individual control registers that you can use for any purpose such as providing programmable scaling. DSP Builder gathers the register map for your design into an XML file that it processes to produce design documentation to display in updated online Help for the Control block.
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Hardware Interfaces
A typical ModelIP block has the following main interfaces:
Control signals: a synchronous clock and two asynchronous reset signals. The reset returns internal state machines to initialized states. Input port: consists of three input signals, data, valid, and channel. DSP Builder writes the data to the core by asserting the valid signal, and providing the channel input all during the same clock cycle. You must provide the data for multiple channels on consecutive cycles, with a single gap of non-valid data until the next sample time. Figure 110 shows typical inputs data a_v, a_c, and a_0 for a 4-channel FIR filter with 10 cycles. To process the channels (t12 - t2 is the time between successive data samples for channel 0).
Output port: uses the same data, valid and channel signals as the input. DSP Builder writes contiguously the data for each channel for each sample. Figure 110 shows typical output data. The interpolation rate determines the output data timing. For interpolation of two, twice as many valid cycles exist as on the input. Memory-mapped interface: allows access to the internal data coefficients and consists of inputs address, write data, and write enable; and outputs read data and read valid. You may use a separate bus clock for this interface. Figure 111 shows a write cycle (time-steps 2 to 6) and a read cycle (time-steps 10 to 14).
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The DSP Builder advanced blockset uses these interfaces to build up chains of filters without additional glue logic, even with sample rate changes. It builds the necessary bus decode logic to access all registers in the datapath.
Design Semantics
Simulink uses the time-step representation of the system clock rate to represent a design. Although, the multi-rate system has multiple sample rates, the Simulink multiple sample-time features does not represent them. Other Simulink-based design systems disable the hardware based on the sample time (wasting hardware that is inactive for much of the time).
Fixed-point Representation
DSP Builder uses the built-in Simulink fixed-point types to specify all the signals in a DSP Builder advanced blockset design. Thus it is easy to debug your design, because you can display the signals as familiar floating-point types. Using fixed-point types allows you to preserve the extra information of binary point position through hardware blocks, so that it is easy to perform rounding and shifting operations without manually tracking the interpretation of an integer value. When you start to tune the performance of your model, a fixed-point type change propagates through your design, with all downstream calculations automatically adjusted.
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The datapath components in the DSP Builder advanced blockset use a single clock rate. An external processor uses a separate bus clock to read and write any primitive registers or shared memories and ModelIP block parameters through an Avalon Memory-Mapped (Avalon-MM) interface. The bus clock is usually not performance critical and can run at a lower clock rate, which allows easier timing closure in many cases. Running the clock as an integer fraction of the system clock rate ensures that no timing issues exist and that both clocks have co-incident edges. In many cases, the bus clock can have any frequency. Set the clock rates in the Signals block (Signals Block on page 14). 1 The memory-mapped input and output registers clear when the system is reset but DSP Builder retains the contents of the dual memory that the FIR Filter, NCO, and ModelBus blocks use. For information about the Avalon-MM Interface, refer to the Avalon Interface Specifications.
Simulation
At the start of each Simulink simulation run, each ModelIP block resynthesizes into an internal representation of the hardware components and Simulink writes it out as VHDL RTL. The internal representation makes simulation fast, and ensures bit and cycle accuracy. Simulink performs this process very quickly, and gives greatly increased productivity over traditional flows where you must configure your design in an external tool, import it into the simulator, and then run the simulation.
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Generated Files
Table 13 lists the files that DSP Builder generates for an advanced blockset design. DSP Builder generates the files in a directory structure at the location you specify in the Control block, which defaults to ..\rtl (relative to the working directory that contains the .mdl file). This directory structure uses the same hierarchy as the subsystems in your design with the files in lower level directories referenced from a corresponding file in its parent directory. For example, there is a Quartus II IP (.qip) file in the <model name> subdirectory that references a .qip file in a lower level subdirectory that references a .qip file in the next lower level and so on throughout your design hierarchy. Any RAM in your design may generate Intel format hexadecimal (.hex) files to initialize the RAM. Usually, the RAM is part of ModelIP blocks (such as the CIC, NCO, or FIR Compiler) which are expandable to lower-level functions such as RAM or ADDSub. A .qip file for a subsystem containing such blocks has the initializing .hex files referenced from the .qip file.
Table 13. Generated Files for the DDC Design Example File rtl directory <model name>.xml <model name>_entity.xml rtl\<model name> subdirectory <block name>.xml <model name>.vhd An XML file containing information about each block in the advanced blockset, which translates into HTML on demand for display in the MATLAB Help viewer. This is the top-level testbench file. It may contain non-synthesizable blocks, and may also contain empty black boxes for Simulink blocks that are not fully supported. This script loads the VHDL files in this subdirectory and in the subsystem hierarchy below it into the Quartus II project. This file contains information about all the files DSP Builder requires to process your design in the Quartus II software. The file includes a reference to any .qip file in the next level of the subsystem hierarchy. DSP Builder generates a VHDL file for each component in your model. An XML file that describes the boundaries of a subsystem as a block-box design (for Signal Compiler in designs that combine blocks from the standard and advanced blocksets). An XML file that describes the attributes of a subsystem. Stimulus files. Helper function that the .qip and .add.tcl files reference to ensure that pathnames read correctly in the Quartus II software. Helper function that ensures a pathname reads correctly in ModelSim. An XML file that describes the attributes of your model. An XML file that describes the boundaries of the system (for Signal Compiler in designs that combine blocks from the standard and advanced blocksets). Description
rtl\<model name>\<subsystem> subdirectories Separate subdirectories exist for each hierarchical level in your design, which include additional .xml, .vhd, qip, and .stm files describing the blocks in each level. Also additional .do, .tcl, and .add.tcl files exist that DSP Builder automatically calls from the corresponding files in the top-level of your model.
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Chapter 1: About the DSP Builder Advanced Blockset Creating a Quartus II Project
Table 13. Generated Files for the DDC Design Example File <subsystem>_atb.do <subsystem>_atb.wav.do <subsystem>/<block>/*.hex <subsystem>.sdc <subsystem>.tcl <subsystem>_hw.tcl Description Script that loads the subsystem automatic testbench into ModelSim. Script that loads signals for the subsystem automatic testbench into ModelSim. These are Intel format Hex files that initialize the RAM in your design for either simulation or synthesis. Design constraint file for TimeQuest support. This Tcl script exists only in the subsystem that contains a Device block. You can use this script to setup the Quartus II project. A TCl script that loads the generated hardware into SOPC Builder.
For an example of the files that DSP Builder generates for a typical design, refer to Exploring the Generated Files on page 514 in the System Tutorial.
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Loading in ModelSim
To load an automatic testbench, click Execute Macro on the Tools menu in ModelSim and select the .do file you require. For example, to run the automatic testbench for the NCOSubsystem subsystem in the NCO design example, select the demo_nco_NCOSubsystem_NCO_atb.do file.
where model = design name (without extension, in single quotes) entity = entity to test (the name of a primitive subsystem or a ModelIP block, in single quotes)
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rtl_path = optional path to the generated RTL (in single quotes, if not specified the path is read from the Control block in your model) For example:
run_modelsim_atb('demo_fft16_radix2', 'FFTChip');
The return values are in the format [pass, status, result] where: pass = 1 or 0 status = should be 0 result = should be a string such as: "# ** Note: arrived at end of stimulus data on clk <clock name>" An output file with the full path to the component under test writes in the working directory. DSP Builder creates a new file with an automatically incremented suffix each time the testbench is run. For example:
demo_fft_radix2_DUT_FFTChip_atb.6.out
This output file includes the ModelSim transcript and is useful for debugging if you encounter any errors. Typical error messages have the following form:
# ** Error (vcom-13) Recompile <path>altera_mf.altera_mf_components because <path>iee.std_logic_1164 has changed. ... # ** Error: <path>mdl_name_system_subsystem_component.vhd(30): (vcom-1195) Cannot find expanded name: 'altera_mf.altera_mf_components'. ... # ** Error: <path>vcom failed. ... # At least one module failed to compile, not starting simulation.
These errors may occur when a ModelSim precompiled model is out of date, but not automatically recompiled. A similar problem may occur after making design changes when ModelSim caches a previously compiled model for a component and does not detect when it changes. In either of these cases, delete the rtl directory, resimulate your design and run the run_modelsim_atb command again.
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For example:
run_all_atbs('demo_agc'); run_all_atbs('demo_agc', true); run_all_atbs('demo_agc', false, true); run_all_atbs('demo_agc', true, true);
The return value is 1 if all tests are successful or 0 if any tests fail. The output is written to the MATLAB command window. If you run the Quartus II Fitter, the command also reports whether the design achieves the target fMAX. For example:
Met FMax Requirement (FMax(291.04) >= Required(200))
A summary also writes to a file results.txt in the current working directory. For example:
Starting demo_agc Tests at 2009-01-23 14:58:48 demo_agc: demo_agc/AGC_Chip/AGC hardware matches simulation (atb#1): PASSED demo_agc: Quartus II compilation was successful. (Directory=../quartus_demo_agc_AGC_Chip_2): PASSED demo_agc: Met FMax Requirement (FMax(291.04) >= Required(200)): PASSED Finished demo_agc Tests at 2009-01-23 15:01:59 (3 Tests, 3 Passes, 0 Skipped, 0 Failed (fmax), 0 Failed (non-fmax))
To get a list of the blocks in a design that have automatic testbenches, run the following command:
getBlocksWithATBs(model)
You must have run a simulation of the design before running this command (or set the runSimulation argument to true). The script deletes any existing RTL directory before simulation occurs. If it cannot delete the directory, for example if the files are in use, the script fails with an appropriate error message.
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Similarly you can get and set other parameters. For example, on the Signals block you can set the target clock frequency:
fmax_freq = 300.0; set_param(signals{1},'freq', fmax_freq);
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You can also change the following threshold values that are parameters on the Control block:
You can loop over changing these values, change the destination directory, run the Quartus II software each time, and perform design space exploration. For example:
%% Run a simulation; which also does the RTL generation. t = sim(model); %% Then run the Quartus II compilation flow. [success, details] = run_hw_compilation(<model>, './') %% where details is a struct containing resource and timing information details.Logic, details.Comb_Aluts, details.Mem_Aluts, details.Regs, details.ALM, details.DSP_18bit, details.Mem_Bits, details.M9K, details.M144K, details.IO, details.FMax, details.Slack, details.Required, details.FMax_unres, details.timingpath, details.dir, details.command, details.pwd such that >> disp(details) gives output something like: Logic: 4915 Comb_Aluts: 3213 Mem_Aluts: 377 Regs: 4725 ALM: 2952 DSP_18bit: 68 Mem_Bits: 719278
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M9K: 97 M144K: 0 IO: 116 FMax: 220.1700 Slack: 0.4581 Required: 200 FMax_unres: 220.1700 timingpath: [1x4146 char] dir: '../quartus_demo_ifft_4096_natural_for_SPR_FFT_4K_n_2' command: [1x266 char] pwd: 'D:\test\script'
The Timing Report is in the timingpath variable, which you can display by disp(details.timingpath). Unused resources may appear as -1, rather than 0.
You must previously execute load_system before commands such as find_system and run_hw_compilation work. A useful set of commands to generate RTL, compile in the Quartus II software and return the details is:
load_system(<model>); sim(<model>); [success, details] = run_hw_compilation(<model>, './')
The ModelIP Tutorial (Chapter 3) shows how to use the ModelIP NCO block to create a customized NCO. The tutorial performs RTL simulation in ModelSim, compiles your design in the Quartus II software, and instantiates your design as a subsystem in the SOPC Builder. The Primitive Library Tutorial (Chapter 4) shows how you can use blocks from the ModelPrim library to build a simple design. The System Tutorial (Chapter 5) shows how you can plug blocks together to create a digital downconverter (DDC).
The Altera DSP Builder advanced blockset provides a variety of design examples, which you can use to learn from or as a starting point for your own design. This section describes the available design examples. To view all the design examples, type demo at the MATLAB command prompt. The Demos tab opens in the Help window displaying a list of the available design examples. You can click DSP Builder Advanced Blockset in the Help window to expand the list and click on an entry to display a Help page for each design example. All the design examples have the same basic structure: a top-level testbench containing an instantiated functional block, which represents the hardware design. The testbench typically includes Simulink source blocks that generate the stimulus signals and sink blocks that display simulation results. You can use other Simulink blocks to define the testbench logic. The testbench also includes the following blocks from the DSP Builder advanced blockset:
The Control block specifies information about the hardware generation environment, and the top-level memory-mapped bus interface widths. The Signals block specifies information about the clock, reset, and memory bus signals that the simulation model and the hardware generation use. The Edit Params block provides direct access to a MATLAB M-script that sets up MATLAB workspace variables that parameterize each block. The PreLoadFcn and InitFcn callbacks specify the script, which you can access by clicking Model Properties on the File menu and is usually named setup_<demo name>.m). The Run ModelSim block loads the testbench into the ModelSim simulator. The Run Quartus II block loads the system into the Quartus II software. The ChanView block in a testbench allows you to visualize the contents of the TDM protocol. This block generates synthesizable HDL and can therefore also be useful in a functional subsystem.
The functional subsystem in each design contains a Device block that marks the top-level of the FPGA device and controls the target device for the hardware. f For more information about these blocks, refer to the DSP Builder Advanced Blockset Libraries section in volume 3 of the DSP Builder Handbook.
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or simply:
demo_nco r
Primitive FIR with Back Pressure (demo_back_pressure) Primitive FIR with Forward Pressure (demo_forward_pressure) Kronecker Tensor Product (demo_kronecker) Rectangular Nested Loop Triangular Nested Loop Sequential Loops Parallel Loops
Platforms. This folder contains the following design examples that illustrate how you can implement a DDC or digital up converter (DUC) for use in a radio basestation. These designs provide a starting point to build your own filter chain that meets your exact needs.
16-Channel DDC (demo_ddc) 16-Channel DUC (demo_duc) 2-Channel DUC (demo_AD9856) 2-Antenna DUC for WiMAX (demo_wimax_duc) System (demo_ddc)
Filters. This folder contains the following design examples of cascaded integrator-comb (CIC) and finite impulse response (FIR) filters:
Decimating CIC Filter (demo_dcic) Interpolating CIC Filter (demo-icic) Single Rate FIR Filter (demo_firs) Decimating FIR Filter (demo_fird) Interpolating FIR Filter (demo_firi) Fractional Rate FIR Filter (demo_firf) Half Band FIR Filter (demo_firih) Root Raised Cosine FIR Filter (demo_fir_rrc) Fractional FIR Filter Chain (demo_fir_fractional) Super-Sample FIR Filter (demo_ssfiri) Filter Chain with Forward Flow Control (demo_filters_flow_control) Multiple Coefficient Banks Interpolating FIR Filter
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Waveform Synthesis. This folder contains the following design examples that synthesize waveforms with a NCO or direct digital synthesis (DDS):
NCO (demo_nco) Real Mixer (demo_mix) Complex Mixer (demo_complex_mixer) Four Channel, Two Banks NCO (demo_mc_nco_2banks_mem_interface) Four Channel, Four Banks NCO (demo_mc_nco_4banks_mem_interface) Four Channel, Eight Banks, Two Wires NCO (demo_mc_nco_8banks_2wires) Four Channel, 16 Banks NCO (demo_mc_nco_16banks) Four Channel, 64 Banks NCO (demo_mc_nco_64banks)
Primitive Blocks. This folder contains the following design examples built with primitive blocks from the ModelPrim library:
Hello World (helloWorld) Fibonacci Series (demo_fibonacci) Automatic Gain Control (demo_agc) Multi-Channel IIR Filter (demo_iir) 88 Inverse Discrete Cosine Transform (demo_idct8x8) Quadrature Amplitude Modulation (demo_QAM256) Radix 2 Streaming FFT (demo_fft16_radix2) Radix 4 Streaming FFT (demo_fft256_radix4) 4K FFT (demo_fft_4096_br) 8K FFT (demo_fft_8192_br) 4K IFFT (demo_ifft_4096_natural) 8K IFFT (demo_ifft_8192_natural) Test CORDIC Functions Using Primitive Blocks (demo_cordic_primitives) Test CORDIC Functions Using the CORDIC Block (demo_cordic_lib_block) Folded Color Space Converter Folded Single-stage IIR Filter Folded 3-stage IIR Filter Folded Primitive FIR Filter Hybrid Direct Form and Transpose Form FIR Filter Digital Predistortion Forward Path Run-time Configurable Decimating and Interpolating Half-rate FIR Filter Matrix Initialization of Vector Memories Matrix Initialization of LUT Vector Initialization of Sample Delay
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Host Interface. This folder contains a design example showing how you can control memory-mapped registers:
Base Blocks. This folder contains design examples of the Scale and the LocalThreshold block:
Reference Designs. This folder accesses groups of reference designs that illustrate the design of DDC and DUC systems for digital intermediate frequency (IF) processing. The first group implement IF modem designs compatible with the wideband Code Division Multiple Access (W-CDMA) standard:
4-Carrier, 2-Antenna W-CDMA DDC (wcdma_multichannel_ddc_mixer) 1-Carrier, 2-Antenna W-CDMA DDC (wcdma_picocell_ddc_mixer) 4-Carrier, 2-Antenna W-CDMA DUC (wcdma_multichannel_duc_mixer) 1-Carrier, 2-Antenna W-CDMA DDC (wcdma_picocell_duc_mixer) 4-Carrier, 2-Antenna High-Speed W-CDMA DUC at 368.64 MHz with Total Rate Change 32 (wcdma_multichannel_duc_mixer_96x_32R) 4-Carrier, 2-Antenna High-Speed W-CDMA DUC at 368.64 MHz with Total Rate Change 48 (wcdma_multichannel_duc_mixer_96x_48R) 4-Carrier, 2-Antenna High-Speed W-CDMA DUC at 307.2 MHz with Total Rate Change 40 (wcdma_multichannel_duc_mixer_80x_40R)
The second group implements IF modem designs compatible with the Worldwide Interoperability for Microwave Access (WiMAX) standard. Altera provide separate models for one and two antenna receivers and transmitters:
1-Antenna WiMAX DDC (wimax_ddc_1rx) 2-Antenna WiMAX DDC (wimax_ddc_2rx_iiqq) 1-Antenna WiMAX DUC (wimax_duc_1tx) 2-Antenna WiMAX DUC (wimax_ddc_2tx_iiqq)
Design Examples
This section describes the available design examples.
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After you run a simulation, Simulink replaces the Help page for each DSP Builder advanced blockset block (which displays when you click Help on the popup menu for the blocks) by a page showing information about the actual block usage. 1 You can return to the normal Help page by clicking on the Help on core functionality of <block name> link.
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The final block uses an external ready signal that comes from a downstream block in the system.
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Sequential Loops
In this design example, two inner loops (InnerLoopA and InnerLoopB) both nest within the outer loop. The design example daisy chains the ld port of InnerLoopA to the ls port of InnerLoopB rather than connecting it directly to the bd port of OuterLoop. Thus each activation of InnerLoopA is followed by an activation of InnerLoopB. The model file is forloop_seqloop.mdl.
Parallel Loops
This design example has two inner loops nested within the outer loop. The inner loops execute in parallel rather than sequentially. The two inner loops are started simultaneously by duplicating the control token but finish at different times. The RendezVous block waits until both of them finish and then passes the control token back to the outer loop. The model file is forloop_parloop.mdl.
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16-Channel DDC
This design example shows how to use using ModelIP and ModelBus blocks to build a 16-channel digital-down converter for modern radio systems. Decimating CIC and FIR filters down convert eight complex carriers (16 real channels) from 61.44 MHz. The total decimation rate is 64. A real mixer and NCO isolate the eight carriers. The testbench isolates two channels of data from the TDM signals using a channel viewer. The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus II blocks, plus a ChanView block that deserializes the output bus. An Edit Params block allows easy access to the setup variables in the setup_demo_ddc.m script. The DDCChip subsystem includes Device, Decimating FIR, DecimatingCIC, Mixer, NCO, Scale, RegBit, and RegField blocks. The model file is demo_ddc.mdl. 1 This design example uses the Simulink Signal Processing Blockset.
16-Channel DUC
This design example shows how to build a 16-channel DUC as found in modern radio systems using ModelIP, ModelBus, and ModelPrim blocks. An interpolating filter chain is presented. interpolating CIC and FIR filters up convert eight complex channels (16 real channels). The total interpolation rate is 50. DSP Builder integrates several primitive subsystems into the datapath. This design example shows how you can integrate ModelIP blocks with primitive subsystems:
There is a programmable Gain subsystem at the beginning of the datapath. This subsystem shows how you can use processor-visible register blocks to control a datapath element. The Sync subsystem is a primitive subsystem that shows how to manage two data streams coming together and synchronizing. DSP Builder writes the data from the NCOs to a memory with the channel as an address: the data stream using its channel signals to read out the NCO signals. This resynchronizes the data correctly. Alternatively, you can simply delay the NCO value by the correct number of cycles to ensure that the NCO and channel data arrive at the Mixer on the same cycle.
Extensive use is made of Simulink multiplexer and demultiplexer blocks to manage vector signals. The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus II blocks, plus a ChanView block that deserializes the output bus. An Edit Params block allows easy access to the setup variables in the setup_demo_duc.m script. The DUCChip subsystem includes a Device block and a lower level DUC16 subsystem. The DUC16 subsystem includes InterpolatingFIR, InterpolatingCIC, ComplexMixer, NCO, and Scale blocks.
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It also includes lower level Gain, Sync, and CarrierSum subsystems which make use of other ModelBus and ModelPrim blocks including AddSLoad, And, BitExtract, ChannelIn, ChannelOut, CompareEquality, Const, SampleDelay, DualMem, Mult, Mux, Not, Or, RegBit, RegField blocks, and SynthesisInfo blocks. The model file is demo_duc.mdl. 1 This design example uses the Simulink Signal Processing Blockset.
2-Channel DUC
This design example shows how to build a 2-channel DUC as found in an ASSP chip. Interpolating CIC and FIR filters up convert a single complex channel (2 real channels). A NCO and Mixer subsystem combine the complex input channels into a single output channel. This design example shows how quick and easy it is to emulate the contents of an existing datapath. A primitive block implements the mixer in this design example as the data rate is low enough to save resource using a time-shared hardware technique. The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus II blocks, plus a ChanView block that deserializes the output bus. An Edit Params block allows easy access to the setup variables in the setup_demo_AD9856.m script. The AN9856 subsystem includes a Device block and a lower level DUCIQ subsystem. The DUCIQ subsystem includes Const, InterpolatingFIR, SingleRateFIR, InterpolatingCIC, NCO, Scale blocks, and a lower level Mixer subsystem. The Mixer subsystem includes ChannelIn, ChannelOut, Mult, Const, BitExtract, CompareEquality, And, Delay, Sub, and SynthesisInfo blocks. The model file is demo_AD9856.mdl. 1 This design example uses the Simulink Signal Processing Blockset.
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System
The system tutorial describes the 16-channel DDC design example in detail and shows how you can combine blocks to build a system-level design. System Tutorial on page 51 describes this design example. 1 This design example uses the Simulink Signal Processing Blockset.
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The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus II blocks, plus ChanView block that deserialize the output buses. An Edit Params block allows easy access to the setup variables in the setup_demo_firih.m script. The FilterSystem subsystem includes the Device block and two separate InterpolatingFIR blocks for the regular and interpolating filters. The model file is demo_firih.mdl. 1 This design example uses the Simulink Signal Processing Blockset.
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After simulation, right-click on the FIR, select Help and scroll down to the input and output data format sections. The model file is demo_ssfiri.mdl. 1 This design example uses the Simulink Signal Processing Blockset.
NCO
This design example uses the NCO block from the Waveform Synthesis library to implement an NCO. A Simulink double precision sine or cosine wave compares the results. The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus II blocks, plus ChanView blocks that deserialize the output buses. An Edit Params block allows easy access to the setup variables in the setup_demo_nco.m script. The NCOSubSystem subsystem includes the Device and NCO blocks. The model file is demo_nco.mdl. 1 This design example uses the Simulink Signal Processing Blockset.
Real Mixer
This design example shows how to mix non-complex signals. The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus II blocks, plus ChanView block that deserialize the output buses. An Edit Params block allows easy access to the setup variables in the setup_demo_mix.m script.
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The MixerSystem subsystem includes the Device and Mixer blocks. The model file is demo_mix.mdl. 1 This design example uses the Simulink Signal Processing Blockset.
Complex Mixer
This design example shows how to mix complex signals. The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus II blocks, plus ChanView block that deserialize the output buses. An Edit Params block allows easy access to the setup variables in the setup_demo_complex_mixer.m script. The FilterSystem subsystem includes the Device and ComplexMixer blocks. The model file is demo_complex_mixer.mdl. 1 This design example uses the Simulink Signal Processing Blockset.
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Four writes for each bank exist to write new values for channel 1 and 2 into bank 0, and new values for channel 3 and 4 into bank 1. Each new phase value needs two registers due to the size of the memory interface. The spectrum scope shows that there are three peaks for a selected channel with the first two peaks representing the two banks and the third peak showing the frequency that you specify through the memory interface. The scope of the select channel shows the sinusoidal waves of the channel you select. You can zoom in to see that smooth and continuous sinusoidal signals at the switching point. You can also see the frequency changes after 8000 steps where the phase increment value alters through the memory interface. The top-level testbench includes Control, Signals, BusStimulus, Run ModelSim, and Run Quartus II blocks, plus ChanView blocks that deserialize the output buses. An Edit Params block allows easy access to the setup variables in the setup_demo_mc_nco_2banks_mem_interface.m script. The NCOSubSystem subsystem includes the Device and NCO blocks. The model file is demo_mc_nco_2banks_mem_interface.mdl. 1 This design example uses the Simulink Signal Processing Blockset.
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The top-level testbench includes Control, Signals, BusStimulus, Run ModelSim, and Run Quartus II blocks, plus ChanView blocks that deserialize the output buses. An Edit Params block allows easy access to the setup variables in the setup_demo_mc_nco_4banks_mem_interface.m script. The NCOSubSystem subsystem includes the Device and NCO blocks. The model file is demo_mc_nco_4banks_mem_interface.mdl. 1 This design example uses the Simulink Signal Processing Blockset.
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A workspace variable phaseIncr defines the 16 (rows) 4 (columns) matrix for the phase increment input with the phase increment values that the setup script calculates. The input for the bank index is set up so that it cycles from 0 to 15 with each bank lasting 1200 steps. The spectrum display shows clearly that there are 16 peaks for the selected channel indicating that the design example generates 16 different frequencies for that channel. The scope of the selected channel shows the sinusoidal waves of the selected channel. You can zoom in to see that the design example generates smooth and continuous sinusoidal signals at the switching point. The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus II blocks, plus ChanView blocks that deserialize the output buses. An Edit Params block allows easy access to the setup variables in the setup_demo_mc_nco_16banks.m script. The NCOSubSystem subsystem includes the Device and NCO blocks. The model file is demo_mc_nco_16banks.mdl. 1 This design example uses the Simulink Signal Processing Blockset.
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ModelIP
The ModelIP design example describes how you can build a NCO design with the NCO block from the Waveform Synthesis library. ModelIP Tutorial on page 31 describes this design example. 1 This design example uses the Simulink Signal Processing Blockset.
Hello World
This design example is a simple primitive design example that outputs a simple text message that it stores in a look-up table. An external input enables a counter that addresses a lookup-table (LUT) that contains some text. The design example writes the result to a MATLAB array. You can examine the contents with a char(message) command in the MATLAB command window. This design example does not use any ChannelIn, ChannelOut, GPIn, or GPOut blocks. The design example uses Simulink ports for simplicity although they prevent the automatic testbench flow from working. The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus II blocks. The Chip subsystem includes Device, Counter, Lut, and SynthesisInfo blocks. 1 In this design example, the top-level of the FPGA device (marked by the Device block) and the synthesizable primitive subsystem (marked by the SynthesisInfo block) are at the same level. The model file is helloWorld.mdl.
Fibonacci Series
This design example generates a Fibonacci sequence. This design example shows that even for circuitry with tight feedback loops and 120-bit adders, designs can achieve high data rates by the pipelining algorithms. The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus II blocks. The Chip subsystem includes the Device block and a lower level FibSystem subsystem. The FibSystem subsystem includes ChannelIn, ChannelOut, SampleDelay, Add, Mux, and SynthesisInfo blocks. 1 In this design example, the top-level of the FPGA device (marked by the Device block) and the synthesizable primitive subsystem (marked by the SynthesisInfo block) are at different hierarchy levels. The model file is demo_fibonacci.mdl.
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The DUT subsystem includes the Device block and a lower level FFTChip subsystem. The FFTChip subsystem uses the ComplexMult, Complex SampleDelay, and BFI blocks from the FFT library. It also includes ChannelIn, ChannelOut, Counter, BitExtract, Lut, Convert, SampleDelay, DualMem, and SynthesisInfo blocks. There is also a BitReverse subsystem that is very similar to the more general purpose BitReverseCore masked subsystem in the FFT library, but without the channel signal. The model file is demo_fft16_radix2.mdl.
4K FFT
This design example implements a 4,096 point, Radix 22 fast Fourier transform. This design example accepts data in bit reversed order, but the data is in natural order at the output of the FFT. The design example includes a bit-reversal block before the FFT algorithm, which makes the testbench easier to understand. The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus II blocks. An Edit Params block allows easy access to the setup variables in the setup_demo_fft_4096_br.m script. 1 The FFT designs do not inherit width in bits and scaling information. The design example specifies these values with the Wordlength and FractionLength variables in the setup script, which are 16 and 19 for this design example. You can also set the maximum width in bits by setting the MaxOut variable. Most applications do not need the maximum width in bits. To save resources, set a threshold value for this variable. The default value of inf allows worst case bit growth.
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The FFT_4K_br subsystem includes the Device block, a BitReverseCore block from the Filter library and a lower level FFT_4K_BR_Natural subsystem. The FFT_4K_BR_Natural subsystem uses the ComplexMult, Complex SampleDelay, BFI, BFII, and TwiddleGenerator blocks from the FFT library. It also includes ChannelIn, ChannelOut, Counter, BitExtract, Sequence, SampleDelay, Convert, DualMem, Const, CompareEquality, OR Gate, Not Gate, Mux, and SynthesisInfo blocks. The model file is demo_fft_4096_br.mdl.
8K FFT
This design example implements a 8,192 point, Radix 22 fast Fourier transform. This design example accepts data in bit reversed order, but the data is in natural order at the output of the FFT. The design example includes a bit-reversal block before the FFT algorithm, which makes the testbench easier to understand. The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus II blocks. An Edit Params block allows easy access to the setup variables in the setup_demo_fft_8192_br.m script. 1 The FFT designs do not inherit width in bits and scaling information. The design example specifies these values with the Wordlength and FractionLength variables in the setup script, which are 16 and 19 for this design example. You can also set the maximum width in bits by setting the MaxOut variable. Most applications do not need the maximum width in bits. To save resources, set a threshold value for this variable. The default value of inf allows worst case bit growth. The FFT_8K_br subsystem includes the Device block, a BitReverseCore block from the Filter library and a lower level FFT_8K_BR_Natural subsystem. The FFT_8K_BR_Natural subsystem uses the ComplexMult, Complex SampleDelay, BFI, BFII, and TwiddleGenerator blocks from the FFT library. It also includes ChannelIn, ChannelOut, Counter, BitExtract, Sequence, SampleDelay, Convert, DualMem, Const, CompareEquality, OR Gate, Not Gate, Mux, and SynthesisInfo blocks. The model file is demo_fft_8192_br.mdl.
4K IFFT
This design example implements a 4,096 point, Radix 22 inverse fast Fourier transform. This design example accepts naturally ordered inputs, and the output of the FFT algorithm is in bit reversed order. The design example includes a bit-reversal block after the FFT algorithm so that the final result is easier to visualize. The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus II blocks. An Edit Params block allows easy access to the setup variables in the setup_demo_ifft_4096_natural.m script.
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The FFT designs do not inherit width in bits and scaling information. The design example specifies these values with the Wordlength and FractionLength variables in the setup script, which are 16 and 19 for this design example. To set the maximum width in bits, set the MaxOut variable. Most applications do not need the maximum width in bits. To save resources, set a threshold value for this variable. The default value of inf allows worst case bit growth. The FFT_4K_n subsystem includes the Device block, a BitReverseCore block from the Filter library and a lower level FFT_4K_Natural_BR subsystem. The FFT_4K_Natural_BR subsystem uses the ComplexMult, Complex SampleDelay, BFI, BFII, and TwiddleGenerator blocks from the FFT library. It also includes ChannelIn, ChannelOut, Counter, BitExtract, Sequence, SampleDelay, Convert, DualMem, Const, CompareEquality, OR Gate, Not Gate, Mux, and SynthesisInfo blocks. The model file is demo_ifft_4096_natural.mdl.
8K IFFT
This design example implements a 8,192 point, Radix 22 inverse fast Fourier transform. This design example accepts naturally ordered inputs. The output of the FFT algorithm is in bit reversed order. The design example includes a bit-reversal block after the FFT algorithm so that the final result is easier to visualize. The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus II blocks. An Edit Params block allows easy access to the setup variables in the setup_demo_ifft_8192_natural.m script. 1 The FFT designs do not inherit width in bits and scaling information. The design example specifies these values with the Wordlength and FractionLength variables in the setup script, which are 16 and 19 for this design example. To set the maximum width in bits, set the MaxOut variable. Most applications do not need the maximum width in bits. To save resources, set a threshold value for this variable. The default value of inf allows worst case bit growth. The FFT_8K_n subsystem includes the Device block, a BitReverseCore block from the Filter library and a lower level FFT_8K_Natural_BR subsystem. The FFT_8K_Natural_BR subsystem uses the ComplexMult, Complex SampleDelay, BFI, BFII, and TwiddleGenerator blocks from the FFT library. It also includes ChannelIn, ChannelOut, Counter, BitExtract, Sequence, SampleDelay, Convert, DualMem, Const, CompareEquality, OR Gate, Not Gate, Mux, and SynthesisInfo blocks. The model file is demo_ifft_8192_natural.mdl.
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This design example uses a 16-bit signed fixed-point. It illustrates rotating the input vector by a specified angle and rotating the input vector to the x-axis while recording the angle required to make that rotation. The top-level testbench includes Control, Signals, and Run Quartus II blocks. The CordicChip subsystem includes ChannelIn, ChannelOut, and SynthesisInfo blocks, plus sixteen Vector and sixteen Rotate masked subsystems that perform the CORDIC calculations. The design example uses Add, BitExtract, Const, Mux, Not, and Sub blocks to build the Vector and Rotate masked subsystems The model file is test_cordic_prim.mdl.
Y = 0.257R + 0.504G + 0.098B + 16 Cb = 0.148R 0.291G + 0.439B + 128 Cr = 0.439R 0.368G 0.071B + 128
The data arrives as three channels repeating every 10 clock cycles: <R><G><B>< x >< x >< x >< x >< x >< x >< x > The folding that the ChannelIn and ChannelOut blocks specify states there are three TDM slots and the data rate per channel is 10 MSps (1/10th of the 100-MHz clock). The ChannelIn block presents these three channels as a vectorthree wires in parallel. You implement your algorithm fully parallel. In compilation, the Quartus II software folds the hardware down to a more serial implementation. This example can fold the nine multiplications down to a fully serial, single-multiplier implementation within the 10 available cycles. After simulation, right-click on the Control block and open the generated help. The resource utilization table shows that hardware implementation uses one multiplier only.
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In this design example, the sample rate is less than the clock rate. Use the design example as is for the full-speed sample-rate clock-rate implementation and use the folding feature to TDM the hardware down to a single multiplier. After simulation you can right-click on the SynthesisInfo block and view help for details of the resource usage The model file is primitive_fir..mdl.
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Specify table contents as single row or column vector. The length of the 1D row or column vector determines the number of addressable entries in the table. If DSP Builder reads vector data from the table, all components of a given vector share the same value. When a look-up table contains vector data, you can provide a matrix to specify the table contents. The number of rows in the matrix determines the number of addressable entries in the table. Each row specifies the vector contents of the corresponding table entry. The number of columns must match the vector length, otherwise DSP Builder issues an error.
The default initialization of the LUT is a row vector round([0:255]/17). This vector is inconsistent with the default for the DualMem block, which is a column vector [zeros(16, 1)]. The latter form is consistent with the new matrix initialization form in which the number of rows determines the addressable size.
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Memory-Mapped Registers
This design example is an extreme example of using the processor registers to implement a simple calculator. Registers and shared memories write arguments and read results. The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus II blocks. The RegChip subsystem includes RegField, RegBit, RegOut, SharedMem, Const, Add, Sub, Mult, Convert, Select, BitExtract, Shift, and SynthesisInfo blocks. The model file is demo_regs.mdl.
Scale
This design example demonstrates the use of the Scale block. The testbench allows you to see a vectorized block in action. Displays in the testbench track the smallest and largest values to be scaled and verify the correct behavior of the saturation modes. The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus II blocks, plus a ChanView block that deserializes the output bus. The ScaleSystem subsystem includes the Device and Scale blocks. The model file is demo_scale.mdl.
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Local Threshold
This design example has two identical NCOsone is in a subsystem with a LocalThreshold block that is set to force soft rather than hard multipliers. After simulation, right-click on the Control block and select Help. In the resource table, you can compare the resources for NCO and NCO1. NCO1 uses no multipliers at the expense of extra logic. The resource table also contains resources for the ChannelViewer blockssynthesizable blocks, that the design example uses outside the device system. The model file is demo_nco_threshold.mdl.
Reference Designs
The installation also includes reference designs that demonstrate the design of DDC and DUC systems for digital intermediate frequency (IF) processing. f For more information about these designs, refer to AN 544: Digital IF Modem Design with the DSP Builder Advanced Blockset.
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A system clock rate of 245.76 MHz drives the design on the FPGA, which the Device block defines inside the DUC subsystem. The model file is wcdma_multichannel_duc_mixer.mdl. 1 This reference design uses the Simulink Signal Processing Blockset.
4-Carrier, 2-Antenna High-Speed W-CDMA DUC at 368.64 MHz with Total Rate Change 32
This reference design uses ModelIP and ModelBus blocks to build a high-speed 16-channel, 2-antenna, multiple-frequency modulation DUC for use in an IF modem design compatible with the W-CDMA standard. The top-level testbench includes Control, Signals, and Run Quartus II blocks. A Spectrum Scope block computes and displays the periodogram of the outputs from the two antennas. The DUCChip subsystem includes a Device block to specify the target FPGA device, and a DUC subsystem that contains InterpolatingFIR, InterpolatingCIC, NCO, ComplexMixer, and Scale blocks. The FIR and CIC filters implement an interpolating filter chain that up converts the 16-channel input data from a frequency of 3.84 MSPS to a frequency of 122.88 MSPS (a total interpolation factor of 32). Because of the unusual FPGA clock frequency and total rate change combination, this design example uses dummy signals and carriers to achieve the desired rate up conversion. The complex mixer and NCO modulate the
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four channel baseband input signal onto the IF region. The design example configures the NCO with four channels to provide four pairs of sine and cosine waves at frequencies of 12.5 MHz, 17.5 MHz, 22.5 MHz and 27.5 MHz, respectively. The NCO has the same sample rate (122.88 MSPS) as the final interpolated output sample rate from the last CIC filter in the interpolating filter chain. The Sync subsystem shows how to manage two data streams that come together and synchronize. The data from the NCOs write to a memory with the channel as an address: the data stream uses its channel signals to read out the NCO signals, which resynchronizes the data correctly. The GenCarrier subsystem manipulates the NCO outputs to generate carrier signals that can align with the datapath signals. The CarrierSum and SignalSelector subsystems sum up the right modulated signals to the designated antenna. A system clock rate of 368.64 MHz, which is 96 times the input sample rate, drives the design on the FPGA, which the Device block defines inside the DUC subsystem. The higher clock rate can potentially allow resource re-use in other modules of a digital system implemented on an FPGA. The model file is wcdma_multichannel_duc_mixer_96x_32R.mdl. 1 This reference design uses the Simulink Signal Processing Blockset.
4-Carrier, 2-Antenna High-Speed W-CDMA DUC at 368.64 MHz with Total Rate Change 48
This reference design uses ModelIP and ModelBus blocks to build a high-speed 16-channel, 2-antenna, multiple-frequency modulation DUC for use in an IF modem design compatible with the W-CDMA standard. The top-level testbench includes Control, Signals, and Run Quartus II blocks. A Spectrum Scope block computes and displays the periodogram of the outputs from the two antennas. The DUCChip subsystem includes a Device block to specify the target FPGA device, and a DUC subsystem that contains InterpolatingFIR, InterpolatingCIC, NCO, ComplexMixer, and Scale blocks. The FIR and CIC filters implement an interpolating filter chain that up converts the 16-channel input data from a frequency of 3.84 MSPS to a frequency of 184.32 MSPS (a total interpolation factor of 48). The complex mixer and NCO modulate the four channel baseband input signal onto the IF region. The design configures the NCO with four channels to provide four pairs of sine and cosine waves at frequencies of 12.5 MHz, 17.5 MHz, 22.5 MHz, and 27.5 MHz, respectively. The NCO has the same sample rate (184.32 MSPS) as the final interpolated output sample rate from the last CIC filter in the interpolating filter chain. The Sync subsystem shows how to manage two data streams that come together and synchronize. The data from the NCOs write to a memory with the channel as an address: the data stream uses its channel signals to read out the NCO signals, which resynchronizes the data correctly.
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The CarrierSum and SignalSelector subsystems sum up the right modulated signals to the designated antenna. A system clock rate of 368.64 MHz, which is 96 times the input sample rate, drives the design on the FPGA, which the Device block defines inside the DUC subsystem. The higher clock rate can potentially allow resource re-use in other modules of a digital system implemented on an FPGA. The model file is wcdma_multichannel_duc_mixer_96x_48R.mdl. 1 This reference design uses the Simulink Signal Processing Blockset.
4-Carrier, 2-Antenna High-Speed W-CDMA DUC at 307.2 MHz with Total Rate Change 40
This reference design uses ModelIP and ModelBus blocks to build a high-speed 16-channel, 2-antenna, multiple-frequency modulation DUC for use in an IF modem design compatible with the W-CDMA standard. The top-level testbench includes Control, Signals, and Run Quartus II blocks. A Spectrum Scope block computes and displays the periodogram of the outputs from the two antennas. The DUCChip subsystem includes a Device block to specify the target FPGA device, and a DUC subsystem that contains InterpolatingFIR, InterpolatingCIC, NCO, ComplexMixer, and Scale blocks. The FIR and CIC filters implement an interpolating filter chain that up converts the 16-channel input data from a frequency of 3.84 MSPS to a frequency of 153.6 MSPS (a total interpolation factor of 40). The complex mixer and NCO modulate the four channel baseband input signal onto the IF region. The design configures the NCO with four channels to provide four pairs of sine and cosine waves at frequencies of 12.5 MHz, 17.5 MHz, 22.5 MHz, and 27.5 MHz, respectively. The NCO has the same sample rate (153.6 MSPS) as the final interpolated output sample rate from the last CIC filter in the interpolating filter chain. The Sync subsystem shows how to manage two data streams that come together and Synchronize. the data from the NCOs write to a memory with the channel as an address: the data stream uses its channel signals to read out the NCO signals, Which resynchronizes the data correctly. The CarrierSum and SignalSelector subsystems sum up the right modulated signals to the designated antenna. A system clock rate of 307.2 MHz, which is 80 times the input sample rate, drives the design on the FPGA, which the Device block defines inside the DUC subsystem. The higher clock rate can potentially allow resource re-use in other modules of a digital system implemented on an FPGA. The model file is wcdma_multichannel_duc_mixer_80x_40R.mdl. 1 This reference design uses the Simulink Signal Processing Blockset.
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A complex mixer and NCO modulate the two input channel baseband signals to the IF domain. The design configures the NCO to provide two sets of sine and cosine waves at a frequency of 22.4 MHz. The NCO has the same sample rate (89.6 MSPS) as the input data sample rate. The Sync subsystem shows how to manage two data streams coming together and synchronizing. DSP Builder writes the data from the NCOs to a memory with the channel as an address: the data stream using its channel signals to read out the NCO signals. This resynchronizes the data correctly. A system clock rate of 179.2 MHz drives the design on the FPGA, which the Device block defines inside the DUCChip subsystem. The model file is wimax_duc_2tx_iiqq.mdl. 1 This reference design uses the Simulink Signal Processing Blockset.
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A system clock rate of 245.76 MHz drives the design on the FPGA. The Signals block of the design defines this clock. The input random data for the 64 QAM symbol mapping subsystem has a data rate of 15.36 Msps. The model file is sc_LTEtxr.mdl.
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3. ModelIP Tutorial
The ModelIP tutorial is based on a NCO design. NCOs are efficient means of generating sinusoidal signals. They are useful when you require a continuous phase sinusoidal signal with variable frequency. The NCO block uses an octant based algorithm with trigonometric interpolation. The NCO block builds a 4-channel programmable NCO for use in a digital down-converter (DDC) or digital up-converter (DUC). Altera builds the design in the following stages: 1. Open the design example and set the configuration parameters. 2. Simulate the design example in Simulink and explore the generated files. 3. Simulate the RTL in ModelSim. 4. Compile with the Quartus II software. 5. Instantiate the design in SOPC Builder. You can customize the design in one of the following ways: 1. A 24-channel NCO targeting a system clock frequency of 360 MHz. 2. An NCO with increased spurious-free dynamic range (SFDR) of 130 dB.
You can also open the design example by clicking Open this model in the header for the ModelIP Tutorial in the Demos tab of the MATLAB Help viewer. Most of the top-level design blocks comprise the testbench, which contains the sources to drive the NCO and a collection of blocks to post process the data, displaying the results in the time and frequency domains.
The Control Block controls whether to generate hardware, the destination directory, the parameters for testbench creation, selects a big endian or little endian system bus, and specifies the memory-mapped interface details. Place a Control block at the top-level of each design example.
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The Signals block sets up the clock and reset names and parameters for the system. Place one Signals block at the top-level of each design. At this point, the system clock is set to 240 MHz. The Edit Params block provides access to the setup_demo_nco.m script that specifies MATLAB workspace variables to configure your design. The source blocks (Channel Counter and Valid Counter) provide channel and valid stimulus for the NCO block. These blocks provide the essential first stage of the DSP Builder advanced blockset interface protocol. The NCOSubSystem contains the NCO block. The remainder of the design example compares the NCO output to that of the Simulink Sine Wave and Cosine Wave blocks for reference. The two ChanView blocks deserialize the TDM output from the NCO.
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ChanCount = 4; ClockRate = 240.00; ClockMargin = 0.0; SampleRate = 60; Period = ClockRate / SampleRate; SampleTime = 1;
2. Check that the SampleTime variable is set to 1 (and comment out the alternative line for real world time):
SampleTime = 1; % SampleTime = 1/(ClockRate * 1e6); % uncomment this line to simulate the model with real world time
Set the sample time to 1 so that each step in your design example corresponds to a clock cycle in the hardware. This action allows easy debugging in the hardware, and communication with any hardware interfaces required. 3. Save the file and close the editor window. 1 If you change the sample time to the clock period (1/240e6), and run simulation for 20000/240e6 seconds, you receive a more architectural view of your design example.
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2. Double click on the NCO block to open its configuration parameter dialog box. This example produces four channels of complex output (one sine and one cosine) at a data rate of 60 MHz where the design specifies the frequency within 5 Hz by the following parameters:
The Output rate per channel determines the amount of folding the design uses. This parameter is set to the value of the SampleRate variable (which you can edit with the Edit Params block on the top-level design). The value is initially set to a value of 60 MSPS which creates outputs with single width wires. The Output data type is set to sfix(18). This setting produces sines and cosines with 22 bits of precision. The Output scaling value is set to 2^-17. This setting ensures that the design interprets the value as a sfix18_En17 (Q1.17) signed number and that Simulink reports the values inside the range (1.0 to 1.0). To generate symmetrical data do not use the extreme values. The Accumulator bit width is set to 24 and specifies the width of the memory-mapped accumulator bit width. This governs the precision with which you can control the NCO frequency. The Phase increment and inversion is a vector that represents the step in phase that each sample uses. This setting controls the frequencies that the design generates during simulation. The length of the vector determines how many channels of data generate. DSP Builder specifies the following vector value: [1:0.01:(1.0+(ChanCount-1)/100.0)] .* (2^24 * 0.051) + (0 * 2^24) + (0 * 2^25) The first part of this vector [1:0.01:(1.0+(ChanCount-1)/100.0)] .* (2^24 * 0.051) specifies the values 1.0e+005 * [8.5564 8.6419 8.7275 8.8131] of the phase increments for four channels. The following equation defines this frequency: Frequency = (Output Rate) * (Phase Increment Value) / (2(Accumulator Bit Width)) Therefore, the phase increment values produce a set of frequencies in MHz: [3.06 3.0906 3.1212 3.1518]. The value of the Accumulator bit width parameter in this example is set to 24. Hence, expect the binary format of the phase increment values in 26 binary digits as follows: 00 00 00 00 0000 0000 0000 0000 1101 1101 1101 1101 0000 0010 0101 0111 1110 1111 0001 0010 0101 1100 0010 1001 0110 0010 1111 1011
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The lower 24 bits specify the frequencies for the four channels. The top two bits control the inversion of sine (26th bit) and cosine (25th bit) respectively.
The second part of the phase increment and inversion vector, (0 * 2^24), manipulates the 25th bit of the values. When you specify (0 * 2^24), a 0 is set to the 25th bit. However, if you change it to (1 * 2^24), DSP Builder produces a 1 at the 25th bit, as the following bit pattern shows, indicating that the cosine wave is inverted: 01 01 01 01 0000 0000 0000 0000 1101 1101 1101 1101 0000 0010 0101 0111 1110 1111 0001 0010 0101 1100 0010 1001 0110 0010 1111 1011
The third part of the phase increment and inversion vector, (0 * 2^25), manipulates the 26th bit of the phase increment and inversion values. When you specify (0 * 2^25), a 0 is set to the 26th bit. However, if you change it to (1 * 2^25), DSP Bu idler produces a 1 at the 26th bit, indicating that an inverted sine wave. The following example demonstrates the case when both the sine and cosine waves are inverted: 11 11 11 11 0000 0000 0000 0000 1101 1101 1101 1101 0000 0010 0101 0111 1110 1111 0001 0010 0101 1100 0010 1001 0110 0010 1111 1011
The following example demonstrates the case when only the sine wave is inverted: 10 10 10 10 0000 0000 0000 0000 1101 1101 1101 1101 0000 0010 0101 0111 1110 1111 0001 0010 0101 1100 0010 1001 0110 0010 1111 1011
The top two bits (the 25th bit and 26th bit) change the binary bit patterns of the phase increment and inversion parameter, but they do not alter the frequencies of the generated sinusoidal signals. Figure 33 shows the frequency of the sinusoidal waves for the first channel. DSP Builder ignores any values in bits higher than the 26th bit.
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Figure 34, Figure 35, Figure 36, and Figure 37 show how the sine and cosine waves appear in the Simulink scopes after DSP Builder inverts them.
Figure 34. Neither Inverted: [1:0.01:(1.0+(ChanCount-1)/100.0)] .* (2^24 * 0.051) + (0 * 2^24) + (0 * 2^25)
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The Phase increment and inversion memory map value controls where in the memory-mapped space DSP Builder maps the NCO registers. This value is set to 0. The Read/Write mode controls access to the memory-mapped registers. This option is set to Read/Write. For more information about the NCO parameters, refer to the description of the NCO block in the DSP Builder Advanced Blockset Libraries section in volume 3 of the DSP Builder Handbook.
3. Click on the Results tab to display the results for your parameters, which shows the worst case SFDR based on the width in bits. Measured values may be significantly better than this, and you should perform further analysis. The accumulator precision shows for the specified accumulator width in bits. The actual frequencies that the initial phase increment values imply show as around 3 MHz for each channel. DSP Builder shows the number of output wires (width of output vector or outputs per cycle).
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You can specify the root to this directory as an absolute path name or as a relative path name. If you specify a relative path name (such as ../rtl), DSP Bu idler creates the directory structure relative to the MATLAB current directory. Table 31 lists the generated files for the NCO design example.
Table 31. Generated Files for the NCO Design Example File rtl directory demo_nco.xml demo_nco_entity.xml An XML file that describes the attributes of your design example. An XML file that describes the boundaries of the system that Signal Compiler uses in designs that combine blocks from the standard and advanced blocksets. Description
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Table 31. Generated Files for the NCO Design Example File rtl\demo_nco subdirectory <block name>.xml An XML file containing information about each block in the advanced blockset, which translates into HTML on demand for display in the MATLAB Help viewer. The top-level testbench file. It may contain non-synthesizable blocks, and may also contain empty black boxes for Simulink blocks that are not fully supported. This script loads the VHDL files in this subdirectory and in the subsystem hierarchy below it into the ModelSim project. This script compiles the VHDL files in this subdirectory and in the subsystem hierarchy below it into the ModelSim project. This script loads the VHDL files in this subdirectory and in the subsystem hierarchy below it into the Quartus II project. This file contains all the assignments and other information to process the demo_nco design example in the Quartus II software. The file includes a reference to the .qip file in the NCO subsystem. DSP Builder generates a VHDL file for each component in your model. An XML file that describes the boundaries of the subsystem as a block box (for Signal Compiler in designs that combine blocks from the standard and advanced blocksets). An XML file that describes the attributes of the NCOSubsystem. Stimulus files for ModelSim. Helper function that ensures a path name is read correctly in the Quartus II software. Helper function that ensures a path name is read correctly in ModelSim. Description
demo_nco.vhd
NCOSubsystem.xml *.stm safe_path.vhd safe_path_msim.vhd rtl\demo_nco\NCOSubsystem subdirectory Device.xml demo_nco_NCOSubsystem.vhd demo_nco_NCOSubsystem_NCO.vhd demo_nco_NCOSubsystem_ConstantP.vhd demo_nco_NCOSubsystem_ConstantS.vhd demo_nco_NCOSubsystem_NCO_atb.do demo_nco_NCOSubsystem_NCO_atb.vhd
An XML files containing information about the Device block, which translates into HTML on demand for display in the MATLAB Help viewer. The VHDL file for the subsystem. A VHDL file that describes the NCO component. A VHDL file that describes the ConstantP component. A VHDL file that describes the ConstantS component. Script that loads the Subsystem automatic testbench into ModelSim. A VHDL file for the automatic testbench.
demo_nco_NCOSubsystem_NCO_atb.wav.do Script that loads signals for the NCO subsystem automatic testbench into ModelSim. demo_nco_NCOSubsystem_NCO_stm.vhd demo_nco_NCOSubsystem_wysiwyg.vhd NCO.xml A VHDL stimulus file. A VHDL synthesis information file. An XML file containing information about the NCO block, which DSP Builder translates into HTML on demand for display in the MATLAB Help viewer. This script loads the VHDL files in this subdirectory into the ModelSim project.
NCOSubsystem.add.do
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Table 31. Generated Files for the NCO Design Example File NCOSubsystem.add.tcl NCOSubsystem.compile.do NCOSubsystem.qip NCOSubsystem.sdc NCOSubsystem.tcl NCOSubsystem_hw.tcl Description This script loads the VHDL files in this subdirectory into the Quartus II project. This script compiles the VHDL files in this subdirectory in the ModelSim project. This file contains all the assignments and other information the design requires to process the NCO subsystem in the Quartus II software. Design constraint file for TimeQuest timing analyzer support. You can use this Tcl script to setup a Quartus II project. A Tcl script that loads the generated hardware into SOPC Builder.
rtl\demo_nco\NCOSubsystem\NCO subdirectory *.hex *.stm These are Intel format .hex files that initialize the RAM blocks in your design for either simulation or synthesis. Generated stimulus files for ModelSim.
After your design loads, you can compile your design by clicking Start Compilation on the Processing menu.
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For these parameters, the Fitter Summary report shows that the Quartus II software specifies a small device (Figure 39).
Figure 39. Quartus II Compilation Fitter Summary for the NCO Design Example
The NCO circuit naturally compiles to a high clock frequency as the TimeQuest Timing Analyzer, Slow Model, Fmax Summary report shows (Figure 310).
Figure 310. Quartus II Timing for the NCO Design Example
For more full timing information, you can click TimeQuest Timing Analyzer on the Tools menu to access a more detailed timing report.
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2. In the Create New System dialog box, enter nios32 as your System Name, select VHDL for the target HDL and click OK. 3. In SOPC Builder, click Options on the Tools menu and select IP Search Path. Click Add and browse to the NCOSubsystem directory. 4. Click Finish. 5. On the File menu, click Refresh Component List. The NCOSubsystem should now appear in the SOPC Builder System Contents tab under Altera DSP Builder Advanced. 6. Click the System Contents tab in SOPC Builder and expand Memories and Memory Controllers. Expand On-Chip and double-click On Chip Memory (RAM or ROM). Click Finish in the MegaWizard interface to add an on-chip RAM component with default parameters. 7. Double-click the Nios II Processor module in the System Contents tab. Set the reset and exception vectors to use onchip_mem in the MegaWizard interface and click Finish to add the processor to your system with all other parameters set to their default values. 8. Double-click NCOSubsystem to include it in your Nios II system. (Figure 311).
Figure 311. Nios II System including NCOSubsystem in SOPC Builder
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If you add the memory device, Nios II processor, and DSP Builder advanced subsystem in this order, you should not need to set a base address. However, you can click Auto-Assign Base Addresses on the System menu to automatically add a base address if necessary.
9. Click Generate to complete your SOPC Builder system. Progress messages issue in the System Generation tab ending with the message:
System generation was successful
Use the standard Nios II embedded processor design flow, to design the rest of your Nios II embedded processor system. f For information about SOPC Builder and the Nios II processor, refer to the Quartus II Help.
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Running your design example again shows similar behavior as before, except with different frequencies. At this point, it is worth looking at the raw signals emerging from the NCO block (Figure 313).
Figure 313. Signals Output from the NCO Block
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sin and cos. These traces show the sines and cosines for the four wires emerging from the NCO. These traces display in four different colors and all differ because each channel has a different frequency. The valid signal is constantly high indicating that each value is valid. The channel output is a count running from 0 to 5 and repeating, which indicates the TDM slot that the data refers to.
You can see how DSP Builder represents 24 channels of sine on the sin output. Wire 0 of the 4 element vector has channels 0 to 5, wire 1 has channels 6 to 11, and so on. On each of those wires, the channels are in the order 0, 1, 2, 3, 4, 5 and you can use the channel value to determine which cycle to examine. For example, if you want to locate channel 14, it is on the third element of the vector and corresponds to channel indicator 2. To find the data for a particular channel, you must sample the correct element on the correct phase of the clock that the channel indicates, which the ChanView block performs. You can code up an equivalent function in RTL for interfacing, or ModelPrim library blocks, or in MATLAB m-code for analyzing captured data. DSP Builder preserves this mapping into the hardware when you can see it in simulation and in the device.
2. If you want the result to stay in the range (1.0 to 1.0), change the Output scaling value to 2^-21. 3. Close the Function Block Parameters dialog box and save your design. 4. Rerun the simulation to see the improved noise margins (Figure 314).
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4. Drag and drop a ChannelIn and a ChannelOut block into your design example (the Fibonacci window). 5. Drag and drop two SampleDelay blocks into your model. 6. Select both of the SampleDelay blocks and point to Format on the popup menu and click Flip Block to reverse the direction of the blocks. 7. Drag and drop Add and Mux blocks from the ModelPrim library into your model. 8. Connect the blocks. 9. Double-click on the second SampleDelay block (SampleDelay1) to display the Function Block Parameters dialog box and change the Number of delays parameter to 2. 10. Double-click on the Add block to display the Function Block Parameters dialog box and set the parameters (Table 41).
Table 41. Parameters for the Add Block Parameter Output data type mode Output data type Output scaling value Number of inputs Value Specify via dialog ufix(120) 2^-0 2
Specify the data type because this design contains loops and DSP Builder cannot determine the type if one of the inherit data options is set.
11. Complete your design by dragging and dropping a SynthesisInfo block from the ModelPrim library.
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4. Drag and drop a Device block from the DSP Builder advanced blockset Base Blocks library into your design example (Figure 41).
Figure 41. Updated Fibonacci Subsystem
6. Drag and drop a Scope block from the Simulink Sinks library into your model. 7. Double-click on the Scope block, open the Scope Parameters dialog box and set the Number of axes to 3.
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9. Complete the top-level diagram by dragging and dropping the Control, Signals, Run ModelSim and, Run Quartus II, and Signals blocks from the DSP Builder advanced blockset Base Blocks library. 10. Double-click on the Signals block and change the Clock Margin to 260. 1 f For this tutorial, you can use the Control block with its default settings. For more information about the Control and Signals block, refer to the System Tutorial on page 51, or to their block descriptions in the DSP Builder Advanced Blockset Libraries section in volume 3 of the DSP Builder Handbook.
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The sequence on the fib output starts at 0, and increments to 1 when q_v and q_c are both high at time 21.0. It then follows the expected Fibonacci sequence incrementing through 0, 1, 1, 2, 3, 5, 8, 13 and 21 to 34 at time 30.0. 1 You can verify that the fib output continues to increment according to the Fibonacci sequence by simulating for longer time periods.
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5. Simulate the design in Simulink. The Scope block output (when you use Autoscale) reveals that the real data and imaginary components now contain the Fibonacci sequence multiplied by the expected constant factors.
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Table 43. Generated Files for the Fibonacci Design File rtl directory fibonacci.xml fibonacci_entity.xml rtl\fibonacci subdirectory <block name>.xml fibonacci.vhd fibonacci.add.do fibonacci.compile.do fibonacci.add.tcl fibonacci.qip An XML file containing information about each block in the advanced blockset, which translates into HTML on demand for display in the MATLAB Help viewer. The top-level testbench file. It may contain non-synthesizable blocks, and empty black-box designs for Simulink blocks that are not fully supported. This script loads the VHDL files in this subdirectory and in the subsystem hierarchy below it into the ModelSim project. This script compiles the VHDL files in this subdirectory and in the subsystem hierarchy below it into the ModelSim project. This script loads the VHDL files in this subdirectory and in the subsystem hierarchy below it into the Quartus II project. This file contains all the assignments and other information DSP Builder requires to process the Fibonacci design example in the Quartus II software. The file includes a reference to the .qip file in the subsystem hierarchy. DSP Builder generates a VHDL file for each component in your model. An XML file that describes the boundaries of the subsystem as a block-box design (for Signal Compiler in designs that combine blocks from the standard and advanced blocksets). An XML file that describes the attributes of the subsystem. Stimulus files. Helper function that ensures a pathname is read correctly in the Quartus II software. Helper function that ensures a pathname is read correctly in ModelSim. An XML file that describes the attributes of your model. An XML file that describes the boundaries of the system (for Signal Compiler in designs that combine blocks from the standard and advanced blocksets). Description
rtl\fibonacci\Subsystem subdirectory *.stm Device.xml *.vhd fibonacci_Subsystem_atb.do Subsystem.add.tcl Subsystem.qip Subsystem.sdc Subsystem.tcl Subsystem_hw.tcl Generated stimulus files for ModelSim. An XML files containing information about the Device block, which translates into HTML on demand for display in the MATLAB Help viewer. The VHDL file for the subsystem. It generates as plain VHDL text that you can use in any design flow. Script that loads the subsystem automatic testbench into ModelSim. This script loads the VHDL files in this subdirectory into the Quartus II project. This file contains all the assignments and other information to process the subsystem in the Quartus II software. Design constraint file for TimeQuest timing analyzer support. You can use this Tcl script to setup a Quartus II project. A Tcl script that loads the generated hardware into SOPC Builder.
fibonacci_Subsystem_atb.wav.do Script that loads signals for the subsystem automatic testbench into ModelSim.
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Design Recommendations Using Vectors Implementing Flow Control Building System Components with Avalon-ST Interface Blocks Using ModelPrim Subsystems
Design Recommendations
This topic discusses various recommendations.
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Essential Recommendations
Before using ModelPrim blocks, follow these guidelines: 1. Ensure the primitive subsystem contain a SynthesisInfo block with style set to Scheduled. 2. Ensure the primitive subsystems do not contain ModelIP blocks. 3. Route all subsystem inputs with associated valid and channel signals that are to be scheduled together through the same ChannelIn blocks immediately following the subsystem inputs. Route any other subsystem inputs through GPIn blocks. 4. Route all subsystem outputs with associated valid and channel signals that are to be scheduled together through the same ChannelOut blocks immediately before the subsystem outputs. Route any other subsystem outputs through GPOut blocks. 5. Use Convert blocks to change data type preserving real-world value. 6. Use Specify via dialog options to change data type to preserve bit pattern, or to fix a data type. 7. Ensure the valid signal is a scalar boolean or ufix(1). 8. Ensure the channel signal is a scalar uint(8).
Testbench Recommendations
Before using testbenches, follow these guidelines: 1. Turn on Create Automatic Testbenches and Coverage in Testbenches on the Control block. DSP Builder performs stimulus capture for testbenches on the inputs and outputs of ModelIP blocks and by ChannelIn, ChannelOut, GPIn, and GPOut blocks. 2. Run all testbenches with the following command:
run_all_atbs(<model name>, <run simulation first? 1 : 0>, <run Quartus II software afterwards ? 1 : 0)
3. Run an individual subsystem or ModelIP block testbench with the following command:
run_modelsim_atb(<path to subsystem> or <'gcb' if currently selected>)
4. Run the single device-level testbench from the Run ModelSim block. 5. Examine the generated resource summariesafter simulation, right-click and select Help on the ModelIP block for ModelIP blocks, or on the SynthesisInfo block for primitive subsystems, or on the Control block for a top-level design summary.
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2. Set workspace variables in initialization scripts. Execute them on the model's PreLoadFnc and InitFcn callbacks, such that the design opens with parameters set, and the next simulation reflects any changes in the next simulation, without explicitly running the script or opening and closing the model. 3. Call your main initialization script for the model setup_<model name>, and as a shortcut to editing it include the Edit Params block in the top level design. 4. Build a testbench that is parameterizable with the Channelizer block, which varies correctly with system parameters such as sample rate, clock rate, and number of channels. 5. Use the model's StopFnc call back to run any analysis scripts automatically. 6. Build systems that use the valid and channel signals for control and synchronization, not latency matching. For example, capture valid output in FIFO buffers to manage dataflow. 7. Build up and use your own libraries of reusable components. 8. Keep block and subsystem names short, but descriptive. Avoid names with special characters, slashes, or that begin with numbers. 9. Use LocalThreshold blocks, with the top-level thresholds, for localized tradeoffs or pipelining.
Verification Recommendations
Follow theses guidelines for verification: 1. The output only matches the hardware when valid is high. 2. run_modelsim_atb displays the command it executes. You can cut and paste this command into an open ModelSim UI in the same directory and run manually. With this command you can analyze the behavior of particular subsystems in detail, and can force simulation to continue past errors if necessary. 3. If using FIFO buffers within multiple feedback loops, while the data throughput and frequency of invalid cycles is the same, their distribution over a frame of data many vary (due to the final distribution of delays around the loop). If you find a mismatch, step past errors as step 2 describes.
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Using Vectors
Using vectors with ModelPrim blocks has the following advantages:
Makes the design more parameterizable Speeds up simulation Simplifies the schematic Avoids cut-and-paste duplication in many instances Enables flexible designs that scale with input vector width
This section describes using vectors for building more parameterizable design components. The following three design examples demonstrate using vectors:
Matrix Initialization of Vector Memories Matrix Initialization of LUT Vector Initialization of Sample Delay
Expand Scalar (ExpandScalar) Vector Multiplexer (VectorMux) Tapped Delay Line (TappedDelayLine)
Number of input dimensions1 only Index mode: zero-based or one-based Index options Select all
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The Simulink Selector block does not support the following features:
For more information on this Simulink block, refer to Simulink help. In hardware, this block synthesizes to wiring.
Zero-Latency Latch (latch_0L) on page 23 Single-Cycle Latency Latch (latch_1L) on page 24 Reset-Priority Latch (SRlatch_PS) on page 24 Set-Priority Latch (SRlatch) on page 24
Some of these blocks use the Simulink Data Type Prop Duplicate block, which takes the data type of a reference signal ref and back propagates it to another signal prop. Use this feature to match data types without forcing an explicit type that you can use in other areas of your design.
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There is a three cycle latency between the first write and valid going high. The q output has a similar latency in response to writes. The latency in response to read acknowledgements is only one cycle for all output ports. The valid out goes low in response to the first read, even though the design writes two items to the FIFO buffer. The second write is not older than three cycles when the read occurs. With the fill threshold set to a low value, the t output can go high even though the v out is still zero. Also, the q output stays at the last value read when valid goes low in response to a read. Problems can occur when you use no feedback on the read line, or if you take the feedback from the t output instead with fill threshold set to a very low value (< 3). A situation may arise where a read acknowledgement is received shortly following a write but before the valid output goes high. In this situation, the internal state of the FIFO buffer does not recover for many cycles. Instead of attempting to reproduce this behavior, Simulink issues a warning when a read acknowledgement is received while valid output is zero. This intermediate state between the first write to an empty FIFO buffer and the valid going high, highlights that the input to output latency across the FIFO buffer is different in this case. This situation is the only time when the FIFO buffer behaves with a latency greater than one cycle. With other primitive blocks, which have consistent constant latency across each input to output path, you never have to consider these intermediate states. You can mitigate this issue by taking care when using the FIFO buffer. The model needs to ensure that the read is never high when valid is low using the simple feedback. If you derive the read input from the t output, ensure that you use a sufficiently high threshold.
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Because of differences in latency across different pairs of portsfrom w to v is three cycles, from r to t is one cycle, from w to t is one cycleyou can set fill threshold to a low number (<3) and arrive at a state where output t is high and output v is low. If this situation arises, do not send a read acknowledgement signal to the FIFO buffer. Ensure that when the v output is low, the r input is also low. A warning appears in the MATLAB command window if you ever violate this rule. If you derive the read acknowledgement signal with a feedback from the t output, ensure that the fill threshold is set to a sufficiently high number (3 or above). Similarly for the f output and the full period. If you supply vector data to the d input, you see vector data on the q output. DSP Builder does not support vector signals on the w or r inputs, as the behavior is unspecified. The v, t, and f outputs are always scalar.
A single Loop block can implement an entire stack of nested loops. There are no wasted cycles when the loop is active but the count is not valid. The implementation cost is lower because there is no overhead for the token-passing scheme.
Loops may count either up or down. You may specify the initial value and the step, not just the limit value. The token-passing scheme allows the construction of control structures that are more sophisticated than just nesting rectangular loops.
When a stack of nested loops is the appropriate control structure (for example, matrix multiplication) use a single Loop block. When a more complex control structure is required, use multiple ForLoop blocks.
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Avalon-ST Output (AStOutput) on page 21 Avalon-ST Input (AStInput) on page 23 Avalon-ST Input FIFO Buffer (AStInputFIFO) on page 23
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Restrictions
You can place the Avalon-ST interface blocks in different levels of hierarchy. However, you should never place Simulink, ModelIP or primitive blocks between the interface and the device level ports. The Avalon-ST interface specification only allows a single data port per interface. Thus you may not add further data ports, or even using a vector through the interface and device-level port (which creates multiple data ports). To handle multiple data ports through a single Avalon-ST interface, pack them together into a single (not vector or bus) signal, then unpack on the other side of the interface. The maximum width for a data signal is 256 bits. Use the BitCombine and BitExtract blocks to pack and unpack.
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There are some configurations of input and output blocks, if accounting for latency at the inputs and outputs, which require latency correction of negative size, implying discarding the first few samples. Assume that multipliers need a delay three times the delay of adders. Any solution for latency correction requires a negative sized buffer on at least one of the I/O blocks. Discarding the first few samples is not possible in the discrete simulation that Simulink uses, but you can still do it for the stimulus files. When this occurs a warning message makes you aware that the Simulink model does not behave in a similar way to the hardware.
Common Problems
You may observe problems with the following areas:
Timed Feedback Loops Care must be taken with feedback loops generally, in particular in providing sufficient delay around the loop. Designs that have a cycle containing two adders with only a single sample delay are not sufficient. In automatically pipelining designs, DSP Builder creates a schedule of signals through the design. From internal timing models, DSP Builder calculates how fast certain components, such as wide adders, can run and how many pipelining stages they require to run at a specific clock frequency. DSP Builder must account for the required pipelining while not changing the order of the schedule. The single sample delay is not enough to pipeline the path through the two adders at the specific clock frequency. DSP Builder is not free to insert more pipelining, as it changes the algorithm, accumulating every n cycles, rather than every cycle. The scheduler detects this change and gives an appropriate error indicating how much more latency the loop requires for it to run at the specific clock rate. In multiple loops, this error may be hit a few times in a row as DSP Builder balances and resolves each loop.
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Loops, Clock Cycles and Data Cycles Never confuse clock cycles and data cycles in relation to feedback loops. For example, you may want to accumulate previous data from the same channel. The multichannel IIR filter design example (demo_iir) shows feedback accumulators processing multiple channels. In this example, consecutive data samples on any particular channel are 20 clock cycles apart. DSP Builder derives this number from clock rate and sample rate. The folded IIR filter design example (demo_iir_fold2) demonstrates one channel, at a low data rate. This design example implements a single-channel infinite impulse response (IIR) filter with a subsystem built from primitive blocks folded down to a serial implementation. The design of the IIR is the same as the IIR in the multichannel example, demo_iir. As the channel count is one, the lumped delays in the feedback loops are all one. If you run the design at full speed, there is a scheduling problem. With new data arriving every clock cycle, the lumped delay of one cycle is not enough to allow for pipelining around the loops. However, the data arrives at a much slower rate than the clock rate, in this example 32 times slower (the clock rate in the design is 320 MHz, and the sample rate is 10MHz), which gives 32 clock cycles between each sample. You can set the lumped delays to 32 cycles longthe gap between successive data sampleswhich is inefficient both in terms of register use and in underused multipliers and adders. Instead, use folding to schedule the data through a minimum set of fully used hardware. Set the SampleRate on both the ChannelIn and ChannelOut blocks to 10 MHz, to inform the synthesis for the primitive subsystem of the schedule of data through the design. Even thought the clock rate is 320 MHz, each data sample per channel is arriving only at 10 MHz. The RTL is folded downin multiplier useat the expense of extra logic for signal multiplexing and extra latency.
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Alternatively set the type with Specify via dialog on any other primitive. For example by using a zero-length sample delay. To reinterpret the bit pattern and also discard bits, if the type you specify with the Output data type is smaller that the natural (inherited) output type, DSP Builder discards the MSBs (most significant bits). Never set Specify via dialog to be bigger than the natural (inherited) bit pattern DSP Builder performs no zero-padding or sign extension, and the result may generate hardware errors due to signal width mismatches. Use the Convert block for any sign extension or zero padding. If you want to use sign extends and zero pads to reinterpret the bit pattern, you can combine these methods. To set a specific format so that DSP Builder can resolve types, for example, in feedback loops, set Specify via dialog on an existing primitive or insert a zero-cycle sample delay (which generates no hardware and just casts the type interpretation). To ensure the data type is equal to some other signal data type, force the data type propagation with a Simulink data type propagation block.
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CmpEQ CmpGE CmpLT CmpNE ComplexConjugate Lut Min Max Mult Mux SampleDelay Select Sub
To apply floating-point data type, select single or double in the Output data type drop-down box. The following blocks in the primitive library support common maths functions:
ACos ASin ATan Cos Divide Exp LdExp Log Reciprocal RecipSqRt Sin Tan
Most of these blocks have multiplier-based implementations and have a size typically about three to four times that of a corresponding floating-point multiply. 1 None of these blocks support fixed-point data types. You can use these blocks in fixed-point designs by converting from and to floating point either side of the block.
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Relatively large differences can still occur when subtracting numbers that are very close in value (such that after alignment of mantissas to equalize the exponent, the subtraction zeros out the first 6 to 16 most significant bits). You may introduce a deviation in the output of the Simulink model and the generated HDL, largely due to numerical round-off. You must understand the measuring of results against that produced with IEEE single precision computation in terms of this accuracy, and not in terms of absolute error. Given the generally higher precision of the internal floating point format that the generated HDL uses, the Simulink single precision answer may be more wrong in this case. Such numeric differences may be exaggerated, for example by the ill-conditioning of the matrix that forward and backward substitution uses. Here you can iterate and multiply the differences. For this example, use pivoting at the QR decomposition stage, which involves reordering matrix columns.
Internal Floating Point NumberSingle Precision In addition to IEEE754 that DSP Builder uses at the subsystem boundaries and memories, there are two internal single precision formats: a signed one for addition and subtraction, and another unsigned for multiplication and division. Both formats have a 32-bit mantissa followed by the 10-bit exponent (Table 46 and Table 47).
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Table 46. Signed Format for Addition and SubtractionSingle Precision Number Part Exponent Mantissa Bits 41:10 9:0
Table 47. Unsigned Format for Multiplication and DivisionSingle Precision Number Part Exponent Mantissa Bits 41:10 9:0
Also there are three flag bits for saturation (inf), zero, and not a number (NaN). Addition and Subtraction FormatSingle Precision For addition and subtraction operations, Table 413 shows the format on conversion from IEEE754 single precision.
Table 48. Addition and Subtraction Number FormatSingle Precision Number Part Mantissa Bits 44 43 42 41:37 36 35:13 12:10 Exponent 9:0 Sat Zip NaN SSSSS 1 Mantissa UUU Exponent Symbol
Table 49 shows the addition and subtraction word formats for single precision.
Table 49. Addition and Subtraction Word FormatsSingle Precision Minimum Positive (Subnormal) Value 2536 4.4 x 10162 Minimum Positive Normal Value 2510 2.98 x 10154 Maximum Representable Value (32226) x 2511 2.1 x 10155
The format is just fixed point, plus an exponent. To convert from IEEE, pad with sign and zeros. To convert back to IEEE is harder and requires detecting sign, using absolute values, counting leading zeros, shifting, and so on, which DSP Builder performs in the generated hardware. Adding numbers together is also simple, with word growth into the overflow bits. These four overflow bits (one is sign) allow for 16 unnormalized additions to feed into a single node without overflow. Underflow may happen more quickly, because of bit cancellation, but the effects of underflow are reduced by normalizing more often where necessary, which DSP Builder performs in the generated hardware.
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Multiplication and Division FormatSingle Precision The multiplier has a slightly different input number format. A fully normalized multiplier input format for the 32 bit mantissa is a signed number (Table 410).
Table 410. Multiplication and Division Number FormatSingle Precision Number Part Mantissa Bits 44 43 42 41 40 39:17 16:10 Exponent 9:0 Sat Zip NaN S 1 Mantissa UUUUUUU Exponent Symbol
Table 411 shows the multiplication and division word formats for single precision.
Table 411. Multiplication and Division Word FormatsSingle Precision Minimum Positive (Subnormal) Value 2540 Minimum Positive Normal Value 2510 Maximum Representable Value (2230) x 2511 1.34 x 10154
2.8 x
10163
2.98 x
10154
DSP Builder always normalizes the multiplier input to prevent overflow. If there is significant underflow in the part of the datapath feeding the multiplier, the number may be very small. If the other number is very small also, the multiplier may produce a zero output, as the new mantissa is expected in the top half of the multiplier output. In the internal format, the sign bit is part of the mantissa. The mantissa is a 32- or 36-bit signed number, with the entire mantissa (including the implied '1') rather than just the fractional part. The exponent follows the mantissa. In addition, two bits are always associated with every internal floating point number: a saturation signaling bit and a zero signaling bit. Rather than calculating an infinity or zero condition at every operation, the functions forward saturation and zero conditions that DSP Builder detects at the input of the datapath. DSP Builder combines these conditions with the conversion (cast) back to IEEE754 at the output of the datapath to determine special conditions. Double Precision Word Formats Generally, the double precision word formats are analogous to the single precision word formats. In IEEE754 format, as Table 412 shows, the sign bit is in the most significant bit, followed by an 11-bit exponent, followed by the 52-bit fractional part of the mantissa.
Table 412. IEEE754 Number FormatSingle Precision Number Part Sign Exponent Mantissa Bits 63 62:52 51:0 S Exponent Mantissa Symbol
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Internal Floating Point NumberDouble Precision In addition to IEEE754 that DSP Builder uses at the subsystem boundaries and memories, there are two internal double precision formats: a signed one for addition and subtraction, and another unsigned for multiplication and division. In the signed format, the 64-bit signed mantissa is followed by the 13-bit exponent; the unsigned format has the 54-bit mantissa followed by the 13-bit exponent (Table 414 and Table 415).
Table 414. Signed Format for Addition and SubtractionDouble Precision Number Part Exponent Mantissa Bits 76:13 12:0
Table 415. Unsigned Format for Multiplication and DivisionDouble Precision Number Part Exponent Mantissa Bits 66:13 12:0
The saturation and zero signaling bits operate in the identical way to the single precision case. Also there are three flag bits for saturation (Inf), zero, and not a number (NaN). Addition and Subtraction MantissaDouble Precision DSP Builder uses a signed 64-bit mantissa internally. The mantissa from the IEEE format becomes part of the sfix64_En58 signed fractional number (Table 416).
Table 416. Addition and Subtraction Number FormatDouble Precision Number Part Mantissa Bits 79 78 77 76:72 71 70:19 18:13 Exponent 12:0 Sat Zip NaN SSSSS 1 Mantissa UUU Exponent Symbol
Table 417 shows the addition and subtraction word formats for double precision.
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Table 417. Addition and Subtraction Word FormatsDouble Precision Minimum Positive (Subnormal) Value 24152 1.3 x 101250 Minimum Positive Normal Value 24094 3.8 x 101233 Maximum Representable Value (32258) x 24095 1.7 x 101234
As with the single precision mantissa, there are four overflow bits (four additional integer bits compared to IEEE) so that 16 additions can feed into any node without overflow. There are six underflow (guard) bits. Multiplication, Division, and Function MantissasDouble Precision The multiplier and divider have the same format, which is different from the signed mantissa (Table 418).
Table 418. Multiplication and Division Number FormatDouble Precision Number Part Mantissa Bits 69 68 67 66 65 64:13 Exponent 12:0 Sat Zip NaN S 1 Mantissa Exponent Symbol
Table 419 shows the multiplication and division word formats for double precision.
Table 419. Multiplication and Division Word FormatsDouble Precision Minimum Positive (Subnormal) Value 2
4146
8.5 x 10
1249
3.8 x 10
1233
The sign bit is packed with the mantissa, but DSP Builder performs the multiplication or division operation on an unsigned 54-bit mantissa. As with single precision, the function library mantissa is the same as the division mantissa, except that some functions only have a valid positive output. The mantissa is 54-bits wide, consisting of a leading "01" and a 52-bit fractional part. The exponent is 13-bits wide, and is signed. As with the single precision internal format, DSP Builder uses the additional width for local overflow and underflow. The exponent can exceed 2,046 locally and be less than 0 locally before normalization. As with the IEEE754 format, the exponent is offset, where a value of 1,023 denotes 1 (20), and 0 denotes (21023). DSP Builder does not support denormalized numbers, but in cases where a node temporarily is less than (21023) can be accommodated if the node increases to (2-1022) before the next conversion to a IEEE754 number (an output).
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Memory The IEEE format is propagated though to memory, which always stores data in IEEE, even in feedback loops.
Multiplier Multipliers can take IEEE format and can generate multiplier format.
Adder
IEEE
Output
Special Considerations
DSP Builder often folds down algorithms to reduce the total resources, while maintaining the required data throughput. For example, most folded algorithm implementations assume single-cycle accumulators, which permit DSP Builder to perform partial calculations in adjacent clock cycles, and for DSP Builder to write the control in a natural way. However, to meet high fMAX, floating point accumulators are at least 6 cycles for single precision, and 10 cycles for double precision. A delay-line adder tree is a typical structure in DSP designs. But with the latency required for floating point, it may use large resources, and add latency to the overall calculation. If you perform calculations out-of-order, you can often build a more hardware efficient implementation. When designing with floating-point data in DSP Builder, build simple designs that are still efficient. The following sections describe structures that you can use for efficient floating-point design, and algorithmic transformations to build them automatically: These techniques apply to simple designs, and to more complex linear algebra fucntions such as Cholesky and QR decomposition. You may also apply these techniques to fixed-point designs.
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Flow Control DSP Builder uses FIFO buffers to provide self-timed control. Rather than either relying on cycle counting or on state machines, FIFO buffers offer simple controlled access to memories. The aim is to have the floating-point arithmetic running as fast as it can. Rather than issuing a command to 'start processing', then waiting for the latency of the calculation before using the result, have the arithmetic unit running continually in advance. DSP Builder continually pushes results onto the back of the FIFO buffer queue and pulls them from the front by the downstream process. If this queue becomes too big (the FIFO buffer is getting full), ensure you feed back to stall the processing for a while. You aim not to lose any results, while still storing any results currently in midcalculation. Pipelining cannot add extra latency around loops, only balance and redistribute existing algorithmic latency. Therefore, although you need not care about the latency around the loop, you must specify sufficient delay around the loop in the design so that the pipelining solver can redistribute the latency to meet timing without needing to add further delay. In the Mandelbrot example, examine the loop-slack sample delays in each loop.
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number of clock-cycles before you need them, as you must change them each time you retarget a device, or change target clock rate. Instead, DSP Builder calculates the points quickly from the start, catches them in a FIFO buffer. If the FIFO buffer starts to get fulla sufficient number of cycles ahead of fullDSP Builder stops the calculation upstream without loss of data. This flow is self regulating that mitigates latency while remaining flexible. Avoid inefficienies by designing algorithm implementation around the latency and availability of partial results. Data dependencies in processing can stall processing. The design has the following features:
The design uses the FinishedThisPoint signal the valid signal. Although the system constantly produces data on the output, it marks the data as valid only when the design finishes a point. Downstream components can then just process valid data, just as the enabled subsystem in the design testbench captures and plot the valid points. In both feedback loops, you must allow sufficient delay for the scheduler to redistribute as pipelining. In feed-forward paths you can add pipelining without changing the algorithmonly the timing of the algorithm. But in feedback loops, inserting a delay can alter the meaning of an algorithm. For example, adding N cycles of delay to an accumulator loop increments N different numbers, each incrementing every N clock cycles. In loops, the design must give the scheduler in charge of pipelining for timing closure enough slack in the loop to be able to redistribute this delay to meet timing, while not changing the total latency around the loop, and thus ensuring the function of the algorithm is unaltered. Such slack delays are in the top-level design of the synthesizable design in the feedback loop controlling the generation of new points, and in the FeedBackFIFO subsystem controlling the main iteration calculation. The FIFO buffers operate in show-ahead modethey display the next value to be read. The read signal is a read acknowledgement, which reads the output value, discards it, and shows the next signal. DSP Builder uses multiple FIFO buffers with the same control, which are full and give a valid output at the same time. Thus we only need the output control signals from one of the FIFO buffers and can ignore the corresponding signals from the other FIFO buffers.
Floating Point Matrix Multiply A matrix multiplication must multiply row and column dot product for each output element. For 88 matrices A and B:
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AB ij =
Aik Bkj
k=1
You may accumulate the adjacent partial results, or build adder trees, without considering any latency. However, to implement with a smaller dot product, folding to use a smaller number of multipliers rather than performing everything in parallel, split up the loop over k into smaller chunks. Then reorder the calculations to avoid adjacent accumulations. A traditional implementation of a matrix multiply design is structured around a delay line and an adder tree: A11B11 +A12B21 +A13B31 and so on.
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The length and size grow as folding size (typically 8 to 12) Uses adder trees of 7 to 10 adders that are only used once every 10 cycles. Each matrix size needs different length, so you must provide for the worst case
A better implementation is to use FIFO buffers to provide self-timed control. New data is accumulated when both FIFO buffers have data. This implementation has the following advantages:
Runs as fast as possible Is not sensitive to latency of dot product on devices or fMAX Is not sensitive to matrix size (hardware just stalls for small N) Can be responsive to back pressure, which stops FIFO buffers emptying and full feedback to control
Generated Testbenches
The automatic testbench for an entity under test consists of the following files:
<name>.vhdthe HDL that is generated as part of the design (regardless of automatic testbenches) <name>_stm.vhdan HDL file that reads in data files of captured Simulink simulation inputs and outputs on <name> <name>_atb.vhda wrapper HDL file that performs the following actions:
Declares <name>_stm and <name> as components Wires the input stimuli read by <name>_atb to the inputs of <name> and the output stimuli and the outputs of <name> to a validation process that checks the captured Simulink data Channel matches the VHDL simulation of <name> for all cycles where valid is high Checks that the valid signals match
<input>/<output>.stmthe captured Simulink data that the ChannelIn, ChannelOut, GPIn, GPout and ModelIP blocks write
Each block writes a single stimulus file capturing all the signals through it writing them in columns as doubles with one row for each timestep. The device-level testbenches use these same stimulus files, following connections from device-level ports to where the signals are captured. Device-level testbenches are therefore restricted to cases where the device-level ports are simply connected to stimulus capturing blocks.
5. System Tutorial
The top-level design example (Figure 51 on page 52) shows the testbench components when the design is in the DDCChip subsystem. To build the design, follow these steps: 1. Use fixed-point types in Simulink to model the design. 2. Simulate the design example in Simulink. 3. Simulate the generated RTL in ModelSim. 4. Use the Quartus II software to synthesize and fit the RTL.
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Figure 51 shows the entire design for the DDC (the testbench) and Figure 52 (the DDCChip subsystem) shows just how few components you require to build a complex, production ready system.
Figure 51. Testbench for the DDC Design
The top-level testbench includes integration blocks for ModelSim and the Quartus II software, Control and Signals blocks, and some Simulink blocks to generate source signals and visualize the output. The full power of the Simulink blocksets is available for your design.
Figure 52. DDCChip Subsystem
The DDCChip subsystem block contains the NCO and mixer, decimate by 16 CIC filter, and two decimate by 4 FIR odd-symmetric filters, one with length 21, the other length with 63. These blocks form the lowest level of the design hierarchy. The other blocks in this subsystem perform a range of rounding and saturation functions. They also allow dynamic scaling. There is also a Device block that specifies the target FPGA.
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Signals Block
Provide a relationship between the sample rates and the system clock, to tell the synthesis engines how much folding or time sharing to perform. Increasing the system clock permits more folding, and therefore typically results in more resource sharing, and a smaller design. You also need a system clock rate so that the synthesis engines know how much to pipeline the logic. For example, by considering the device and speed grade, the synthesis tool can calculate the maximum length that an adder can have. If the design exceeds this length, it pipelines the adder and adjusts the whole pipeline to compensate. This adjustment typically results in a small increase in logic size, which is usually more than compensated for by the decrease in logic size through increased folding. The Signals block specifies the clock and reset names, with the system clock frequency. The bus clock or FPGA internal clock for the memory-mapped interfaces can be run at a lower clock frequency. This lets the design move the low-speed operations such as coefficient update completely off the critical path. 1 To specify the clock frequency, clock margin, and bus clock frequency values in this design, use the MATLAB workspace variables ClockRate and ClockMargin, which you can edit by double-clicking on the Edit Params block.
Control Block
The Control block controls the whole DSP Builder advanced blockset environment. It examines every block in the system, controls the synthesis flow, and writes out all RTL and scripts. A single control block must be present at the top-level of the model. f For full details of each parameter, refer to their block descriptions in the DSP Builder Advanced Blockset Libraries section in volume 3 of the DSP Builder Handbook. In this design, hardware generation creates RTL. DSP Builder places the RTL and associated scripts in the directory ../rtl, which is a relative path based on the current MATLAB directory. DSP Builder creates automatic self-checking testbenches, which saves the data that a Simulink simulation captures to build testbench stimulus for each block in your design. DSP Builder generates scripts to run these simulations. Many memory-mapped registers in the design exist such as filter coefficients and control registers for gains. You can access these registers through a memory port that DSP Builder automatically creates at the top-level of your design. DSP Bu idler creates all address decode and data multiplexing logic automatically. DSP Builder generates a memory map in XML and HTML that you can use to understand the design. To access this memory map, click Help in the Control Block Parameters dialog box after your design simulates. The address and data widths are set to 8 and 32 in the design. The threshold values control the hardware generation. They control the trade-offs between hardware resources, such as hard DSP blocks or soft LE implementations of multipliers. You can perform resource balancing for your particular design needs with a few top-level controls.
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Source Blocks
The Simulink environment enables you to create any required input data for your design. In the DDC design, use manual switches to select sine wave or random noise generators. DSP Builder encodes a simple six-cycle sine wave as a table in a Repeating Sequence Stair block from the Simulink Sources library. This sine wave is set to a frequency that is close to the carrier frequencies that you specify in the NCOs, allowing you to see the filter lineup decoding some signals. DSP Builder creates VHDL for each block as part of the testbench RTL.
Sink Blocks
Simulink Sink library blocks display the results of the DDC simulation. The Scope block displays the raw output from the DDC design. The design has TDM outputs and all the data shows as data, valid and channel signals. At each clock cycle, the value on the data wire either carries a genuine data output, or data that you can safely discard. The valid signal differentiates between these two cases. If the data is valid, the channel wire identifies the channel where the data belongs. Thus, you can use the valid and channel wires to filter the data. The ChanView block automates this task and decodes 16 channels of data to output channels 0 and 15. The block decimates these channels by the same rate as the whole filter line up and passes to a spectrum scope block (OutSpectrum) that examines the behavior in the frequency domain.
The Edit Params blocks allows you to edit the script setup_demo_ddc.m, which sets up the MATLAB variables that configure your model. Use the MATLAB design example properties callback mechanism to call this script. 1 The PreloadFCn callback uses this script to setup the parameters when your design example opens and the InitFcn callback re-initializes your design example to take account of any changes when the simulation starts.
The Run ModelSim block starts ModelSim with a script generated during the hardware generation process, and simulates the testbench and design contents. This process compiles all the VHDL files, adds signals to the ModelSim Wave window and simulates for the same time as the Simulink design example was run. The Run Quartus II block opens the Quartus II software and adds all your design files to a project. You can then compile your design for your target device and clock rate with the Quartus II software.
You can edit the parameters in the setup_demo_ddc.m script by double-clicking on the Edit Params block to open the script in the MATLAB text editor. The script sets up MATLAB workspace variables. The SampleRate variable is set to 61.44 MHz, which typical of a CDMA system, and represents a quarter of the system clock rate that the FPGA runs at. You can use the feature to TDM four signals onto any given wire.
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DDCChip Subsystem
The DDCChip subsystem contains a Device block. This block labels this level of design hierarchy that compiles onto the FPGA. DSP Builder generates VHDL for all levels of the hierarchy, but this level has additional script files that build a project in the Quartus II software. The Device block sets the FPGA family, device and speed grade. The family and speed grade optimize the hardware. In combination with the target clock frequency, the device determines the degree of pipelining. The following sections describe the blocks in the DDCChip subsystem. The following three types of block exist:
The grey blocks are ModelIP blocks. These represent functional IP such as black box filters, NCOs, and mixers. The blue blocks are processor visible registers. The black and white blocks are Simulink blocks.
You can mix and match blocks in a natural way. Figure 53 shows the first part of the datapath.
The inputs, NCO, and mixer stages show with Simulink signal formats turned on.
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Primary Inputs
The primary inputs to the hardware are two parallel data signals (DataInMain and DataInDiversity), a channel signal (DataChan), and a valid signal (DataValid). The parallel data signals represent inputs from two antennas. They are of type sfix14_13 which is a Simulink fixed-point type of total width 14 bits. The type is signed with 13 bits of fraction, which is a typical number format that a analog-to-digital converter generates. The data channel DataChan is always an 8-bit unsigned integer (uint8) and DSP Builder synthesizes away the top bits if not used. The valid signal DataValid indicates when real data transmits. The first rising edge of the valid signal starts operation of the first blocks in the chain. As the first blocks start producing outputs, their valid outputs start the next blocks in the chain. This mechanism ensures that filter chain start up is coordinated without having a global controller for the latencies of each block. The actual latencies of the blocks may change based on the clock frequency and FPGA selection.
Merge Multiplexer
The ModelIP blockset supports vectors on its input and output data wires, which ensures that a block diagram is scalable when, for example, changing channel counts and operating frequencies. The merge multiplexer (DDCMerge1) takes two individual wires and combines them into a vector wire of width 2. Although this is a Simulink Mux block, it does not perform any multiplexing in hardwareit is just as a vectorizing block. If you examine the RTL, it contains just wires.
NCO
The NCO block generates sine and cosine waveforms to a given precision. These waveforms represent a point in the complex plane rotating around the origin at a given frequency. DSP Builder multiplies this waveform by the incoming data stream to obtain the data from the transmitted signal. 1 Four frequencies exist, because the vector in the Phase Increment and Inversion field is of length 4. DSP Builder configures the NCO block to produce a signed 18-bit value with 17 bits of fraction. The internal accumulator width is set to 24 bits. This internal precision affects the spurious free dynamic noise (SFDN). DSP Builder specifies the initial frequencies for the simulation as phase increments. Because, the phase accumulator width in bits is 2^24, one complete revolution of the unit circle corresponds to a value of 2^24. Dividing this number by 5.95, means that the design requires 5.95 cycles to perform one complete rotation. That is, the wavelength of the sine and cosine that the design produces are 5.95 cycles. Because the sample rate is 61.44 MHz, the frequency is 61.44/5.95, which is 10.32 MHz. The input frequency in the testbench rotates every 6 cycles for a frequency of 61.44/6=10.24 MHz. Therefore, because DSP Builder mixes these signals you can expect to recover the difference of these frequencies (0.08 MHz or 80 kHz) which fall in the low-pass filters pass bands. f For more information about how to configure the NCO block refer to the ModelIP Tutorial on page 31.
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The design exposes phase values through a memory-mapped interface at the address specified by the variable DDC_NCO_PHASE_INCR, which is set to address 0x0000 in the setup script. After the simulation runs, a report file generates that confirms and documents that address map. To access this script right-clicking on the Control block in the top-level design example and click Help. DSP Builder reports for each register, the name, width, reset value, and address. This report collates all the registers from your design into a single location. You can view the estimated results for this NCO configuration in the Results tab of the dialog box). Based on the selected accumulator width and output width, DSP Builder calculates an estimated SFDR and accumulator precision. To verify this precision in a separate testbench, use demo_nco.mdl as a start.
Mixer
The Mixer block performs the superheterodyne operation by multiplying each of the two received signals (DataInMain and DataInDiversity) by each of the four frequencies. This action produces eight complex signals or 16 scalar signals (the 16 channels in the DDC design). The mixer requires sufficient multipliers to perform this calculation. The total number of real complex multiplications required for each sample is 2 signals 4 frequencies = 8. 8 real complex multiplies require 8 2 = 16 scalar multiplications. Because this processing is spread over four cycles (the TDM factor given by the ratio of clock rate to sample rate), 4 physical multipliers are required. The report file confirms this result, which you can by right-clicking the Mixer block (after you run a simulation) and clicking Help. The resource utilization section reports that the design uses four 1818 multipliers. The Help report also lists the input and output ports that DSP Builder creates for this block, with the data width and brief description. DSP Builder suffixes the vector inputs with 0 and 1 to implement the vector. This list of signals corresponds to the signals in the VHDL entity. DSP Builder provides the results for the mixer as separate in phase and quadrature outputseach is a vector of width 2. It performs the remaining operations on both the I and Q signals, so that DSP Builder can combine them with another Simulink multiplexer to provide a vector of width 4. This opera it on is carrying the 16 signals, with a TDM factor of 4. At this point the channel counts count 0, 1, 2, 3, 0, 1, ....
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To determine the setup, DSP Builder usually uses a microprocessor, which writes to a register to set the shift amount. This design uses a RegField block (Mixer_Scaling_Register). This block behaves like a constant in the Simulink simulation, but in hardware the block performs as a processor-writable register that initializes to the value in your design example. This parameterization results in a register mapped to address DDC_GAINS, which is a MATLAB variable that you specify in the setup_demo_ddc.m script. The register is writable from the processor, but not readable. The register produces a 2-bit output of type ufix(2)an unsigned fixed-point number. The scaling is 2^-0 so is, in effect, a 2-bit unsigned integer. These 2 bits are mapped into bits 0 and 1 of the word (another register may use other bits of this same address). The initial value for the register is set to 0. DSP Builder provides a description of the memory map in the updated Help for the block. Sometimes, Simulink needs an explicit sample time, but you can use the default value of 1 for this tutorial. The 2-bit unsigned integer is fed to the Scale3 block. This block has a vector of width 4 as its data input. The Scale3 block builds a vector of 4 internal scale units. These parameters are not visible through the user interface, but you can see them in the resource report by clicking Help on the Scale3 block. The block produces four outputs, which DSP Bu idler presents at the output as a vector of width 4. DSP Bu idler preserves the order in the vector. You can create quite a large block of hardware by passing many channels through a ModelIP block. The exception output of the scale block provides signals to say when saturation occurs, which this design does not require, so this design terminates them. The design sets the output format to 16-bit signed with 15 bits of fraction and uses the Unbiased rounding method. This method (convergent rounding or round-to-even) typically avoids introducing a DC bias. The saturation method uses Symmetric rounding which clips values to within +0.9999 to -0.9999 (for example) rather than clipping to 1. Again this avoids introducing a DC bias. The number of bits to shift is a vector of values that the scaling register block (Mixer_Scaling_Register) indexes. Because this is a vector of 4 values, DSP Builder requires a 2-bit input. An input of 0 uses the 0th value in the vector (address 1 in Simulink), and so on. Therefore, in this example inout0 shifts by 0 and the result at the input has the same numerical range as the input. An input of 1 shifts left by 1, and so multiply the input value by 2, thus increasing the gain.
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Two main blocks existthe DecimatingCIC and the Scale block. To configure the CIC Filter, double click on the DecimatingCIC block. The input sample rate is still the same as the data from the antenna. The SampleRate variable specifies the input sample rate. The number of channels, ChanCount, is a variable set to 16. The CIC filter has 5 stages, and performs decimation by a factor of 16. 1/16 in the dialog box indicates that the output rate is 1/16th of the input sample rate. The CIC parameter differential delay controls how many delays each CIC section usesnearly always set to 1. The CIC has no registers to configure, therefore no memory map elements exist. The input data is a vector of four elements, so DSP Builder builds the decimating CIC from four separate CICs, each operating on four channels. Because the decimation behavior reduces the data rate at the output, all 16 data samples (now at 61.44/16 MSPS each channel) can fit onto 1 wire. The DecimatingCIC block multiplexes the results from each of the internal CIC filters onto a single wire. That is, four channels from vector element 1, followed by the four channels from vector element 2. DSP Builder packs the data onto a single TDM wire. Data is active for 25% of the cycles because the aggregate sample rate is now 61.44 MSPS 16 channels/16 decimation = 61.44 MSPS and the clock rate for the system is 245.76 MHz. Figure 55 shows this behavior, which is the CIC_All_Scope in the CIC_Scopes subsystem. Bursts of data occur, with 16 contiguous samples followed by a gap. Each burst is tagged with the valid signal. Also the channel indicator shows that the channel order is 0..15.
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The number of input integrator sections is 4, and the number of output comb sections is 1. The lower data rate reduces the size of the overall group of 4 CICs. The Help page also reports the gain for the DCIC to be 1,048,576 or approximately 2^20. The comb section utilization confirms the 25% calculation for the TDM factor. The Help page also shows how DSP Builder combines the four channels of input data on a single output data channel. The Scale block reduces the output width in bits of the CIC results. In this case, the design requires no variable shifting operation, so it uses a Simulink constant to tie the shift input to 0. However, because the gain through the DecimatingCIC block is approximately 2^20 division of the output, enter a scalar value -20 for the Number of bits to shift left in the dialog box to perform data. 1 Enter a scalar rather than a vector value to indicate that the scaling is static.
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The first decimating FIR decimates by a factor of 4. The input rate per channel is the output sample rate of the decimating CIC, which is 16 times lower than the raw sample rate from the antenna. 1 You can enter any MATLAB expression, so DSP Builder can extract the 16 out as a variable to provide additional parameterization of the whole design. This filter performs decimation by a factor of 4 and the calculations reduce the size of the FIR filter. 16 channels exist to process and the coefficients are symmetrical. The Coefficients field contains information that passes as a MATLAB fixed-point object (fi), which contains the data, and also the size and precision of each coefficient. Specifying an array of floating-point objects in the square brackets to the constructor to achieve this operation. The length of this array is the number of taps in the filter. At the end of this expression, the numbers 1, 16, 15 indicate that the fixed-point object is signed, and has 16-bit wide elements of which 15 are fractional bits. f For more information about fi objects, refer to the MATLAB Help. This simple design uses a low-pass filter. Figure 57 shows the response. In a real design, more careful generation of coefficients may be necessary.
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The output of the FIR filter fits onto a single wire, but because the data reduces further, there is a longer gap between frames of data. Access a report on the generated FIR filter from the Help page. You can scroll down in the Help page to view the port interface details. These match the hardware block, although the RTL has additional ports for clock, reset, and the bus interface. The report shows that the input data format uses a single channel repeating every 64 clock cycles and the output data is on a single channel repeating every 256 clock cycles. Details of the memory map include the addresses DSP Builder requires to set up the filter parameters with an external microprocessor. The Help page also shows the total estimated resources. Altera estimates this filter to use 338 LUT4s, 1 1818 multiplier and 7844 bits of RAM. The Scale1 block that follows the DecimatingFIR1 block performs a similar function to the DecimatingCIC block. The DecimatingFIR2 block performs a second level of decimation, in a very similar way to DecimatingFIR1. The coefficients use a MATLAB function. This function (fir1) returns an array of 63 doubles representing a low pass filter with cut off at 0.22. You can wrap this result in a fi object:
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fi(fir1(62, 0.22),1,16,15)
The IScope block (Figure 58) shows the first two channels (1 real and 1 complex for the first carrier) of data (magenta and yellow) as the input signals. The first trace shows the rapidly changing input signal that the testbench generates. The second signal shows the result of the mixer. This slowly changing signal contains the information to be extracted, plus a lot of high frequency residue. Applying the series of low-pass filters and decimating results in the required data.
Figure 58. Simulation Results Shown in the IScope Block
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<block name>.vhd
demo_ddc_DDCChip_entity.xml An XML file that describes the boundaries of the DDCChip subsystem as a block box (for Signal Compiler in designs that combine blocks from the standard and advanced blocksets). DDCChip.xml *.stm safe_path.vhd safe_path_msim.vhd An XML file that describes the attributes of the DDCChip subsystem. Stimulus files. Helper function that ensures a pathname is read correctly in the Quartus II software. Helper function that ensures a pathname is read correctly in ModelSim.
rtl\demo_ddc\<subsystem> subdirectories Separate subdirectories exist for each hierarchical level in your design. These subdirectories include additional .xml .vhd, qip and .stm files describing the blocks contained in each level. Also additional .do and .tcl files exist, which it automatically calls from the corresponding files in the top-level of your model. <subsystem>_atb.do <subsystem>_atb.wav.do <subsystem>/<block>/*.hex <subsystem>.sdc <subsystem>.tcl <subsystem>_hw.tcl Script that loads the subsystem automatic testbench into ModelSim. Script that loads signals for the subsystem automatic testbench into ModelSim. Intel format .hex files that initialize the RAM blocks in your design for either simulation or synthesis. Design constraint file for TimeQuest support. Use this Tcl file to setup a Quartus II project. A Tcl script that loads the generated hardware into SOPC Builder.
The Signal View Depth parameter in the Control block determines the signals that add to the Wave window. Where appropriate, the signals automatically display in analog format (Figure 510). Simulink scopes identify the signals to display, therefore, to display a particular signal, just attach a scope, regenerate, and resimulate.
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Figure 510. Simulation Results in the ModelSim Wave Window for the DDC Design Example
After your design loads, you can compile your design by clicking Start Compilation on the Processing menu. 1 In many real production environments, wrap the generated RTL in some hand-coded RTL to perform detailed memory interfacing, high speed I/O, and interfacing to a processor. DSP Builder structures the generated RTL to ease this process.
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To instantiate your DSP Builder advanced subsystem into an SOPC Builder design, refer to the ModelIP Tutorial in Instantiating the Design in SOPC Builder on page 313.
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6. Latency Management
You may want to fix or constrain the latency after you complete part of a design, for example on a ModelIP block or for a primitive subsystem. In other cases, you may want to limit the latency in advance, which allows future changes to other subsystems without causing undesirable effects upon the overall design. To accommodate extra latency insert registers. This feature applies only to primitive subsystems. To access, use the ModelPrim Synthesis Info block. Latency is the number of delays in the valid signal across the subsystem. The DSP Builder advanced blockset balances delays in the valid and channel path with delays that DSP Builder inserts for auto-pipelining in the datapath. 1 User-inserted sample delays in the datapath are part of the algorithm, rather than pipelining, and are not balanced. However, any uniform delays that you insert across the entire datapath optimize out. If you want to constrain the latency across the entire datapath, you can specify this latency constraint in the SynthesisInfo block.
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Non-Explicit Delays
The design does not analyze delays to the valid path in primitive subsystems caused by anything other than explicit delays (for example Counter or Sequence blocks) and the design does not count in the valid latency. For example, the 4K FFT design example uses a Sequence block to drive the valid signal explicitly (Figure 62).
Figure 62. Sequence Block in the 4K FFT Design Example
The latency that the ChannelOut block reports is therefore not 4096 + the automatic pipelining value, but just the pipelining value.
Distributed Delays
The design example is not cycle-accurate inside a primitive subsystem, because DSP Builder distributes and optimizes the user-specified delay. For example, in Figure 61 on page 61 the Mult block has a direct feed-through simulation model, and the following SampleDelay block has a delayed simulation design example with a delay of 10. Thus, there is zero delay on the Mult block in simulation, followed by a delay of 10. In the generated hardware, DSP Builder distributes part of this 10-stage pipelining throughout the multiplier optimally, such that the Mult block has a delay (in this case, four pipelining stages) and the SampleDelay block a delay (in this case, six pipelining stages). The overall result is the same10 pipelining stages, but if you try to match signals in the primitive subsystem against hardware, you may find DSP Builder shifts them by several cycles. Similarly, if you have insufficient user-inserted delay to meet the required fMAX, DSP Builder automatically pipelines and balances the delays, and then corrects the cycle-accuracy of the primitive subsystem as a whole, by delaying the output signals in simulation by the appropriate number of cycles at the ChannelOut block. If there is no user-specified pipelining, the simulation design example for the multiplier is direct-feed-through, and the result appears on the output immediately (Figure 63).
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To reach the desired fMAX, DSP Builder then inserts four pipelining stages in the multiplier, and balances these with four registers on the channel and valid paths. To correct the simulation design example to match hardware, the ChannelOut block delays the outputs by four cycles in simulation and displays Lat: 4 on the block. Thus, if you compare the output of the multiplier simulation with the hardware it is now four cycles early in simulation; but if you compare the primitive subsystem outputs with hardware they match, because the ChannelOut block provides the simulation correction for the automatically inserted pipelining. If you want a consistent 10 cycles of delay across the valid, channel and datapath, you may need latency constraints (Figure 64).
Figure 64. latency Example with Consistent Delays
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In this example, a consistent line of SampleDelays inserts across the design. However, the algorithm does not use these delays. DSP Builder recognizes that designs do not require them and optimizes them away, leaving only the delay that designs require. In this case, each block requires a delay of four, to balance the four delay stages to pipeline the multiplier sufficiently to reach the target fMAX. The delay of 10 in simulation remains from the non-direct-feed-through SampleDelay blocks. In such cases, you receive the following warning on the MATLAB command line:
Warning: Some user inserted SampleDelays have been optimized away. The latency on the valid path across primitive subsystem '<design name>' in hardware is 4, which may differ from the simulation model. If you need to preserve extra SampleDelays in this case, use the 'Constraint Latency' option on the SynthesisInfo block.
In summary, if you want to consistently apply extra latency to a primitive subsystem, use latency constraints.
Latency and f
MAX
Constraint Conflicts
You cannot set a latency constraint that conflicts with the constraint that the fMAX target implies. For example, a latency constraint of < 2 for the example (Figure 63) conflicts with the fMAX implied pipelining constraint. The multiplier needs four pipelining stages to reach the target fMAX. The simulation fails and issues an error, highlighting the primitive subsystem. This error issues because you must increase the constraint limit by at least 3 (that is, to < 5) to meet the target fMAX.
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For example:
eval(get_param('design/latencydemo/ChannelOut','latency'))
DSP Builder calculates the latency in the initialization of the model, at the start of simulation. Because DSP Builder calculates all latencies at the same stage, you cannot use the latency of one block to set the constraint on another and expect to see the changes that propagate in the same simulation. For example, suppose you want to always have a latency of 40 for the CIC block in the demo_dcic design. Add a primitive subsystem after the CIC block (Figure 65). This subsystem consists only of ChannelIn, ChannelOut, and SynthesisInfo blocks. (Figure 66).
Figure 65. Decimating CIC Design Example Illustrating Latency Propagation
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On the SynthesisInfo block, set the following latency constraint that DSP Builder derives from the CIC block:
40 eval(get_param(demo_dcic/CICSystem/CIC, latency))
Any changes to the CIC block that change the latency do not display as immediate latency changes in the primitive subsystem; but only on the subsequent simulation and hardware generation cycle. The latency for the CIC block is only available after the initialization step in which it is set in the primitive subsystem. Thus, you must simulate until after cycle 0, stop and re-start simulation (without making any changes) to guarantee that DSP Builder applies the correct latency in the primitive subsystem. The SynthesisInfo block uses the evaluated CIC block latency from the previous simulation.
7. Folding
Folding is closely related to the TDM factor. When the system clock rate is faster than the data rate or sample rate, the same piece of hardware such as a multiplier can potentially reprocess multiple data points. Different data points use the TDM factor to access the shared hardware resource. Similarly, in a system with multiple parallel data sources or data channels, instead of duplicating hardware for each channel or data source, in many cases you can use one datapath to process multiple data channels. Folding allows multiple channels to access system resources such as multipliers and adders in a similar way to the TDM factor, thus resulting in resource savings. By default, the hardware that DSP Builder generates for a primitive subsystem can receive and process new data every clock cycle. However, some designs may not require this feature. For those designs with a sample rate lower than their clock rate, DSP Builder advanced blockset's folding functionality can take advantage of the disparity between both rates to optimize the generated hardware. You can implement your core algorithm in the most intuitive way, as if there was no folding or TDM factor. You do not have to explicitly implement signal multiplexing and data buffering schemes, which manually folded designs normally require. 1 Setting latency constraints is incompatible with folding in primitive subsystems. DSP Builder ignores any latency constraints set in folded subsystems.
Using Folding
You enable and configure folding in the primitive subsystem's ChannelIn and ChannelOut blocks. Turn on Folding enabled, to edit the Number of used TDM slots, and Sample rate parameters. The correct values for these parameters depend on the desired type of folded subsystem. 1 You must set the Folding enabled, Number of used TDM slots and Sample rate parameters to identical values for all ChannelIn and ChannelOut blocks in the same primitive subsystem. Set the Simulink solver to Variable Step Discrete, to use the folding feature.
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For this example, the data format you expect at ChannelIn inputs and which DSP Builder produces at ChannelOut outputs is: a0, x, x, x, a1, x, x, x, a2, x, x, x, a3, x, x, x, ... Where a0, a1, a2, a3, ..., are the input data to the design, and DSP Builder ignores data that it receives during the cycles marked as x. In this type of folded subsystem, you must set Number of used TDM slots to 1, and you must set Sample rate to the clock rate divided by the folding factor. DSP Builder needs no other changes with respect to the unfolded version of the same subsystem. In this setting, there is no TDM, as only 1 data source or data channel is present. A typical example of such a system is one that processes a single channel or a single data source. The primitive_fir design is an example of a folded subsystem without TDM factor.
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Figure 71 shows the color space converter design example, demo_fold_csc, which is an example of a folded subsystem with time division demultiplexing. In this example, the three elements r, g, and b represent three independent channels. By demultiplexing them onto three parallel datapaths inside the folded subsystem, you can apply distinct coefficients to each channel. The conversion algorithm in demo_fold_csc involves 9 multiplications. However, the number of multipliers the design uses when you enable folding depends on the folding factor, or the ratio of the clock rate and sample rate.
Figure 71. ChannelIn Block with time Division Demultiplexing
When enabling TDM, Simulink vectors appear. Ensure that the design continues to work as you expect in the presence of these vectors. The number of TDM slots must be smaller or equal to the folding factor. The greater the difference of folding factor and TDM slots, the greater hardware reuse and resource saving. If they are equal, DSP Builder receives new data and processes it every cycle. It reduces the hardware resources by a factor of the available TDM slots the folding factor. In the multichannel context, instead of duplicating hardware for each channel, multiple channels can in many cases share a single signal path for data processing. For instance, in the demo_fold_csc example, if the folding factor is 3 and r, g, and b occupies all 3 slots, the number of multipliers in the generated hardware is 3, down by 3-fold from the 9 multiplications in the algorithm. If the FGPA clock rate increases, which allows more folding or resource sharing, DSP Builder can reduces the number of multiplier hardware even further. For example, when the folding factor increases to 10, a single multiplier is sufficient to complete the 9 multiplications in the algorithm. Enough idle clock cycles between adjacent data bursts allow repeated reuse of the same hardware, thus DSP Builder generates optimized hardware that instantiates a single multiplier.
Effects of Folding
When you enable folding and the folding factor is greater than one, DSP Builder can reuse hardware resources with TDM to perform computation. This action can result in hardware savings, which is usually the result of enabling folding for a design. However, enabling folding also induces other changes in the hardware, as explained in the following sections. In some cases, these changes can result in hardware that is less desirable than the one with folding disabled. A general understanding of these changes can help to predict cases where usage of folding may not be advisable.
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If the subsystem's highest latency path is one that contains manual delays, enabling folding affects the subsystem's global latency. Although the length in cycles of manual delays is multiplied by the folding factor, the cost in hardware resources grows by a smaller factor that is typically only slightly above the Number of used TDM slots. The effect of folding on manual delays can solve the situation where DSP Builder cannot implement a certain feedback loop in hardware because of insufficient delays specified. A sufficiently large folding factor increases the length in clock cycles of existing delays so that they can compensate for the required pipelining of other blocks.
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With folding disabled, the resulting hardware can closely resemble the original Simulink blocks (Figure 74).
Figure 74. Example of Unfolded Hardware
A B C D
Assume that folding has a folding factor of 2. Each of the A, B, C, D inputs in Figure 74 only receive data every second clock cycle. As the hardware multipliers can perform one multiplication per clock cycle, in this example the design uses each one only half of the time. In this example, DSP Builder can use a single hardware multiplier to implement the two Simulink multiplier blocks. To timeshare the hardware multiplier between performing (A B) and (C D), DSP Builder must insert some extra delays and multiplexes. Figure 75 shows the resulting hardware.
Figure 75. Example of Folded Hardware
A C B D Z -1 Z -1 Z -1
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The folded hardware in Figure 75 may appear more expensive than the unfolded hardware in Figure 74. However this observation typically is not true. The saved multiplier normally requires more hardware resources than the delays and multiplexes that replace it. DSP Builder implements heuristics that limit block combination to those cases where you expect it to be beneficial.
Examples
Altera offers the following folding design examples:
This chapter describes how you can combine blocks from the DSP Builder standard and advanced blocksets in the same design. The top-level design example can contain the Control and Signals blocks from the advanced blockset. However, you must embed the Device block and the functional blocks in the advanced blockset design in a lower level subsystem. The Run ModelSim block from the advanced blockset does not work in a combined blockset design. However, you can use the TestBench block from the standard blockset to generate a testbench and compare the simulation results with the ModelSim simulator. You can still use the Run Quartus II block from the advanced blockset in a combined blockset design but it only creates a Quartus II project for the advanced blockset subsystem containing the Device block. Use a Signal Compiler block from the standard blockset to create a Quartus II project for the whole combined blockset design. The mechanism for embedding an advanced blockset subsystem within a top-level DSP Builder design is similar to that for embedding a HDL subsystem as a black-box design, with the Device block from the advanced blockset taking the place of the HDL Entity block from the standard blockset. 1 DSP Builder generates the advanced blockset design when you simulate the design in Simulink. Perform this simulation before DSP Builder generates the top-level design example by running Signal Compiler. The following settings and parameters must match across the two blocksets in an integrated design:
Use forward slash (/) separator characters to specify the hardware destination directory that you specify in the Control block as an absolute path. The device family that you specify in the Device block must match the device family you specify in the top level Signal Compiler block and the device on your development board. However, you can set the specific device to Auto, or have different values. The target device in the generated Quartus II project is the device that you specify in the Signal Compiler block. HIL specifies its own Quartus II project, which can have a different device provided that the device family is consistent. The reset type that you specify in the advanced blockset Signals block must be active High. When you run the TestBench for a combined blockset design, expect mismatches when the valid signal is low. The standard blockset does not support vector signals. To convert any vectors in the advanced blockset design, use multiplexer and demultiplexer blocks.
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Use HDL Input and HDL Output blocks (Figure 81 on page 82) to connect the subsystem that contains the advanced blockset design. The signal dimensions on the boundary between the advanced blockset subsystem and the HDL Input/HDL Output blocks must match.
Figure 81. Advanced Blockset Subsystem Enclosed by HDL Input and Output Blocks
The signal types are on either side of the HDL Input/HDL Output blocks after you simulate the subsystem. If the signal types do not display, check that Port Data Types is turned on in the Simulink Format menu. If the signal types do not match, there may be error messages of the form:
Error (10344): VHDL expression error at <subsystem>_<HDL I/O name>.vhd (line no.): expression has N elements, but must have M elements"
For example in Figure 81, DSP Builder issues an error because the signal type for the HDL OutputQ block is incorrect . Change it from Signed Fractional [2].[26] to Signed Fractional [2].[15]. After this change, the signal type shows as SBF_2_15 (representing a signed binary fractional number with 2 integer bit and 15 fractional bits) in the standard blockset part of the design (before the HDL Input block). The same signal shows as sfix17_En15 (representing a Simulink fixed-point type with word length 17 and 15 fractional bits) in the advanced blockset design (after the HDL Input block). 1 For more information about the fixed-point notation that the standard blockset uses, refer to the Fixed-Point Notation section in the DSP Builder Advanced Blockset User Guide section in volume 3 of the DSP Builder Handbook. For more information about Simulink fixed-point types, refer to the MATLAB help.
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2. Add three Input blocks from the DSP Builder IO & Bus library immediately before the new Subsystem block: Input (with Signed Fractional [1][11] type), Input1 (with Single Bit type), and Input2 (with Unsigned Integer 8 type). 3. Add an Output block immediately after the Subsystem block with Signed Fractional [1][15] type. 1 Steps 2 and 3 specify the boundaries between Simulink blocks and DSP Builder blocks.
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4. Open the Subsystem block and select the AD9856, OvScope, and ChanView blocks inside the subsystem. Click Create Subsystem on the popup menu to push these blocks down another level. Rename this subsystem (to for example DSPBA). 5. Add three HDL Input blocks from the DSP Builder AltLab library between the Simulink input ports and the DSPBA subsystem. a. These blocks should have the same types as in Step 2: HDL Input (Signed Fractional [1][11]), HDL Input1 (Single Bit), and HDL Input2 (Unsigned Integer 8). b. On the signed fractional HDL Input, set the External Type parameter to Simulink Fixed-point Type. 6. Add a HDL Output block between the subsystem and the subsystem output port with the same type as in Step 3 (Signed Fractional [1][15]). 1 Steps 5 and 6 specify the boundaries between blocks from the standard and advanced blocksets. The HDL Input and HDL Output blocks must be in a lower level subsystem than the Input and Output blocks. If they are at the same level, a NullPointerException error issues when you run Signal Compiler.
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7. Open the DSPBA subsystem and the AD9856 subsystem. 8. Move the Device block from the AD9856 subsystem up a level into the DSPBA subsystem you create by making a copy of the existing Device block and then deleting the old one. 1 The Device block detects the presence of a DSP Builder advanced subsystem and should be in the highest level of the advanced blockset design that does not contain any blocks from the standard blockset.
9. Open the Control block in the top level of the design and change the Hardware Destination Directory to an absolute path. For example: C:/rtl 1 You must use forward slashes (/) in this path.
10. Add Signal Compiler, TestBench and Clock blocks from the DSP Builder AltLab library to the top-level model.
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11. In the Signal Compiler block, set the Family to Stratix II to match the family specified in the Device block. 12. In the Clock block, set the Real-World Clock Period to 50 ns so that it matches the Clock Frequency specified in the Signals block. Set the Reset Name to aclr Active Low. 13. Remove the Run ModelSim and Run Quartus II blocks that the combined blockset design no longer requires. Figure 86 shows the updated design.
Figure 86. Updated AD9856 Design Example
14. Simulate the design to generate HDL for the advanced subsystem. 15. Compile the system using Signal Compiler. It should compile successfully with no errors. You can also use the Testbench block to compare the Simulink simulation with ModelSim. However, several cycles of delay in the ModelSim output are not present in Simulink because the advanced blockset simulation is not cycle-accurate. DSP Builder treats the subsystem containing the HDL Input, HDL Output blocks and the advanced blockset subsystem as a black box. You can only add additional blocks from the advanced blockset to the subsystem inside this black-box design. However, you can add blocks from the standard blockset in the top-level design or in additional subsystems outside this black-box design.
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A number of settings and parameters must match across the two blocksets in an integrated design. 1. Open the Adapted_AD9856.mdl design example from the Demos\Combined Blockset directory in the installed design examples for the standard blockset (Figure 87). f Ensure that the Hardware Destination Directory specified in the Control block is specified as an absolute path using forward slash (/) separator characters.
2. Simulate the design to generate hardware. 3. Run Signal Compiler to create a Quartus II project for the combined design. 1 The device family in the Signal Complier block is set to Stratix II, which should match the device family specified in the Device block inside the advanced blockset subsystem. If you use a different board, change the device family in both the Signal Compiler and the Device block and repeat steps 2 and 3.
4. Save a copy of the design example as Adapted_AD9856_HIL.mdl and delete the AdvancedBlockset subsystem in this model. 5. Replace the AdvancedBlockset subsystem by a HIL block from the AltLab library in the DSP Builder standard blockset.
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6. Double-click on the HIL block to open the Hardware in the loop dialog box (Figure 88). In the first page of the dialog box, select the Quartus II project (Adapted_AD9856_dspbuilder/Adapted_AD9856.qpf) that was created in step 3. Select the clock pin (Clock) and reset pin (aclr) names. Set the channelin signal type to unsigned 8 bits, dataIn to signed [1].[11] bits, and ChannelOut0 and ChannelOut1 to signed [1].[15] bits.
Figure 88. Hardware in the Loop Parameter Settings Page 1 for the AD9856 Example
7. Close the Hardware in the loop dialog box and connect the dataIn, validIn, channelIn, ChannelOut0, and ChannelOut1 ports to your design example (Figure 89 on page 89). 1 HIL simulation does not use the bus interface. Connect the bus_areset signal to a GND block and the bus_clk port to a VCC block from the standard blockset IO & Bus library. Connect the bus_clk_out and bus_clk_reset_out signals to Simulink Terminator blocks.
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8. Clean up the HIL design example by removing the blocks that are not related to the HIL (Figure 810).
Figure 810. Cleaned Up HIL Design
9. Save the Adapted_AD9856_HIL.mdl model. 10. Connect the DSP development board and ensure that you switch it on. 11. Re-open the Hardware in the loop dialog box and set the reset level as Active_High. 1 The reset level must match the level specified in the Signals block for the original model.
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12. Click on Next to display the second page of the Hardware in the loop dialog box (Figure 811). Enter a full device name into the FPGA device field. Verify that the device name matches the device on the DSP development board and is compatible with the device family set in the original model. 1 If you need to change the device family to use a different board, you must repeat steps 2, 3, 6, and 11.
13. Click Compile with Quartus II to compile the HIL model. 14. Click Scan JTAG to find all the hardware connected to your computer and select the required JTAG Cable and Device in chain. 15. Click Configure FPGA to download the compiled programming file (.sof) to the DSP development board. 16. Close the Hardware in the loop dialog box and save the model. 17. Simulate the HIL model. Compare the displays of the OutputSpectrum and OutScope blocks to the waveforms in the original model, which should be identical. Figure 812 on page 811 shows the output spectrum waveform and Figure 813 on page 811 shows the output scope waveform.
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You can speed up the HIL simulation using burst mode. To use burst mode, open the Hardware in the loop dialog box and turn on Burst Mode. Then repeat step 15 to download an updated programming file into the device on the DSP development board. This action resets the memory and registers to their starting value. When you simulate the HIL design example again the simulation is much faster. The OutputSpectrum display should be identical, but you can observe extra delays (equal to the burst length) on signals in the OutScope display.
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2. Simulate the design to generate HDL. f Ensure that the Hardware Destination Directory specified in the Control block uses an absolute, not relative, path.
This design demonstrates the Scale block from the advanced blockset to scale four-channel data from signed fractional [2].[30] to signed fractional [1].[15]. The four inputs are repeating square stairs of [1 0.5 -0.5 -1 0], randomly generated numbers, a slow sine wave, and a fast sine wave (Figure 815 on page 814).
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3. Open the Device block inside the ScaleSystem subsystem to verify that the target device family is compatible with the target DSP development board for the HIL simulation. 4. Double-click on the Run Quartus II block to start the Quartus II software and create a Quartus II project with the HDL generated in step 2. 1 The Quartus II project obtains its name from the subsystem that contains the Device block, ScaleSystem.qpf.
5. In the Quartus II Tools menu, click Start Compilation and verify that the project compiles successfully. 6. Save a copy of the design example as demo_scale_HIL.mdl and delete the ScaleSystem subsystem in this model. 7. Replace the ScaleSystem subsystem by a HIL block from the AltLab library in the DSP Builder standard blockset. 8. Double-click on the HIL block to open the Hardware in the loop dialog box (Figure 816 on page 815). In the first page of the dialog box, select the Quartus II project (ScaleSystem.qpf) that you created in step 4. Select the clock pin (clk) and reset pin (areset_n). Set the a0, a1, a2, and a3 input port types as signed [2].[30], the q0, q1, q2, and q3 output port types as signed [1].[15]. 1 Leave the ac and shift input ports and the qc output port as unsigned. The reset level must match the level specified in the Signals block for the original model.
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Figure 816. Hardware in the Loop Parameter Settings Page 1 for the Scale Block Example
9. Close the Hardware in the loop dialog box. 10. Remove the Scope1, Scope3, Unit Delay, Unit Delay1, MinMax, MinMax1, To Workspace. Display, Display1, Display2, and Display3 blocks from the model. 11. Connect all the inputs and outputs to the HIL block using Input and Output blocks from the standard blockset. Verify that the data types for all the inputs and outputs are set correctly, matching those set in the Hardware in the loop dialog box by step 8. 1 The HIL block expands the channel data input bus into four individual inputs (a0, a1, a2, and a3) and the channel data output bus into four separate outputs (q0, q1, q2, and q3).
Use Simulink Demux and Mux blocks to separate the inputs into individual inputs and multiplex the four outputs together into one data bus. Connect a a VCC block from the standard blockset IO & Bus library to the signal input bus_areset_n. Terminate the output signals qe0, qe1, qe2, and qe3 using Simulink Terminator blocks. Figure 89 on page 89 shows the updated model.
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12. Connect the DSP development board and ensure that you switch it on. 13. Re-open the Hardware in the loop dialog box and set the reset level as Active_High. 14. Click on Next to display the second page of the Hardware in the loop dialog box (Figure 818). Enter a full device name into the FPGA device field. Verify that the device name matches the device on the DSP development board and is compatible with the device family set in the original model.
Figure 818. Hardware in the Loop Parameter Settings Page 2
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15. Click Compile with Quartus II to compile the HIL model. 16. Click Scan JTAG to find all the hardware connected to your computer and select the required JTAG Cable and Device in chain. 17. Click Configure FPGA to download the compiled programming file (.sof) to the DSP development board. 18. Close the Hardware in the loop dialog box and save the model. 19. Simulate the HIL model. Compare the waveform of the DataOutScope block to the results for the original model, which should be identical.
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Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Revision History
The following table shows the revision history for this section.
Date December 2010 Version 2.0
Changes Made Corrrected categorized block list Added the following block descriptions, which are in the Additional library:
AStInput AStInputFIFO AStOutput latch_0L) latch_1L) SRlatch_PS) SRlatch) ExpandScalar TappedDelayLine VectorMux
June 2010 1.0 First published. Replaces DSP Builder Advanced Blockset Reference Manual.
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1. Introduction
Base Library
This library contains basic blocks that allow you to control your design flow and run external synthesis and simulation tools.
FFT Library
This library contains common blocks that support FFT design. It also includes support for a Radix-22 algorithm. f For more information about the Radix-22 algorithm, refer to A New Approach to Pipeline FFT Processor Shousheng He & Mats Torkleson, Department of Applied Electronics, Lund University, Sweden.
Filter Library
This ModelIP library contains several decimating and interpolating cascaded integrator comb (CIC), and finite impulse response (FIR) filters including single rate multirate and fractional rate FIR filters. Multirate filters are essential to the up and down conversion tasks that modern radio systems require. Cost effective solutions to many other DSP applications also use multirate filters to reduce the multiplier count. A memory-mapped interface allows you to read and write coefficients directly, easing system integration.
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ModelBus Library
This library provides memories and registers that you can access in your DSP datapath and with an external interface. You can use these blocks to configure coefficients or run-time parameters and read calculated values. This library also provides blocks that you can use to simulate the bus interface in the Simulink environment.
ModelPrim Library
This library contains primitive operators such as add, multiply, and delay. It also includes functions to manipulate signal types that support building hardware functions that use the MathWorks fixed-point types. You do not need to understand the details of the underlying FPGA architecture, as the primitive blocks are automatically mapped into efficient FPGA constructs. You can design and debug your model quickly using zero-latency blocks, without having to track block latencies around your circuit, decreasing design time and reducing bugs. You can let the synthesis tool pipeline your logic to give you the system clock frequency you need and take care of pipeline balancing. Arithmetic operators, such as adders, are pipelined to increase operating frequency. Register blocks and shared memories permit synthesis of the processor-datapath interface. Your design remains portable between supported FPGA families, allowing you to future-proof your design investment. f Some primitives support Simulink 1-D vector and complex types.
The Additional library contains the following blocks in the Avalon Streaming folder:
Avalon-ST Output (AStOutput) Avalon-ST Input (AStInput) Avalon-ST Input FIFO Buffer (AStInputFIFO)
The Additional library contains the following blocks in the Control folder:
Zero-Latency Latch (latch_0L) Single-Cycle Latency Latch (latch_1L) Reset-Priority Latch (SRlatch_PS) Set-Priority Latch (SRlatch)
The Additional library contains the following blocks in the Vector Utils folder:
Expand Scalar (ExpandScalar) Vector Multiplexer (VectorMux) Tapped Delay Line (TappedDelayLine)
Channel Viewer (ChanView) Control Device Edit Params LocalThreshold Run ModelSim Run Quartus II Scale Signals
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Table 21. AStOutput Block External Interface Signals Name source_ready source_sop source_valid Direction Input Output Output Description Indicates from downstream components that they can accept source_data on this rising clock edge. Indicates start of packet. indicates that source_data, source_channel, source_sop, and source_eop are valid.
Table 22 shows the AStOutput block signals that interface internally with the DSP Builder design component.
Table 22. AStOutput Block Internal Interface Signals Name output_channel output_data output_eop output_ready output_sop output_valid Direction input input input output input input Channel number. The output data (which may be, or include control data). Indicates end of packet. Indicates from the output of the DSP Builder component that it can accept sink_data on this rising clock edge. Indicates start of packet. Indicates that output_data, output_channel, output_sop, and output_eop are valid. Description
The downstream system component may not accept data and so may back pressure this block by forcing Avalon ST signal source_ready = 0. However, the DSP Builder design may still have lots of valid outputs in the pipeline. You must store these outputs in memory. DSP Builder writes the output data for the design into a data FIFO buffer, with Avalon-ST signals channel. It writes sop and eop into the respective channel, FIFO buffers. Connect the back pressure signal (source_ready) from downstream components to port ready in this subsystem. Then DSP Builder on reads the FIFO buffers when the downstream block can accept data (read_fifo = 1) and there is data in FIFO to output (fifo_empty_n = 1). If the downstream component is continually back pressuring this DSP Builder design, these FIFO buffers start to fill up. If you continue to feed data into the DSP Builder component, eventually the FIFO buffers overflow, which you must not allow to happen. Therefore, when the FIFO buffers reach a certain fill level, they assert signal nearly_full = 1. Use this signal to apply back pressure to upstream component (forcing Avalon ST signal sink_ready = 0). So that upstream components stop sending in more data and so that the FIFO buffer should not overflow, set the fill level at which nearly_full = 1 to a value that depends on the latency of this DSP Builder design. For example, if the design contains a single primitive subsystem and the ChannelOut block indicates a latency of L, assert the nearly_full flag at the latest point when there are L free entries in the FIFO buffer. Setting this threshold is a manual process and full threshold must be greater than or equal to (depth of FIFO buffer L).
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Table 24 shows the AStInput block signals that interface internally with the DSPBA design component.
Table 24. AStInput Block Internal Interface Signals Name input_channel input_data input_eop input_ready input_sop input_valid Direction output output output input output output Channel number. The data (which may be, or include control data). Indicates end of packet. indicates from the output of the DSP Builder component that it can accept sink_data on this rising clock edge. Indicates start of packet. indicates that input_data, input_channel, input_sop and input_eop are valid. Description
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Figure 21. Channel Viewer Output for Two Channels on a Single Wire
You can add delays after ChanView blocks if you want to realign the output channels.
Parameters
Table 27 shows the parameters for the ChanView block.
Table 27. Parameters for the ChanView Block
Parameter
Description
Number of input channels Specifies the number of unique channels the block can process. The design does not use this parameter unless the data bus is a vector or the TDM factor is greater than the number of channels. If the data bus is a vector, this value determines which vector element contains the correct channel. Output channels A vector that controls the input channels to decode and present as outputs. The number of outputs equals the length of this vector, and each output corresponds to one channel in order.
Port Interface
Table 28 shows the port interface for the ChanView block.
Table 28. Port Interface for the ChanView Block
Description The data input to the block. This signal may be a vector. Indicates validity of data input signals. If v is high then the data on the a wire is valid. Indicates channel of data input signals. If v is high, then c indicates which channel the data corresponds to. Each output is a deserialized version of the channel contained in the TDM bus. The output value is updated on each clock cycle that has valid data when the channel matches the required channel.
Updated Help
After DSP Builder runs a simulation, it updates the help pages with specific information about each instance of a block. Table 29 shows some typical help messages that DSP Builder issues for the ChanView block.
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Description The latency that this block introduces. Lists the port interfaces to the ChanView block. Lists the resource utilization for the ChanView block.
Written on Tue Feb 19 11:25:27 2008 Date and time when you ran this file.
Design Example
The demo_AD9856, demo_ddc, demo_duc, demo_dcic, demo_filters_flow_control, demo_firs, demo_fird, demo_firi, demo_firf, demo_firih, demo_fir_fractional, demo_fir_rrc, demo_icic, demo_iir, demo_nco, demo_mix, demo_complex_mixer, demo_scale, and demo_wimax_duc design examples include the ChanView block.
Control
The Control block specifies information about the hardware generation environment and the top-level memory-mapped bus interface widths. A Control block must be present at the top level of your model.
Parameters
Table 210 shows the parameters for the Control block.
Table 210. Parameters for the Control Block
Parameter Generate hardware Hardware destination directory Create automatic testbenches (1) Turn on to enable output file generation.
Description Specifies the root directory in which to write the output files. This location can be an absolute path or a relative path (for example, ../rtl). A directory tree is created under this root directory that reflects the names of your model hierarchy. Turn on this option to generate additional automatic testbench files. These files capture the input and output of each block in a .stm file. DSP Builder creates a test harness (_atb.vhd) that simulates the generated RTL alongside the captured data. DSP Builder generates a script (<model>_atb.do) that you can use to simulate the design in ModelSim and ensure bit and cycle accuracy between the Simulink model and the generated RTL. A wave.do file generates that you can use to open a Wave window in ModelSim. The wave.do file displays all important signals down to the specified level of hierarchy. If you are creating automatic testbenches, this option controls whether ModelSim's code coverage tools enable (if available). Specifies the width in bits of the memory-mapped address bus (132, default=10). Specifies the width in bits of the memory-mapped data bus (16 or 32, default=16). Specifies whether the memory-mapped address bus is Big Endian or Little Endian.
Signal view depth Turn on coverage in testbenches System address width System data width System bus is:
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Parameter Delay: register and RAM block threshold (2) DualMem: small and medium threshold (2) DualMem: medium and large threshold (2) Multiplier: logic and DSP threshold (2)
Notes to Table 210:
Description Specifies the RAM block threshold in bits. If the number of logic cells the design requires is greater than the specified value, the design implements the delay with RAM blocks. Any value less than 0 means use the default 20 bits. Specifies the dual memory RAM threshold in bits. If the number of logic cells that a dual memory block requires is greater than the specified value, the design implements the delay with RAM blocks. Any value less than 0 means use the default 1,280 bits. Specifies the M-RAM threshold in bits. If the number of bits in memory is greater than the specified value, the design uses an M-RAM. Any value less than 0 means never use M-RAM or M144K. Specifies the hard multiplier threshold in bits. The number of logic elements you want to use to save a multiplier. If the design exceeds the specified value, it uses hard multipliers. Any value less than 0 means always use hard multipliers.
(1) For more information about this parameter, refer to Comparison with RTL in the DSP Builder Advanced Blockset User Guide section in volume 3 of the DSP Builder Handbook. (2) For more information about these parameters, refer to Basic Blocks in the DSP Builder Advanced Blockset User Guide section in volume 3 of the DSP Builder Handbook.
Updated Help
After you run a simulation, DSP builder updates the help pages with specific information about each instance of a block. Table 211 shows a typical help message that DSP Builder issues for the Control block.
Table 211. Messages for the Control Block
Description Lists the resource utilization for each subsystem in the current model.
Design Example
All the design examples use the Control block.
Device
The Device block marks a particular Simulink subsystem as the top-level design of an FPGA device. DSP Builder generates project files and scripts that relate to this level of hierarchy. All blocks in subsystems below this level become part of the RTL design. All blocks above this level of hierarchy become part of the testbench. You can insert multiple Device blocks in non-overlapping subsystems to use multiple FPGAs in the same design. You can mix device families freely. Table 212 shows the parameters for the Device block.
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Description Select the required target device family (Stratix, Stratix GX, Stratix II, Stratix II GX, Stratix III, Stratix IV, Cyclone II, Cyclone III, or Arria II GX). Specifies the device member as free-form text or enter AUTO to allow automatic selection. If you enter free-form text, the name must start with EPxxx. For example: EP2C35F484C6. You can select the speed grade for the FPGA target, which helps DSP Builder balance the hardware size against the resources required to meet the clock frequency set in the Signals block.
Design Example
All the design examples use the Device block.
Edit Params
The Edit Params block is not available as a functional block in the Simulink library browser. However, you can create your own Edit Params block as a graphical shortcut to a MATLAB M-script that sets up and initializes your design. Examples of Edit Params blocks are in many of the design examples. You can create an Edit Params block if you create an M-script defining workspace variables that you want to call when your model loads or initializes. Specify this script in the PreLoadFcn or InitFcn callbacks that you can access by clicking Model Properties on the File menu:
To call your script automatically when your model opens, add a PreloadFcn reference to your script in the Callbacks tab of your Model Properties in Simulink. To call your script automatically at the start of a simulation run, add a InitFcn reference to your script in the Callbacks tab of your Model Properties in Simulink.
In the design examples, the names of the initialization scripts derive from your model name: setup_<model name>.m. For example, setup_demo_firs.m (Figure 22).
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Figure 22. Callbacks Tab in the Simulink Model Properties Dialog Box
To create an Edit Params block that references this script, follow these steps: 1. Drag a Subsystem block from the Simulink Commonly Used Blocks library. 2. Double-click on the Subsystem block to open it and delete the default In1 and Out1 ports. Close the Subsystem block. 3. Right-click on the Subsystem block, select Block Properties and click the Callbacks tab.
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5. If you name your script setup_<model name>.m, enter the following functions:
s = sprintf('edit setup_%s', eval('gcs')); eval(s);
Alternatively, you can explicitly reference a script such as my_script.m by entering a function of the form:
eval(edit my_script.m);
6. Click OK to close the Block Properties dialog box. 7. Rename the Subsystem block EditParams (or any name of your choice). 1 You can optionally hide the block name by right-clicking and clicking Hide Name on the popup menu.
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8. If you want to apply a graphic icon to your block, right-click and select Mask Subsystem to display the Mask Editor dialog box (Figure 24).
Figure 24. Mask Editor Dialog Box
9. Click the Icon tab and enter drawing commands using the following format:
image(imread('edit_params.png')); color('w'); fprintf('Edit\nParams');
These commands reference the default icon for an Edit Params block, set the text color to white and specify the text overlay on the block. You can optionally specify your own custom graphic file, color, and text. f For more information about drawing commands in the mask editor, refer to the Simulink Help.
10. Select Invisible from the Frame icon options. 11. Click on the Documentation tab and enter the Mask type: DSP Builder Advanced Blockset Ignored Block. 12. Click OK to close the Mask Editor. 1 To create an Edit Params block copy an existing block from one of the design examples, and edit the block and mask properties to customize it for your model.
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Usage
Double-click on the Edit Params block to open the script in the MATLAB text editor.
Design Example
The demo_AD9856, demo_complex_mixer, demo_ddc, demo_duc, demo_dcic, demo_filters_flow_control, demo_fird, demo_firf, demo_firi, demo_firih, demo_fir_fractional, demo_fir_rrc, demo_firs, demo_icic, demo_nco, demo_mix, demo_fft16_radix2, demo_fft256_radix4, demo_fft_4096_br, demo_fft_8192_br, demo_ifft_4096_natural, and demo_ifft_8192_natural design examples include the Edit Params block.
LocalThreshold
The LocalThreshold block allows hierarchical overrides of the global clock margin and threshold settings set on the Control and Signals blocks. You can place the LocalThreshold block anywhere in your design to define over-ride values for the margin and threshold settings for that subsystem and any embedded subsystems. You can over-ride these values further down in the hierarchy by implementing more LocalThreshold blocks. For example, you can specify different clock margins for different regions of your design.
Parameters
Table 210 shows the parameters for the Control block.
Table 213. Parameters for the Control Block
Description Specifies the margin requested to achieve a high system frequency in the fitter. The specified margin does not affect the folding options because the system runs at the rate specified by the Clock frequency parameter setting. Specify a positive clock margin if you need to pipeline your design more aggressively (or specify a negative clock margin to save resources) when you do not want to change the ratio between the clock speed and the bus speed. Specifies the RAM block threshold in bits. If the number of logic cells the design requires is greater than the specified value, the design implements the delay with RAM blocks. Any value less than 0 means use the default 20 bits. Specifies the dual memory RAM threshold in bits. If the number of logic cells that a dual memory block requires is greater than the specified value, the design implements the delay with RAM blocks. Any value less than 0 means use the default 1,280 bits. Specifies the M-RAM threshold in bits. If the number of bits in memory is greater than the specified value, the design uses an M-RAM. Any value less than 0 means never use M-RAM or M144K. Specifies the hard multiplier threshold in bits. The number of logic elements you want to use to save a multiplier. If the design exceeds the specified value, it uses hard multipliers. Any value less than 0 means always use hard multipliers.
Delay: register and RAM block threshold DualMem: small and medium threshold DualMem: medium and large threshold Multiplier: logic and DSP threshold
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Run ModelSim
The Run ModelSim block works by stimulus capture, in the same way as the automatic testbenches (ATBs), and compares the Simulink simulation result to the ModelSim simulation.
Usage
Instantiate the Run ModelSim block into the top-level of any design. Double-click the Run ModelSim block to launch the ModelSim tool with the user system as the top-level entity. ModelSim automatically starts compiling your design and runs a simulation for the same number of clock cycles as the Simulink simulation. The simulation compiles and loads with the .do scripts that generate when you run a Simulink simulation. DSP Builder creates the .do scripts in the hardware destination directory that you specify in the Control block. DSP Builder creates the generated files and scripts in a hierarchy of directories that match the hierarchy of your design and calls lower level scripts from the scripts in the top-level directory.
Design Example
All the design examples use the Run ModelSim block.
Run Quartus II
The Run Quartus II block allows automatic launch of the user system in the Quartus II software, where you can verify your design for performance and logic utilization.
Usage
Instantiate the Run Quartus II block into the top-level of any design containing an Altera Device block. Double-click the Run Quartus II block to launch the Quartus II software with the user system as the top-level entity. DSP Builder creates the Quartus II project file (.qpf), Quartus II settings file (.qsf), and Quartus II IP file (.qip) for the Quartus II project in your design directory that contains the .mdl file. These files contain all required references to the files in the hardware destination directory that the Control block specifies and are generated when you run a Simulink simulation. After loading the project in the Quartus II software, you should check the required device settings. You can then compile your design by clicking Start Compilation on the Processing menu. The project compiles with the .tcl scripts in the hardware destination directory. DSP Builder creates the generated files and scripts in a hierarchy of directories that match the hierarchy of your design and calls lower level scripts from the scripts in the top-level directory.
Design Example
All the design examples use the Run Quartus II block.
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Scale
You can use the Scale block to select part of a wide input word, performing various types of rounding, saturation and fixed-point scaling, to produce an output of specified precision. By default, DSP Builder preserves the binary point so that the fixed-point interpretation of the result has the same value, subject to rounding, as the fixed-point interpretation of the input. You can dynamically perform additional scaling, by specifying a variable number of bits to shift, allowing you to introduce any power of two gain. 1
Always use Scale blocks to change data types in preference to Convert blocks, because they vectorize and automatically balance the delays with the corresponding valid and channel signals.
Parameters
Table 214 shows the parameters for the Scale block.
Table 214. Parameters for the Scale Block
Description The type of the result. For example: sfix(16), uint(8). The scaling of the result if the result type is fixed-point. For example: 2^-15. Specifies one of the following three rounding methods for discarding the least significant bits (LSBs):
Truncate: truncates the least significant bits. Has the lowest hardware usage, but introduces the worst bias. Biased: rounds up if the discarded bits are 0.5 or above. Unbiased: rounds up if the discarded bits are greater than 0.5, and rounds to even if the discarded bits equal 0.5.
Multiplication factor
Modify the interpreted value by scaling it by this factor. This factor does not affect the hardware generated for the Scale block, but merely affects the interpretation of the result. For example: 1, 2, 3, 4, 8, 0.5. Specifies on of the following three saturation methods for discarding the most significant bits (MSBs):
Saturation method
None: no saturation is performed. Asymmetric: the range of the number produced occupies the whole of the two's complement range (for example 1.0 to 0.999). There is one more negative number available, so introduces a slight bias. Symmetric: the range of the result is clipped to between symmetrical boundaries (for example -0.999 and 0.999). Ensures no bias enters the dataflow.
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Description A scalar or a vector that determines the gain of the result. A positive number indicates that the scale block introduces a gain to the input. A negative number means that the output signal is attenuated. A vector of gains allows the shift input signal to select which gain to use on a cycle per cycle basis. The value of the shift integer performs zero-based indexing of the vector. For example: 2, -4, [0 1 2 3].
Port Interface
Table 215 shows the port interface for the Scale block.
Table 215. Port Interface for the Scale Block
Signal a a_v
Direction Description Input Input The data input to the block. If you request more channels than can fit onto a single bus, this signal is a vector. The width in bits is inherited from the input wire. Indicates validity of data input signals. If a_v is high then the data on the a wire is valid. Indicates channel of data input signals. If a_v is high, then a_chan indicates to which channel the data corresponds. Indicates which element of the zero-based shift vector to use. The data output from the block. If you request more channels than can fit onto a single bus, this signal is a vector. The width in bits is calculated as a function of the input width in bits and the parameterization. Indicates validity of data output signals. Indicates channel of data output signals. Indicates whether the output sample has saturated or overflowed.
q_v q_exp
Output Output
q_chan Output
Updated Help
After you run a simulation, DSP Builder updates the help pages with specific information about each instance of a block. Table 216 shows some typical help messages that DSP Builder issues for the Scale block.
Table 216. Messages for the Scale Block
Message Example Written on Tue Feb 19 11:25:27 2008 Number of physical buses: 4
Description Date and time when this file ran. Depending on the input data rate, the number of data wires needed to carry the input data may be more than 1. The latency introduced by this block. Lists the current rounding and saturation modes. Lists the port interfaces to the Scale block. Lists the resource utilization for the Scale block.
Calculated bit width of output stage: 16 The width in bits of the (vectorized) data output. Latency is 2 Parameters table Port interface table Resource utilization table
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Design Example
The demo_scale, demo_ddc, demo_duc, demo_AD9856, demo_filters_flow_control, demo_wimax_duc, and demo_fir_fractional design examples include the Scale block.
Signals
The Signals block specifies information about the system clock, reset, and memory bus signals that the simulation model and the hardware generation use. DSP Builder uses the names of the signals to generate the RTL. You must include a Signals block at the top level of your model.
Parameters
Table 217 shows the parameters for the Signals block.
Table 217. Parameters for the Signals Block
Description Specifies the name of the system clock signal that DSP Builder uses in the RTL generation. Specifies the system clock rate for the system. Specifies the margin requested to achieve a high system frequency in the fitter. The specified margin does not affect the folding options because the system runs at the rate specified by the Clock frequency parameter setting. Specify a positive clock margin if you need to pipeline your design more aggressively (or specify a negative clock margin to save resources) when you do not want to change the ratio between the clock speed and the bus speed. Specifies the name of the reset signal that DSP Builder uses in the RTL generation. Specifies whether the logic generated is reset with an active High or active Low reset signal. Specifies the prefix for the address, data and control signals in the generated control bus. When this option is turned on, any processor-visible control registers are clocked by a separate control bus clock to facilitate timing closure. Specifies the frequency of the separate processor interface bus clock (when enabled). Express this value as a fraction of the clock frequency and determine the amount of folding (TDM) that DSP Builder performs to achieve optimum logic utilization. When this option is on, the bus clock is synchronous with the system clock.
Reset Reset active Bus name Separate bus clock (Note 1) Bus clock frequency (MHz) Bus clock synchronous with system clock
Note to Table 217:
(1) This option should be off when using Cyclone families because these devices have limited multiple clock support in block RAMs and do not support a separate bus clock.
Updated Help
After you run a simulation, DSP Buidler updates the help pages with specific information about each instance of a block. Table 218 shows a typical help message that DSP Builder issues for the Signals block.
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Description Lists the system clock name, system clock rate, fitter target frequency, reset name, and reset active parameters for the current model.
Design Example
All the design examples use the Signals block.
3. Filter Library
Decimating CIC Decimating FIR Fractional Rate FIR Interpolating CIC Interpolating FIR Single-Rate FIR
Common Features
Filter length from 1 to 256 taps Data input width from 2 to 32 bits Data output width from 4 to 64 bits Multichannel (up to 1024 channels) Powerful MATLAB integration Simulink fixed-point integration Automatic pipelining Plug and play connectivity Simplified timing closure
Each channel is an independent data source. In an IF Modem design, two channels are required for the complex pair from each antenna.
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At each sample time k, the new output y, is calculated by multiplying coefficients a, by the recent past values of the input x.
Automatic Pipelining
The required system clock frequency, and the device family and speed grade determine the maximum logic depth permitted in the output RTL. Functions such as adders are pipelined by splitting them into multiple sections with a registered carry between them. This pipelining decreases the logic depth allowing higher frequency operation.
Resource Utilization
Figure 32 shows the FPGA resource utilization for a single-rate FIR filter. The multiplier counts fall dramatically as the clock frequency increases, because each multiplier is able to perform more taps.
Figure 32. Typical FIR Filter Resource Usage
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The number of logic resources has a bowl-shaped curve. This curve reflects the fact that at low frequencies there are more adders to cope with the extra multipliers, while at high frequencies long adders have been pipelined into shorter sections, to meet the system clock frequency requirement.
Scalability
In some cases, the aggregate sample rate for all channels may be higher than the system clock rate. In these cases, the filter has multiple input or output buses to carry the additional data. This requirement is implemented in the Simulink block by increasing the vector width of the data signals.
Parameterization
The system specification, including such factors as the channel count and sample rates, determines the main parameters for a filter. The remaining parameters such as data widths and system clock rates are inferred from the enclosing Simulink model. Any changes to these parameters ripple through your design, changing the system performance without you having to update all the components. You can express any of the parameters as MATLAB expressions, to rapidly parameterize a whole system. The hardware generation techniques create efficient filters with combinations of parameters, such as a symmetric 3-band FIR filter with 7 channels and 100 cycles to process a sample from each channel. Hardware generation is fast and can run on-the-fly with every Simulink simulation, so that the edit simulation loop time is much reduced, improving productivity.
Coefficient Generation
You can generate filter coefficients using a MATLAB function that reloads at run time with the memory-mapped interface registers. For example, the Simulink fixed-point object fi(fir1(49, 0.3),1,18,19).
Channelization
The generated help page for the block shows the input channel data format and output data channel format that a FIR or CIC filter uses, after you have run a Simulink simulation.
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Decimating CIC
The DecimatingCIC block implements a highly efficient multichannel cascaded integrator-comb filter across a broad range of parameters directly from a Simulink model. The DecimatingCIC block performs filtering on a stream of multichannel input data and produces a stream of output data with decreased sampling frequency. You can use the DecimatingCIC block in a digital down converter for a radio system or a general purpose DSP application. The coefficients and input data are fixed-point types, and the output is the implied full-precision fixed-point type. You can reduce the precision with a separate Scale block, which can perform rounding and saturation to provide the required output precision.
Features
The DecimatingCIC block supports rate changes from 2 to 64.
Operation
The DecimatingCIC has a lower output sample rate than the input sample rate by a factor D, where D is the decimation factor. Usually, the DecimatingCIC discards (D1) out of D output samples thus lowering the sample rate by a factor D. The physical implementation avoids performing additions leading to these discarded samples, reducing the filter cost. Figure 33 shows how decimating by 5 decreases the sample rate of a random noise input.
Figure 33. Decimate by 5 Filter Decreasing Sample Rate of a Random Noise Input
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Parameters
Table 31 shows the parameters for the DecimatingCIC block.
Table 31. Parameters for the DecimatingCIC Block
Parameter
Description
Input rate per channel Specifies the sampling frequency of the input data per channel measured in millions of samples per second (MSPS). Number of channels Number of stages Decimation factor Differential delay Specifies the number of unique channels to process. Specifies the number of comb and integrator stages. Specifies the decimation factor 1/(integer). (An integer greater than 1 implies interpolation.) Specifies the differential delay.
Port Interface
Table 32 shows the port interface for the DecimatingCIC block.
Table 32. Port Interface for the DecimatingCIC Block
Signal a v c
Direction Description Input Input Input The data input to the block. If you request more channels than can fit on a single bus, this signal is a vector. The width in bits is inherited from the input wire. Indicates validity of the data input signals. If v is high, the data on the a wire is valid. Indicates channel of data input signals. If v is high, c indicates which channel the data corresponds to. When this input asserts, the input data is zero-stuffed and scaled by the gain of the filter, which is useful during hardware debugging. The data output from the block. If you request more channels than can fit on a single bus, this signal is a vector. The width in bits is a function of the input width in bits and the parameterization. Indicates validity of data output signals. (Note 1) Indicates channel of data output signals. (Note 1)
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Table 33. Stratix III Fitter Results for a DecimatingCIC Number of Channels 16 16 16 132 32 32 32 Input Rate (MSPS) 10 10 10 10 10 10 10 Decimation Rate 2 10 10 2 2 10 10 Comb ALUTs 472 526 664 812 819 1,055 1,159 Logic 1818 Registers Multipliers 1,149 1,320 1,806 1,612 1,433 2,226 2,226 0 0 0 0 0 0 0 Block Memory Bits 0 0 0 0 0 0 0 Memory ALUTs 230 350 350 478 460 718 700 System Frequency Frequency Achieved (MHz) (MHz) 400 200 400 200 400 200 400 419 261 443 275 430 259 416
Updated Help
After you run a simulation, DSP Builder updates the help pages with specific information about each instance of a block. Table 34 shows some typical help messages that DSP Builder issues for the DecimatingCIC block.
Table 34. Messages for the DecimatingCIC Block
Message Example Decimating CIC Filter Version: $Revision: 1.20 $ Number of physical input buses / integrators: 1 Number of physical output buses / combs: 2
Description The version number and revision for the Decimating CIC Filter (Version 1, revision 20 in this example). Depending on the input data rate, the number of wires needed to carry the input data may be more than 1. If so, the integrator sections of the filter duplicate (vectorize) to satisfy the data rate requirement. Depending on the output data rate, the number of wires needed to carry the output data may be more than 1. If so, the output wires duplicate (vectorize) to satisfy the data rate requirement. The output data rate is the product of the input rate and the interpolation rate. Depending on the input data rate and interpolation factor the number of integrator stages needed to process the data may be more than 1. If so, the integrator sections of the filter duplicate (vectorize) to satisfy the data rate requirement. The width in bits of the (vectorized) data output from the filter. Each stage in the filter has precise width in bits requirementsN comb sections followed by N integrator sections. The gain through the CIC filter. CIC filters usually have large gains that you must scale back. In the comb section, the data rate is lower, so that you can perform more resource sharing. This message indicates the efficiency of the subtractor usage. In the integrator section, the data rate is higher, so that you can perform less resource sharing. This message indicates the efficiency of the adder usage. The latency that this block introduces. Lists the decimation rate, number of stages, differential delay, number of channels, clock frequency, and input sample rate parameters for the DecimatingCIC block.
Written on Tue Feb 19 11:25:27 2008 Date and time when this file ran.
Number of integrators: 2
Calculated output bit width: 26 Calculated stage bit widths: 17 18 19 20 20 20 22 23 24 26 Gain: 625 Comb section utilization: 20 cycles used of 50 available (40.00%) Integrator section utilization: 10 cycles used of 10 available (100.00%) Latency is 13 Parameters table
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Message Example Port interface table Input Data Format Output Data Format Resource utilization table
Description Lists the port interfaces for the DecimatingCIC block. Displays the input channel data format. Displays the output channel data format. Lists the resource utilization for the DecimatingCIC block.
Design Example
The demo_dcic and demo_ddc design examples include the DecimatingCIC block.
Decimating FIR
The Decimating FIR block implements a highly efficient multichannel finite impulse response filter across a broad range of parameters directly from a Simulink model. A memory-mapped interface allows you to read and write coefficients directly, easing system integration. The Decimating FIR block performs filtering on a stream of multichannel input data and produces a stream of output data with increased sampling frequency. You can use the Decimating FIR block in a digital down converter for a radio system or a general purpose DSP application. The coefficients and input data are fixed-point types, and the output is the implied full precision fixed-point type. You can reduce the precision by using a separate Scale block, which can perform rounding and saturation to provide the required output precision.
Features
The Decimating FIR block supports rate changes from 2 to 64, coefficient width in bits from 2 to 32 bits, half-band and L-band Nyquist filters, real and complex filters, symmetry and anti(negative)-symmetry.
Operation
Equation 31 on page 31 shows the basic convolution operation that a single-rate filter performs. At each sample time k, the new output y, is calculated by multiplying coefficients a, by the recent past values of the input x. The Decimating FIR has a lower output sample rate than the input sample rate by a factor, D, the decimation factor. The decimating FIR discards D1 out of D output samples, thus lowering the sample rate by a factor D. The physical implementation avoids performing multiplications with these zero samples, reducing the filter cost.
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Figure 34 on page 38 shows how decimating by 5 decreases the sample rate of a sine wave input.
Figure 34. Decimating by 5 Filter Decreasing Sample Rate of a Sine Wave Input
Parameters
Table 35 shows the parameters for the Decimating FIR block.
Table 35. Parameters for the Decimating FIR Block
Parameter Input rate per channel Decimation Number of channels Symmetry Coefficients
Description Specifies the sampling frequency of the input data per channel measured in millions of samples per second (MSPS). Specifies the decimation rate. Must be an integer. Specifies the number of unique channels to process. You can select Symmetrical or Anti-Symmetrical coefficients. Symmetrical coefficients can result in hardware resource savings over the unsymmetrical version. You can specify the filter coefficients using a Simulink fixed-point object fi(0). The data type of the fixed-point object determines the width and format of the coefficients. The length of the array determines the length of the filter. For example, fi(fir1(49, 0.3),1,18,19) You can memory map the filter's coefficients into the address space of the system. This field determines the starting address for the coefficients. It is specified as a MATLAB double type (decimal integer) but you can use a MATLAB expression to specify a hexadecimal or octal type if required. You can map the coefficients as Read, Write, Read/Write, or Constant. This field determines the type of address decode to build. You can select Use All Taps, Half Band, or other specified band (from 3rd Band to 46th Band).
Base address
Filter Coefficients
You can change filter coefficients at run time by writing to the memory-mapped interface. You do not need to create custom logic to deal with awkward update schemes.
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You can set the base address of the memory-mapped coefficients with the Base address parameter and set the filter coefficients by entering a Simulink fixed-point array into the Coefficients parameter. You can generate a vector of coefficients either by entering an array of numbers, or using one of the many MATLAB functions to build the required coefficients. f For more information about Simulink fixed-point objects and MATLAB functions, refer to the MATLAB Help.
Port Interface
Table 36 shows the port interface for the Decimating FIR block.
Table 36. Port Interface for the Decimating FIR Block
Signal Direction Description a v c q v c Input Input Input Output Output Output The data input to the block. If you request more channels than can fit on a single bus, this signal is a vector. The width in bits is inherited from the input wire. Indicates validity of the data input signals. If v is high, the data on the a wire is valid. Indicates channel of data input signals. If v is high, then c indicates which channel the data corresponds to. The data output from the block. If you request more channels than can fit on a single bus, this signal is a vector. The width in bits is a function of the input width in bits and the parameterization. Indicates validity of data output signals. (Note 1) Indicates channel of data output signals. (Note 1)
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Table 37. Stratix III Fitter Results for an Decimating FIR Number of Channels 32 32 32 32 Input Rate (MSPS) 5 5 5 5 Decimation Rate 2 2 5 5 Comb ALUTs 1,120 685 516 604 Logic 1818 Registers Multipliers 3,551 1,360 719 886 12 6 4 2 Block Memory Bits 3,264 46,784 70.720 46,240 Memory ALUTs 1,877 211 169 145 System Frequency Frequency Achieved (MHz) (MHz) 200 400 200 400 228 412 258 463
Updated Help
After you run a simulation, DSP Builder updates the help pages with specific information about each instance of a block. Table 38 shows some typical help messages that DSP Builder issues for the Decimating FIR block.
Table 38. Messages for the Decimating FIR Block
Message Example Written on Tue Feb 19 11:35:41 2008 Decimating Filter Version: $Revision: 1.111 $ Number of physical input buses: 1
Description Date and time when this file ran. The version number and revision for the Decimating FIR Filter (Version 1, revision 111 in this example). Depending on the input data rate, the number of wires needed to carry the input data may be more than 1. If so, the comb sections of the filter are duplicated (vectorized) to satisfy the data rate requirement. Depending on the output data rate, the number of data wires needed to carry the output data may be more than 1. If so, the output wires are duplicated (vectorized) to satisfy the data rate requirement. The output data rate is the product of the input rate and the interpolation rate. The number of different phases. The number of times that the design uses each multiplier per sample to reduce the implementation size. For some sample rates, stall the filter internally for several cycles. The number of cycles for active calculation shows with the number of cycles that the sample rate relative to the system clock frequency determines. When some filters are folded, there may be extra unused taps. The extra taps increase the filter length with no hardware resource increase. The latency introduced by this block. Lists the system clock, clock margin, input sample rate, number of coefficients, decimation rate, number of channels, and type of symmetry parameters. Lists the port interfaces to the Decimating FIR block. Displays the input channel data format. Displays the output channel data format. Lists the memory addresses for the FIR coefficient registers. Lists the resource utilization for the Decimating FIR block.
Calculated bit width of output stage: 26 The width in bits of the (vectorized) data output from the filter. Number of different phases: 1 Implementation Folding: 3 Filter Utilization: 48/50 (96.00%)
Tap Utilization: 25/27 (92.59%) Latency is 9 Parameters table Port interface table Input Data Format Output Data Format Memory interface Resource utilization table
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Design Example
The demo_fird, demo_fir_rrc, demo_fir_fractional, and demo_ddc design examples include the Decimating FIR block.
Features
The FractionalRateFIR block supports interpolation rate changes from 2 to 64, decimation rate changes from 2 to 64, rational fractional rate changes, coefficient width in bitss from 2 to 32 bits, half-band and L-band Nyquist filters, real and complex filters, and symmetry and anti(negative)-symmetry.
Operation
Equation 31 on page 31 shows the basic convolution operation that a single-rate filter performs. At each sample time, k, the new output y, is calculated by multiplying coefficients a, by the recent past values of the input x. The FractionalRateFIR has a modified output sample rate that differs from the input sample rate by a factor, I /D, where I is the interpolation rate and D is the decimation factor. Usually, the fractional rate interpolates by a factor I by inserting (I1) zeros before performing the filter operation. Then the FIR discards D1 out of D output samples, thus lowering the sample rate by a factor D. The filtering is performed as in Equation 31. The physical implementation avoids performing multiplications with these zero samples, reducing the filter cost. Figure 35 on page 312 shows how interpolating by 3 and decimating by 2 changes the sample rate of a sine wave input.
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Figure 35. Sample Rate of a Sine Wave Input Interpolated by 3 and Decimated by 2
Parameters
Table 39 shows the parameters for the FractionalRateFIR block.
Table 39. Parameters for the FractionalRateFIR Block
Parameter Input rate per channel Interpolation Decimation Number of channels Symmetry Coefficients
Description Specifies the sampling frequency of the input data per channel measured in millions of samples per second (MSPS). Specifies the interpolation rate. Must be an integer. Specifies the decimation rate. Must be an integer. Specifies the number of unique channels to process. You can select Symmetrical or Anti-Symmetrical coefficients. Symmetrical coefficients can result in hardware resource savings over the unsymmetrical version. You can specify the filter coefficients using a Simulink fixed-point object fi(0). The data type of the fixed-point object determines the width and format of the coefficients. The length of the array determines the length of the filter. For example, fi(fir1(49, 0.3),1,18,19). You can memory map the filter's coefficients into the address space of the system. This field determines the starting address for the coefficients. It is specified as a MATLAB double type (decimal integer) but you can use a MATLAB expression to specify a hexadecimal or octal type if required. You can map the coefficients as Read, Write, Read/Write, or Constant. This field determines the type of address decode to build. You can select Use All Taps, Half Band, or a specified band (from 3rd Band to 46th Band).
Base address
Filter Coefficients
You can change filter coefficients by writing to the memory-mapped coefficients. You do not need to create custom logic to deal with awkward update schemes.
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You can set the base address of the memory-mapped coefficients with the Base address parameter and set the filter coefficients by entering a Simulink fixed-point array into the Coefficients parameter. You can generate a vector of coefficients either by entering an array of numbers, or by using one of the many MATLAB functions to build the required coefficients. f For more information about Simulink fixed-point objects and MATLAB functions, refer to the MATLAB Help.
Port Interface
Table 310 shows the port interface for the FractionalRateFIR block.
Table 310. Port Interface for the FractionalRateFIR Block
Signal Direction Description a v c q v c Input Input Input Output Output Output The data input to the block. If you request more channels than can fit on a single bus, this signal is a vector. The width in bits is inherited from the input wire. Indicates validity of the data input signals. If v is high, the data on the a wire is valid. Indicates channel of data input signals. If v is high, then c indicates which channel the data corresponds to. The data output from the block. If you request more channels than can fit on a single bus, this signal is a vector. The width in bits is a function of the input width in bits and the parameterization. Indicates validity of data output signals. (Note 1) Indicates channel of data output signals. (Note 1)
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Table 311. Stratix III Fitter Results for a FractionalRateFIR Number of Channels 32 32 32 32 Input Rate (MSPS) 5 5 5 5 Decimation / interpolation rate 2/5 2/5 5/2 5/2 Comb ALUTs 1,319 942 773 526 Block System Frequency Logic 1818 Memory Memory Frequency Achieved Registers Multipliers Bits ALUTs (MHz) (MHz) 3,180 3,124 1,227 852 24 12 4 2 16,116 0 29,920 29,920 947 1,056 223 143 200 400 200 400 233 405 258 466
Updated Help
After you run a simulation, DSP Builder updates the help pages with specific information about each instance of a block. Table 312 shows some typical help messages that DSP Builder issues for the FractionalRateFIR block.
Table 312. Messages for the FractionalRateFIR Block
Message Example Written on Tue Feb 19 13:07:18 2008 Interpolating Decimating Filter Version: $Revision: 1.111 $ Number of physical input buses: 1
Description Date and time when this file ran. The version number and revision for the FractionalRateFIR Filter (Version 1, revision 111 in this example). Depending on the input data rate, the number of wires needed to carry the input data may be more than 1. If so, the comb sections of the filter are duplicated (vectorized) to satisfy the data rate requirement. Depending on the output data rate, the number of wires needed to carry the output data may be more than 1. If so, the output wires duplicate (vectorize) to satisfy the data rate requirement. The output data rate is the product of the input rate and the interpolation rate. The number of different phases. The number of times that the design uses each multiplier per sample to reduce the implementation size. For some sample rates, stall the filter internally for several cycles. The number of cycles for active calculation shows with the number of cycles that the sample rate relative to the system clock frequency determines. When some filters are folded, there may be extra unused taps. The extra taps increase the filter length with no hardware resource increase. The latency introduced by this block. Lists the system clock, clock margin, input sample rate, number of coefficients, interpolation rate, decimation rate, number of channels, and type of symmetry parameters for the FractionalRateFIR block. Lists the port interfaces to the FractionalRateFIR block. Displays the input channel data format. Displays the output channel data format. Lists the memory addresses for the FIR coefficient registers. Lists the resource utilization for the FractionalRateFIR block.
Calculated bit width of output stage: 26 The width in bits of the (vectorized) data output from the filter. Number of different phases: 1 Implementation Folding: 3 Filter Utilization: 48/50 (96.00%)
Port interface table Input Data Format Output Data Format Memory interface Resource utilization table
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Design Example
The demo_firf and demo_filters_flow_control design examples include the FractionalRateFIR block.
Interpolating CIC
The InterpolatingCIC block implements a highly efficient multichannel cascaded integrator-comb filter across a broad range of parameters directly from a Simulink model. The InterpolatingCIC block performs filtering on a stream of multichannel input data and produces a stream of output data with increased sampling frequency. You can use the InterpolatingCIC block in a digital up converter for a radio system or a general purpose DSP application. The coefficients and input data are fixed-point types, and the output is the implied full precision fixed-point type. You can reduce the precision by using a separate Scale block, which can perform rounding and saturation to provide the required output precision.
Features
The InterpolatingCIC block supports rate changes from 2 to 64.
Operation
The InterpolatingCIC has a higher output sample rate than the input sample rate by a factor I, where I is the interpolation rate. Usually, the InterpolatingCIC inserts (I1) zeros for every input sample, thus raising the sample rate by a factor I. Figure 36 shows how interpolating by 5 increases the sample rate of a sine wave input.
Figure 36. Interpolate by 5 Filter Increasing Sample Rate of a Sine Wave Input
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Parameters
Table 313 shows the parameters for the InterpolatingCIC block.
Table 313. Parameters for the InterpolatingCIC Block
Parameter Input rate per channel Number of channels Number of stages Interpolation factor Differential delay Final decimation
Description Specifies the sampling frequency of the input data per channel measured in millions of samples per second (MSPS). Specifies the number of unique channels to process. Specifies the number of comb and integrator stages. Specifies the interpolation factor. Must be an integer. Specifies the differential delay. You can optionally specify a final decimation by 2 to allow interpolation rates which are multiples of 0.5. The decimation works by simply throwing away data value. Only use this option to reduce the number of unique outputs the CIC generates.
Port Interface
Table 314 shows the port interface for the InterpolatingCIC block.
Table 314. Port Interface for the InterpolatingCIC Block
Signal a v c
Direction Description Input Input Input The data input to the block. If you request more channels than can fit on a single bus, this signal is a vector. The width in bits is inherited from the input wire. Indicates validity of the data input signals. If v is high, the data on the a wire is valid. Indicates channel of data input signals. If v is high, then c indicates which channel the data corresponds to. When this input is asserted, the input data is zero-stuffed and scaled by the gain of the filter. This option can be useful during hardware debug. The data output from the block. If you request more channels than can fit on a single bus, this signal is a vector. The width in bits is a function of the input width in bits and the parameterization. Indicates validity of data output signals. (Note 1) Indicates channel of data output signals. (Note 1)
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Table 315. Stratix III Fitter Results for a InterpolatingCIC Number of Channels 1 16 16 16 16 32 32 32 32 Input Rate (MSPS) 2 2 2 2 2 2 2 2 2 Interpolation Rate 10 25 25 10 10 25 25 10 10 Comb ALUTs 287 859 737 555 583 1,788 1,336 1,056 946 Block System Frequency Logic 1818 Memory Memory Frequency Achieved Registers Multipliers Bits ALUTs (MHz) (MHz) 771 2,563 2,540 1,490 1,556 4,946 4,582 2,705 2,587 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 758 436 392 234 1,604 916 828 490 400 200 400 200 400 200 400 200 400 471 236 409 303 450 221 408 278 426
Updated Help
After you run a simulation, DSP Builder updates the help pages with specific information about each instance of a block. Table 316 shows some typical help messages that DSP Builder issues for the InterpolatingCIC block.
Table 316. Messages for the InterpolatingCIC Block
Message Example Interpolating CIC Filter Version: $Revision: 1.20 $ Number of physical input buses / combs: 1 Number of physical output buses: 2
Description The version number and revision for the Interpolating CIC Filter (Version 1, revision 20 in this example). Depending on the input data rate, the number of wires needed to carry the input data may be more than 1. If so, the comb sections of the filter are duplicated (vectorized) to satisfy the data rate requirement. Depending on the output data rate, the number of wires needed to carry the output data may be more than 1. If so, the output wires are duplicated (vectorized) to satisfy the data rate requirement. The output data rate is the product of the input rate and the interpolation rate. Depending on the input data rate and interpolation factor the number of integrator stages needed to process the data may be more than 1. If so, the integrator sections of the filter are duplicated (vectorized) to satisfy the data rate requirement. The width in bits of the (vectorized) data output from the filter. Each stage in the filter has precise width in bits requirementsN comb sections followed by N integrator sections. The gain through the CIC filter. CIC filters usually have large gains that you must scale back. In the comb section, the data rate is lower, so that you can perform more resource sharing. This message indicates the efficiency of the subtractor usage. In the integrator section, the data rate is higher, so that you can perform less resource sharing. This message indicates the efficiency of the adder usage. The latency introduced by this block.
Written on Tue Feb 19 12:52:32 2008 Date and time when this file ran.
Number of integrators: 2
Calculated output bit width: 26 Calculated stage bit widths: 17 18 19 20 20 20 22 23 24 26 Gain: 625 Comb section utilization: 20 cycles used of 50 available (40.00%) Integrator section utilization: 10 cycles used of 10 available (100.00%) Latency is 16
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Description Lists the interpolation rate, number of stages, differential delay, number of channels, final decimation on output, clock frequency and input sample rate parameters for the InterpolatingCIC block. Lists the port interfaces to the InterpolatingCIC block. Displays the input channel data format. Displays the output channel data format. Lists the resource utilization for the InterpolatingCIC block.
Port interface table Input Data Format Output Data Format Resource utilization table
Design Example
The demo_icic, demo_filters_flow_control, demo_duc, and demo_AD9856 design examples include the InterpolatingCIC block.
Interpolating FIR
The InterpolatingFIR block implements a highly efficient multichannel finite impulse response filter across a broad range of parameters directly from a Simulink model. A memory-mapped interface allows you to read and write coefficients directly, easing system integration. The InterpolatingFIR block performs filtering on a stream of multichannel input data and produces a stream of output data with increased sampling frequency. You can use the InterpolatingFIR block in a digital up converter for a radio system or a general purpose DSP application. The coefficients and input data are fixed-point types, and the output is the implied full precision fixed-point type. You can reduce the precision by using a separate Scale block, which can perform rounding and saturation to provide the required output precision.
Features
The InterpolatingFIR block supports rate changes from 2 to 64, coefficient width in bits from 2 to 32 bits, data output width in bits from 4 to 64 bits, half-band and L-band Nyquist filters, symmetry and anti(negative)-symmetry, and real and complex filters.
Operation
Equation 31 on page 31 shows the basic convolution operation that a single-rate filter performs. At each sample time k, the new output y, is calculated by multiplying coefficients a, by the recent past values of the input x.
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The InterpolatingFIR has a higher output sample rate than the input sample rate by a factor, I, the interpolation factor. Usually, the interpolating FIR inserts I1 zeroes for every input sample, thus raising the sample rate by a factor I. The filtering is performed as in Equation 31. The physical implementation avoids performing multiplications with these zero samples, reducing the filter cost. Figure 37 shows how interpolating by 2 increases the sample rate of a sine wave input.
Figure 37. Interpolate by 2 Filter Increasing Sample Rate of a Sine Wave Input
Parameters
Table 317 shows the parameters for the InterpolatingFIR block.
Table 317. Parameters for the InterpolatingFIR Block
Parameter Input rate per channel Interpolation Number of channels Symmetry Coefficients
Description Specifies the sampling frequency of the input data per channel measured in millions of samples per second (MSPS). Specifies the interpolation rate. Must be an integer. Specifies the number of unique channels to process. You can select Symmetrical or Anti-Symmetrical coefficients. Symmetrical coefficients can result in hardware resource savings over the unsymmetrical version. You can specify the filter coefficients using a Simulink fixed-point object fi(0). The data type of the fixed-point object determines the width and format of the coefficients. The length of the array determines the length of the filter. For example, fi(fir1(49, 0.3),1,18,19). You can memory map the filter's coefficients into the address space of the system. This field determines the starting address for the coefficients. It is specified as a MATLAB double type (decimal integer) but you can use a MATLAB expression to specify a hexadecimal or octal type if required. You can map the coefficients as Read, Write, Read/Write, or Constant. This field determines the type of address decode to build. You can select Use All Taps, Half Band, or a specified band (from 3rd Band to 46th Band).
Base address
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Filter Coefficients
You can change filter coefficients at run time by writing to the memory-mapped interface. You do not need to create custom logic to deal with awkward update schemes. You can set the base address of the memory-mapped coefficients with the Base address parameter and set the filter coefficients by entering a Simulink fixed-point array into the Coefficients parameter. You can generate a vector of coefficients either by entering an array of numbers, or using one of the many MATLAB functions to build the required coefficients. f For more information about Simulink fixed-point objects and MATLAB functions, refer to the MATLAB Help.
Port Interface
Table 318 shows the port interface for the InterpolatingFIR block.
Table 318. Port Interface for the InterpolatingFIR Block
Signal Direction Description a v c q v c Input Input Input Output Output Output The data input to the block. If you request more channels than can fit on a single bus, this signal is a vector. The width in bits is inherited from the input wire. Indicates validity of the data input signals. If v is high, the data on the a wire is valid. Indicates channel of data input signals. If v is high, then c indicates which channel the data corresponds to. The data output from the block. If you request more channels than can fit on a single bus, this signal is a vector. The width in bits is a function of the input width in bits and the parameterization. Indicates validity of data output signals. (Note 1) Indicates channel of data output signals. (Note 1)
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Table 319. Stratix III Fitter Results for an InterpolatingFIR Number of Channels 16 32 32 32 32 Input Rate (MSPS) 5 5 5 5 5 Interpolation Rate 5 2 2 5 5 Comb ALUTs 367 1,899 1,050 1,604 683 Block System Frequency Logic 1818 Memory Memory Frequency Achieved Registers Multipliers Bits ALUTs (MHz) (MHz) 1,407 5,094 4,337 5,668 2,680 10 24 12 40 20 10,074 0 0 0 21,488 334 2,098 2,048 2,575 645 400 200 400 200 400 429 235 402 215 421
Updated Help
After you run a simulation, DSP Builder updates the help pages with specific information about each instance of a block. Table 320 shows some typical help messages that DSP Builder issues for the InterpolatingFIR block.
Table 320. Messages for the InterpolatingFIR Block
Message Example Written on Tue Feb 19 12:52:32 2008 Interpolating Filter Version: $Revision: 1.111 $ Number of physical input buses: 1
Description Date and time when this file ran. The version number and revision for the InterpolatingFIR Filter (Version 1, revision 111 in this example). Depending on the input data rate, the number of wires needed to carry the input data may be more than 1. If so, the comb sections of the filter are duplicated (vectorized) to satisfy the data rate requirement. Depending on the output data rate, the number of wires needed to carry the output data may be more than 1. If so, the output wires are duplicated (vectorized) to satisfy the data rate requirement. The output data rate is the product of the input rate and the interpolation rate. The number of different phases. The number of times that the design uses each multiplier per sample to reduce the implementation size. For some sample rates, stall the filter internally for several cycles. The number of cycles for active calculation shows with the number of cycles that the sample rate relative to the system clock frequency determines. When some filters are folded, there may be extra unused taps. The extra taps increase the filter length with no hardware resource increase. The latency introduced by this block. Lists the system clock, clock margin, input sample rate, number of coefficients, interpolation rate, number of channels, and type of symmetry parameters for the InterpolatingFIR block. Lists the port interfaces to the InterpolatingFIR block. Displays the input channel data format. Displays the output channel data format. Lists the memory addresses for the FIR coefficient registers. Lists the resource utilization for the InterpolatingFIR block.
Calculated bit width of output stages: 26 The width in bits of the (vectorized) data output from the filter. Number of different phases: 1 Implementation Folding: 3 Filter Utilization: 48/50 (96.00%)
Port interface table Input Data Format Output Data Format Memory interface Resource utilization table
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Design Example
The demo_firi, demo_firih, demo_fir_fractional, demo_filters_flow_control, demo_duc, demo_AD9856, and demo_wimax_duc design examples include the InterpolatingFIR block.
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Single-Rate FIR
The SingleRateFIR block implements a highly efficient multichannel finite impulse response filter across a broad range of parameters directly from a Simulink model. A memory-mapped interface allows you to read and write coefficients directly, easing system integration. The SingleRateFIR block performs filtering on a stream of multichannel input data and produces a stream of output data with increased sampling frequency. You can use the SingleRateFIR block in a digital up converter for a radio system or a general purpose DSP application. The coefficients and input data are fixed-point types, and the output is the implied full precision fixed-point type. You can reduce the precision by using a separate Scale block, which can perform rounding and saturation to provide the required output precision.
Features
The SingleRateFIR block supports sample rates from 1 to 500, coefficient width in bitss from 2 to 32 bits, half-band and L-band Nyquist filters, real and complex filters, and symmetry and anti(negative)-symmetry.
Operation
Equation 31 on page 31 shows the basic convolution operation that a single-rate filter performs.
Parameters
Table 321 shows the parameters for the SingleRateFIR block.
Table 321. Parameters for the Single-Rate FIR Block
Description Specifies the sampling frequency of the input data per channel measured in millions of samples per second (MSPS). Specifies the number of unique channels to process. You can select Symmetrical or Anti-Symmetrical coefficients. Symmetrical coefficients can result in hardware resource savings over the unsymmetrical version. You can specify the filter coefficients using a Simulink fixed-point object fi(0). The data type of the fixed-point object determines the width and format of the coefficients. The length of the array determines the length of the filter. For example, fi(fir1(49, 0.3),1,18,19) You can memory map the filter's coefficients into the address space of the system. This field determines the starting address for the coefficients. It is specified as a MATLAB double type (decimal integer) but you can use a MATLAB expression to specify a hexadecimal or octal type if required. You can map the coefficients as Read, Write, Read/Write, or Constant. This field determines the type of address decode to build.
Base address
Read/Write mode
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Filter Coefficients
You can change filter coefficients at run time by writing to the memory-mapped interface. You do not need to create custom logic to deal with awkward update schemes. You can set the base address of the memory-mapped coefficients with the Base address parameter and set the filter coefficients by entering a Simulink fixed-point array into the Coefficients parameter. You can generate a vector of coefficients either by entering an array of numbers or by using one of the many MATLAB functions to build the required coefficients. f For more information about Simulink fixed-point objects and MATLAB functions, refer to the MATLAB Help.
Port Interface
Table 322 shows the port interface for the SingleRateFIR block.
Table 322. Port Interface for the Single-Rate FIR Block
Signal Direction Description a v c q v c Input Input Input Output Output Output The data input to the block. If you request more channels than can fit on a single bus, this signal is a vector. The width in bits is inherited from the input wire. Indicates validity of the data input signals. If v is high, the data on the a wire is valid. Indicates channel of data input signals. If v is high, then c indicates the channel to which the data corresponds. The data output from the block. If you request more channels than can fit on a single bus, this signal is a vector. The width in bits is a function of the input width in bits and the parameterization. Indicates validity of data output signals. (Note 1) Indicates channel of data output signals. (Note 1)
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Table 323. Stratix III Fitter Results for a Single-Rate FIR Number of Channels 16 32 32 32 32 Input Rate (MSPS) 5 5 5 5 5 Number of Coefficients 47 40 40 47 47 Comb Block ALUTs Logic 1818 Memory (Note 1) Registers Multipliers Bits 569 1,505 713 1,784 823 1,280 3,787 2,202 4,351 2,554 6 20 10 24 12 15,776 0 41,038 0 48,603 System Frequency Memory Frequency Achieved ALUTs (MHz) (MHz) 171 1,377 472 1,615 576 400 200 400 200 400 442 235 409 239 413
Updated Help
After you run a simulation, DSP Builder updates the help pages with specific information about each instance of a block. Table 324 shows some typical help messages that DSP Builder issues for the SingleRateFIR block.
Table 324. Messages for the Single-Rate FIR Block
Message Example Written on Tue Feb 19 13:04:04 2008 Single Rate Filter Version: $Revision: 1.111 $ Number of physical input buses: 1
Description Date and time when this file ran. The version number and revision for the single-rate FIR Filter (Version 1, revision 111 in this example). Depending on the input data rate, the number of wires needed to carry the input data may be more than 1. If so, the comb sections of the filter are duplicated (vectorized) to satisfy the data rate requirement. Depending on the output data rate, the number of wires needed to carry the output data may be more than 1. If so, the output wires are duplicated (vectorized) to satisfy the data rate requirement. The output data rate is the product of the input rate and the interpolation rate. The number of different phases. The number of times that the design uses each multiplier per sample to reduce the implementation size. For some sample rates, stall the filter internally for several cycles. The number of cycles for active calculation shows with the number of cycles that the sample rate relative to the system clock frequency determines. When the design folds some filters, there may be extra unused taps. The extra taps increase the filter length with no hardware resource increase. The latency introduced by this block. Lists the system clock, clock margin, input sample rate, number of coefficients, number of channels, and type of symmetry parameters for the SingleRateFIR block. Lists the port interfaces to the SingleRateFIR block. Displays the input channel data format. Displays the output channel data format.
Calculated bit width of output stage: 26 The width in bits of the (vectorized) data output from the filter. Number of different phases: 1 Implementation Folding: 3 Filter Utilization: 48/50 (96.00%)
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Description Lists the memory addresses for the FIR coefficient registers. Lists the resource utilization for the SingleRateFIR block.
Design Example
The demo_firs, demo_AD9856, and demo_wimax_duc design examples include the SingleRateFIR block.
4. FFT Library
The FFT library contains the following blocks in the Common folder:
Complex Multiplier (ComplexMult) Complex Sample Delay (ComplexSampleDelay) Dual Twiddle Memory Negate Negate Parameterizable
Butterfly I (BFI) Butterfly II (BFII) Bit Reverse Core (BitReverseCore) Twiddle Generator
The blocks in the Radix 2 folder support a hardware oriented Radix-22 algorithm based on a twiddle factor decomposition technique using butterfly structures. The FFT library does not support the Simulink complex data-type or vectors.
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Parameters
The ComplexMult block has no parameters.
Port Interface
Table 41 shows the port interface for the ComplexMult block.
Table 41. Port Interface for the ComplexMult Block
Signal Direction Type ar ai wr wi zr zi Input Input Input Input Output Output Any fixed-point Type Any fixed-point Type Any fixed-point Type Any fixed-point Type Derived fixed-point Type (Note 1) Derived fixed-point Type (Note 1)
Description Real part of operand a Imaginary part of operand a Real part of operand w Imaginary part of operand w Real part of the result Imaginary part of the result
Design Example
The demo_fft16_radix2, demo_fft256_radix4, demo_fft_4096_natural, demo_ifft_8192_natural, demo_fft_4096_br, and demo_fft_8192_br design examples include the ComplexMult block.
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The block conveniently accepts two samples to support complex data streams and typically fully streaming FFT architectures use it. The output type of this block is normally inherited (using an internal rule) and the type propagates through your design automatically. However, if you use the ComplexSampleDelay block in a loop, you must specify the output type for at least one block in the loop as described in the following steps: 1. Click on the ComplexSampleDelay block with the right mouse button and select Look Under Mask to reveal that the block is implemented by two primitive blocks (Figure 41).
Figure 41. SampleDelay Blocks
2. Double click on each SampleDelay block and set the output data type mode with the parameters (refer to Sample Delay (SampleDelay) on page 750). DSP Builder warns you are attempting to change the parameters of a library block. Click OK to confirm this dialog box.
Parameters
Table 42 shows the parameters for the ComplexSampleDelay block.
Table 42. Parameters for the ComplexSampleDelay Block
Parameter Delay
Port Interface
Table 43 shows the port interface for the ComplexSampleDelay block.
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Signal Direction Type In1 In2 Out1 Out2 Input Input Output Output Inherited fixed-point type Inherited fixed-point type Inherited fixed-point type (same as In1) Inherited fixed-point type (same as In2)
Design Example
The demo_fft16_radix2, demo_fft256_radix4, demo_fft_4096_br, demo_fft_8192_br, demo_fft_4096_natural, and demo_ifft_8192_natural design examples include the ComplexSampleDelay block.
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Parameters
Table 44 shows the parameters for the DualTwiddleMemory block.
Table 44. Parameters for the DualTwiddleMemory Block
Description Specifies the number of points on the unit circle. Specifies the precision in bits of the twiddle factors.
Twiddle scaling exponent Specifies the fixed-point scaling factor of the complex twiddle factor.
Port Interface
Table 45 shows the port interface for the DualTwiddleMemory block.
Table 45. Port Interface for the DualTwiddleMemory Block
Signal k1 k2 r1 i1 r2 i2
Type Unsigned integer in range 0 to (N 1) Unsigned integer in range 0 to (N 1) Type determined by parameterization Type determined by parameterization Type determined by parameterization Type determined by parameterization
Description Desired twiddle factor index Desired twiddle factor index Real part of twiddle factor 1 Imaginary part of twiddle factor 1 Real part of twiddle factor 2 Imaginary part of twiddle factor 2
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Negate
The Negate block negates the input value. This operation is equivalent to a multiplication by (-1). The output of this block is of the same precision of the input, hence there is no protection against overflow when the input is the most negative value in that fixed-point type. A separate NegateParameterizable block has the same function but with a parameterizable interface for when you want to specify the input width in bits or scaling factor. 1 When the decimal point is out-of-range (for example, width in bits 16, with scaling 2-19) you must explicitly define the data type for the constant 0 to get the same output width in bits as the input.
Parameters
The Negate block has no parameters. Table 46 shows the parameters for the NegateParameterizable block.
Table 46. Parameters for the NegateParameterizable Block
Description Specifies the data width in bits. Specifies the scaling factor.
Port Interface
Table 47 shows the port interface for the Negate block.
Table 47. Port Interface for the Negate Block
Signal Direction Type x y Input Output Any fixed-point type Derived fixed-point type
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Negate Parameterizable
Refer to the description of the Negate block.
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Butterfly I (BFI)
The BFI block implements the butterfly I functionality associated with the Radix-22 fully streaming decimate in frequency FFT architecture. You should parameterize this block with the incoming data type to ensure that DSP Builder maintains the necessary data precision. At the output, DSP Builder applies an additional bit of growth. The s port connects to the control logic. This control logic is the extraction of the appropriate bit of a modulo N counter. The value of s determines the signal routing of each sample and the mathematical combination with other samples.
Parameters
Table 48 shows the parameters for the BFI block.
Table 48. Parameters for the BFI Block
Description Specifies the number of input bits. Specifies the fixed-point scaling factor of the input.
Port Interface
Table 49 shows the port interface for the BFI block.
Table 49. Port Interface for the BFI Block
Signal Direction Type s xr1 xl1 xr2 xl2 zr1 zl1 zr2 zl2 Input Input Input Input Input Output Output Output Output Boolean or unsigned integer uint(1) Type determined by parameterization Type determined by parameterization Type determined by parameterization Type determined by parameterization Type determined by parameterization Type determined by parameterization Type determined by parameterization Type determined by parameterization
Description Control pin. Input from ComplexSampleDelay. Input from ComplexSampleDelay. Input from previous stage. Input from previous stage. Output to next stage. Output to next stage. Output to ComplexSampleDelay. Output to ComplexSampleDelay.
Design Example
The demo_fft16_radix2, demo_fft256_radix4, demo_fft_4096_br, demo_fft_8192_br, demo_fft_4096_natural, and demo_ifft_8192_natural design examples include the BFI block.
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Butterfly II (BFII)
The BFII block implements the butterfly II functionality associated with the Radix-22 fully streaming decimate in frequency FFT architecture. You should parameterize this block with the incoming data type to ensure that DSP Builder maintains the necessary data precision. At the output, DSP Builder applies an additional bit of growth. The s port connects to the control logic. This control logic is the extraction of the appropriate bit of a modulo N counter. The value of s determines the signal routing of each sample and the mathematical combination with other samples. The t port also connects to the control logic, but the extracted bit is different from the s port. The value of t determines whether an additional multiplication by j occurs inside the butterfly unit.
Parameters
Table 410 shows the parameters for the BFII block.
Table 410. Parameters for the BFII Block
Description Specifies the number of input bits. Specifies the exponent part of the input scaling factor (2-exponent).
Port Interface
Table 411 shows the port interface for the BFII block.
Table 411. Port Interface for the BFII Block
Signal Direction Type s t xr1 xl1 xr2 xl2 zr1 zl1 zr2 zl2 Input Input Input Input Input Input Output Output Output Output Boolean Boolean Type determined by parameterization Type determined by parameterization Type determined by parameterization Type determined by parameterization Derived fixed-point type Derived fixed-point type Derived fixed-point type Derived fixed-point type
Description Control pin. Control pin. Input from ComplexSampleDelay. Input from ComplexSampleDelay. Input from previous stage. Input from previous stage. Output to next stage. Output to next stage. Output to ComplexSampleDelay. Output to ComplexSampleDelay.
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Design Example
The demo_fft256_radix4, demo_fft_4096_br, demo_fft_4096_natural, demo_fft_8192_br, and demo_ifft_8192_natural design examples include the BFII block.
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Parameters
Table 412 shows the parameters for the Bit Reverse block.
Table 412. Parameters for the Bit Reverse Block
Port Interface
Table 413 shows the port interface for the Bit Reverse block.
Table 413. Port Interface for the Bit Reverse Block
Signal Direction Type v c xr xi qv qc qr qi Input Input Input Input Output Output Output Output Boolean Unsigned 8-bit integer Any fixed-point type Any fixed-point type Boolean Unsigned 8-bit integer Any fixed-point type Any fixed-point type
Description Valid input signal. Channel input signal. Data input signal. Data input signal. Valid output signal. Channel output signal. Data output signal. Data output signal.
Design Example
The demo_fft_4096_br, demo_fft_8192_br, demo_fft_4096_natural, and demo_ifft_8192_natural design examples includes the BitReverseCore block.
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Twiddle Generator
The TwiddleGenerator block generates the appropriate sine or cosine coefficients that the streaming data multiplies in a radix-22 streaming FFT architecture. Feed at the input by a modulo N counter (where N is an integer power of two) and the appropriate complex sequence generates at the output. To parameterize this block, set the Counter bit width parameter with log2(N) and enter the width in bits and fixed-point scaling of the twiddle factors. A cosine or sine wave has a range of [-1:1], therefore you must provide at least two integer bits, and as many fractional bits as are appropriate. A good starting point is a twiddle bit width of 16 bits (enter 16 as the twiddle bit width), and a scaling of 214 (enter 14 as the Twiddle scaling exponent). The resulting fixed-point type is sfix16_en14 (2.14 fixed-point format).
Parameters
Table 414 shows the parameters for the TwiddleGenerator block.
Table 414. Parameters for the TwiddleGenerator Block
Parameter Counter bit width Twiddle bit width Twiddle scaling exponent value
Description Specifies the counter width in bits. Specifies the twiddle width in bits. Specifies the fixed-point scaling factor of the complex twiddle factor.
Port Interface
Table 415 shows the port interface for the TwiddleGenerator block.
Table 415. Port Interface for the TwiddleGenerator Block
Signal counter wr wi
Type Any fixed-point type Derived fixed-point type Derived fixed-point type
Design Example
The demo_fft_4096_br, demo_fft_8192_br, demo_fft_4096_natural, and demo_ifft_8192_natural design examples include the TwiddleGenerator block.
The Complex Mixer block does not support the Simulink complex data-type. The in phase (real), and quadrature (imaginary) signals are input and output as separate signals.
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Complex Mixer
The Complex Mixer block performs a complex by complex multiply on streams of data. This function frequency can shift a data stream in a digital up converter, where the first complex data is the i and q data and the second complex data is the cosine and sine data provided by an NCO. The Complex Mixer block multiplies a complex input stream by a synchronized complex data stream, sample by sample. You can use this block in a digital up converter for a radio system or a general purpose DSP application. The data has fixed-point types, and the output is the implied full precision fixed-point type.
Parameters
The Complex Mixer performs element-by-element multiplication on n channels and m frequencies. The system specification, including such factors as the channel count and sample rates, determines the main parameters for this block. The input sample rate of the block determines the number of channels present on each input wire and the number of wires:
Number of Channels per wire = Clock_Rate/Sample_Rate Number of Wires = ceiling(Chan_CountSample_Rate/Clock_Rate)
For example, a sample rate of 60 MSPS and system clock rate of 240 MHz gives four samples to be TDM on to each input wire. If there are more channels than TDM slots available on a wire, the input wire is a vector of sufficient width to hold all the samples. Similarly, the number of frequencies (the number of complex numbers) determines the width of the sine and cosine inputs. The number of results produced by the Complex Mixer is the product of the sample input vector and the frequency vector. The results are TDM on to the i and q outputs in a similar manner to the inputs. Table 51 shows the parameters for the Complex Mixer block.
Table 51. Parameters for the Complex Mixer Block
Description The number of complex input channels. The number of complex frequencies in the multiplier.
Input Rate Per Channel (MSPS) The data rate per channel measured in millions of samples per second.
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Port Interface
Table 52 shows the port interface for the Complex Mixer block.
Table 52. Port Interface for the Complex Mixer Block
Signal Direction Description i q v c sin cos i Input Input Input Input Input Input Output The real (in phase) half of the complex data input. If you request more channels than can fit on a single bus, this signal is a vector. The width in bits inherits from the input wire. The imaginary (quadrature phase) half of the complex data input. If you request more channels than can fit on a single bus, this signal is a vector. The width in bits inherits from the input wire. Indicates validity of data input signals. If v is high, the data on the a wire is valid. Indicates channel of data input signals. If v is high, c indicates the data channel data. The imaginary part of the complex number. For example, the NCO's sine output. The real part of the complex number. For example, the NCOs cosine output. The in-phase (real) output of the mixer, which is (i cos q sin). If you request more channels than can fit on a single bus, this signal is a vector. The width in bits is wide enough for the full precision result. The quadrature phase (imaginary) output of the mixer, which is (i sin + q cos). If you request more channels than can fit on a single bus, this signal is a vector. The width in bits is wide enough for the full precision result. Indicates validity of data output signals. Indicates channel of data output signals.
Output
v c
Output Output
The ComplexMixer block performs the multiplicaiton on corresponding components; the RealMixer block does not. The ComplexMixer block uses modulo indexing if one vector is shorter than another. Hence, the output vector width is the maximum of the widths of the input vectors. The RealMixer block performs a full outer product on the input vectors. The number of components in the output vector is the product of the width of the input vectors for sin and cos (must be the same) and the width of the input vector for a.
Updated Help
After you run a simulation, DSP Builder updates the help pages with specific information about each instance of a block. Table 53 shows some typical help messages that DSP Builder issues for the Complex Mixer block.
Table 53. Messages for the Complex Mixer Block
Description The latency introduced by this block. Lists the port interfaces to the Complex Mixer block. Lists the resource utilization for the Complex Mixer block.
Written on Tue Feb 19 11:25:27 2008 Date and time when this file ran.
Design Example
The demo_complex_mixer, demo_duc, demo_wimax_duc design examples include the Complex Mixer block.
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Real Mixer
The Real Mixer block performs a real by complex multiply on streams of data. This function creates quadrature data from an antenna input, where the real data is the antenna data and the complex data is the cosine and sine data provided by an NCO. The Real Mixer block multiplies a real input stream by a synchronized complex data stream, sample by sample. You can use the Real Mixer block in a digital down converter for a radio system or a general purpose DSP application. The data has fixed-point types, and the output is the implied full precision fixed-point type. Also refer to the ComplexMixer block (Complex Mixer on page 52).
Parameters
The Real Mixer performs element-by-element multiplication on n channels and m frequencies. The system specification, including such factors as the channel count and sample rates, determines the main parameters for this block. The input sample rate of the block determines the number of channels present on each input wire and the number of wires:
Number of Channels per wire = Clock_Rate/Sample_Rate Number of Wires = ceiling(Chan_CountSample_Rate/Clock_Rate)
For example, a sample rate of 60 MSPS and system clock rate of 240 MHz gives four samples to be TDM on to each input wire: If there are more channels than TDM slots available on a wire, the input wire is a vector of sufficient width to hold all the samples. Similarly, the number of frequencies (the number of complex numbers) determines the width of the sine and cosine inputs. The number of results that the Real Mixer produces is the product of the sample input vector and the frequency vector. The results are TDM on to the i and q outputs in a similar way to the inputs. Table 54 shows the parameters for the Real Mixer block.
Table 54. Parameters for the Real Mixer Block
Description The number of real input channels. The number of real frequencies in the multiplier.
Input Rate Per Channel (MSPS) The data rate per channel measured in millions of samples per second.
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Port Interface
Table 55 shows the port interface for the Real Mixer block.
Table 55. Port Interface for the Real Mixer Block
Signal Direction Description a v c sin cos i q Input Input Input Input Input Output Output The real data input to the block. If you request more channels than can fit on a single bus, this signal is a vector. The width in bits is inherited from the input wire. Indicates validity of data input signals. If v is high, the data on the a wire is valid. Indicates channel of data input signals. If v is high, c indicates the data channel. The imaginary part of the complex number. For example, the NCO's sine output. The real part of the complex number. For example, the NCOs cosine output. The in-phase (real) output of the mixer, which is (a cos). If you request more channels than can fit on a single bus, this signal is a vector. The width in bits is wide enough for the full precision result. The quadrature phase (imaginary) output of the mixer, which is (a sin). If you request more channels than can fit on a single bus, this signal is a vector. The width in bits is wide enough for the full precision result. Indicates validity of data output signals. Indicates channel of data output signals.
v c
Output Output
Updated Help
After you run a simulation, DSP Builder updates the help pages with specific information about each instance of a block. Table 56 shows some typical help messages that DSP Builder issues for the Real Mixer block.
Table 56. Messages for the Real Mixer Block
Description The latency introduced by this block. Lists the port interfaces for the Mixer block. Lists the resource utilization for the Mixer block.
Written on Tue Feb 19 11:25:27 2008 Date and time when this file ran.
Design Example
The demo_ddc and demo_mix design examples include the Real Mixer block.
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NCO
A numerically controlled oscillator (NCO) or digitally controlled oscillator (DCO) is an electronic system for synthesizing a range of frequencies from a fixed time base. NCOs are useful when a continuous phase sinusoidal signal with variable frequency is required, such as when receiving the signal from a NCO-based transmitter in a communications system. The NCO block uses an octant-based algorithm with trigonometric interpolation. The basic operation the NCO performs is to accumulate a phase angle in an accumulator. DSP Builder uses this angle as a lookup into sine and cosine tables to find a coarse sine and cosine approximation. DSP Builder implements the tables with a ROM. A Taylor series expansion of the small angle errors refines this coarse approximation to produce accurate sine and cosine values. The NCO block uses folding to produce multiple sine and cosine values if the sample rate is an integer fraction of the system clock rate. You can use this block in a digital up or down converter for a radio system or a general purpose DSP application. The coefficients and input data are fixed-point types, and the output is the implied full precision fixed-point type. An NCO sometimes needs to synchronize its phase to an exact cycle. It uses the phase and sync inputs for this purpose. The sync input is a write enable for the channel (address) specified by the chan input when the new phase value (data) is available on the phase input. You may need some external logic (which you can implement as a primitive subsystem) to drive these signals. For example, you can prepare a sequence of new phase values in a shared memory and then write all the values to the NCO on a synchronization pulse. This option is particularly useful if you want an initial phase offset in the upper sinusoid. You can also use this option to implement efficient phase-shift keying (PSK) modulators in which the input to the phase modulator varies according to a data stream.
Parameters
The system specification, including such factors as the channel count, sample rates, and noise floor, determines the main parameters for this block. You can express all the parameters as MATLAB expressions, making it easy to parameterize a complete system. The hardware generation techniques create very efficient NCOs, which are fast enough to update with every Simulink simulation, so the edit-simulation loop time is much reduced, improving productivity. Table 57 shows the specification parameters for the NCO block.
Table 57. Specification Parameters for the NCO Block
Description The sine and cosine output rate per channel measured in millions of samples per second.
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Description The output width in bits of the NCO. The bit width controls the internal precision of the NCO. The spurious-free dynamic range (SFDR) of the waves produced is approximately 6.02 bit width. The 6.02 factor comes from the definition of decibels with each added bit of precision increasing the SFDR by a factor of 20log10(2). This value interprets the output data in the Simulink environment. The power of 2 scaling provided lets you specify the range of the output value. Specifies the width of the memory-mapped accumulator bit width, which governs the precision you can control the NCO frequency. The width is limited to the range 1530 for use with a 32-bit memory map (shared by other applications such as a Nios II processor). The top two bits in the 32-bit width are reserved to control the inversion of the sine and cosine outputs. A width of 30 bits gives an accumulator precision of 0.02794 Hz. However, you can select Constant for the Read/Write Mode to allow the width to increase to 40 bits. This width results in an accumulator precision of 0.000027 MHz. A vector that represents the step in phase between each sample. This vector controls the frequencies generated during simulation. The length of the vector determines how many channels (frequencies) of data are generated from the NCO. The unit of the vector is one (sine or cosine) cycle. For information about using this parameter, refer to Phase Increment and Inversion.
Phase Increment and Specifies where in the memory-mapped space the NCO registers are mapped. For information Inversion Memory Map about using this parameter, refer to Phase Increment Memory Registers. Read/Write Mode Specifies whether the NCO phase increment and inversion registers are mapped as Read, Write, Read/Write, or Constant.
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When the input is in matrix format (with multiple rows of vectors), the design configures the NCO block as a multi-bank NCO for frequency hopping for multi-carrier designs. The number of rows in the matrix represents the number of banks of frequencies (of sine and cosine waves) that generate for a given channel. An additional bank input and b output port automatically add to the NCO block. 1 There is no upper limit to the number of rows in the matrix and you can specify any number of frequency banks. However, you should carefully monitor the resource usage to ensure that the specified design fits into the target device. You can also use the Phase Increment and Inversion parameter to indicate whether the generated sinusoidal signals are inverted. For an accumulator width in bits of 24 bits, you can add two bits (the 25th and 26th bits) to the phase increment value for a given frequency. These bits indicate if the sine (26th bit) and cosine (25th bit) are inverted.
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To minimize the duration of disruption, you may use two banks of phase increment registers. The new phase increment registers bank switches first. Then, you can apply the sync pulse to synchronize the new phase offsets.
Frequency Hopping
You can use the NCO block to configure multiple banks of predefined frequencies for frequency hopping. If you specify a matrix comprising multiple rows of vectors as the Phase Increment and Inversion values, DSP Builder configures the NCO for multiple banks and defines the number of banks by the number of rows of vectors specified by inputs to the Phase Increment and Inversion parameter. A bank input and b output are automatically added to the NCO block. It also allocates phase increment memory registers for the multiple banks of frequencies automatically. You can use the Avalon-MM interface to access (read or write) the phase increment memory registers in the same way as for a single bank with the register address for the ith bank frequencies starting from: <base address> + (i -1) <number of registers per value> <number of channels>. You can use the bank input as the index to switch the generated sinusoidal waves to the specified set (bank) of predefined frequencies. 1 Ensure you constrain the bank input to the range (0 .. <number of banks> -1). You can expect unreliable outputs from the NCO block if the bank input exceeds the number of banks. When using an Avalon-MM interface to access (read or write) the phase increment memory registers, ensure that you only write to the inactive banks (banks which are not equal to the index specified by the input bank port). The dual-port memory that the NCO block uses is in DONT_CARE mode when reading and writing to the same address. The NCO block uses the active bank to read the phase increment value. Writing to the active bank may cause unreliable values to read out and the active bank may pass out unexpected sinusoidal signals through the memory interface. The read data, from the address to which you write the new values to, may also be unreliable because of the memory type that the NCO block uses. Only use read data from banks where they do not write to at the same time.
Results Tab
The Results tab shows the implications of your parameter settings. Table 58 describes the parameters in the Results tab.
Table 58. Results Tab Parameters for the NCO Block
Parameter Expected SFDR Accumulator precision Frequency # outputs per cycle log2 of look-up table
Description The SFDR in decibels relative to the carrier (dBc): (Output Data Type Width) 20 log10(2). Accumulator precision in Hz: 106 (output rate) / 2(accumulator width in bits+1). Frequency in MHz: (output rate) (phase increment and inversion) / 2(accumulator width in bits). The number of outputs per cycle is the width of the vector of output signals: physical channels out = ceil(length(phase increment and inversion)) / ((system clock frequency) / (output rate))) The number of address bits in the internal look-up tables.
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Port Interface
Table 59 shows the port interface for the NCO block.
Table 59. Port Interface for the NCO Block
Direction Description Input Input Input Indicates the channel. If v is high, then chan indicates which channel the data corresponds to. Indicates validity. If v is high, then new data generates. Specifies the phase offset. The size of this port should match the wire count of the NCO. (Note 1) Specifies the phase synchronization. The size of this port should match the wire count of the NCO output. When asserted, the phase offsets of all channels synchronize to the phase inputs. This signal has no effect to the phase increment and inversion registers. When you use this signal, you may need to initialize the offsets upon system power-up or reset. (Note 1) This input is available when you specify a matrix of predefined vectors for the phase increment values. You can use this input to switch to the bank of predefined frequencies. For information about using this signal, refer to Frequency Hopping on page 59. The sine data output from the block. If you request more channels than can fit on a single bus, this signal is a vector. The width in bits is a function of the input width in bits and the parameterization. The cosine data output from the block. If you request more channels than can fit on a single bus, this signal is vector. The width in bits is a function of the input width in bits and the parameterization. (Note 1) Indicates validity of the data output signals. Indicates channel of the data output signals. Indicates the bank that the output signals use. This output is available when you specify a matrix of predefined vectors for the phase increment values.
phase Input
bank
Input
sin cos
Output Output
v c b
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Table 510. Stratix III Fitter Results for a NCO Input Number of Rate Accumulator Frequencies (MSPS) Width 4 4 4 100 50 100 22 26 26 Comb ALUTs 319 298 370 Block System Frequency Logic 1818 Memory Memory Frequency Achieved Registers Multipliers Bits ALUTs (MHz) (MHz) 851 600 981 4 4 4 9,344 9,344 9,344 89 76 95 400 200 400 467 337 461
Updated Help
After you run a simulation, DSP Builder updates the help pages with specific information about each instance of a block. Table 511 shows some typical help messages that DSP Builder issues for the NCO block.
Table 511. Messages for the NCO Block
Description The latency introduced by this block. Lists the port interfaces to the NCO block. Lists the resource utilization for the NCO block.
Written on Tue Feb 19 11:25:27 2008 Date and time when this file ran.
Design Example
The demo_nco, demo_ddc, demo_duc, demo_AD9856 and demo_wimax_duc design examples include the NCO block.
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6. ModelBus Library
Bus Slave (BusSlave) Bus Stimulus (BusStimulus) Bus Stimulus File Reader (Bus StimulusFileReader) Register Bit (RegBit) Register Field (RegField) Register Out (RegOut) Shared Memory (SharedMem)
The ModelBus library does not support the Simulink complex data-type or vectors.
Parameters
Table 61 shows the parameters for the BusSlave block.
Table 61. Parameters for the BusSlave Block Parameter Memory Name Read/Write Mode Description Specifies the memory region. Can be an expression but must evaluate to an integer address. Specifies the mode of the memory as viewed from the processor:
Read: processor can only read over specified address range. Write: processor can only write over specified address range. Read/Write: processor can read or write over specified address range. Constant: processor cannot access specified address range. This option continues to reserve space in the memory map.
Specifies the address range that htis block accesses. Text describing what is at the specified address.
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Evaluated Address Displays the evaluated value of the Memory Name expression when you click Apply. Expression Sample Time Specifies the Simulink sample time.
Port Interface
Table 62 shows the port interface for the BusSlave block.
Table 62. Port Interface for the BusSlave Block Signal Direction Type rd rv a d w Input Input Output Output Output 16-bit or 32-bit unsigned integer Boolean Derived fixed-point type 16-bit or 32-bit unsigned integer Boolean Description Read data. Read data valid. Bus address. Write data. Write enable.
Parameters
Table 63 shows the parameters for the BusStimulus block.
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Port Interface
Table 64 shows the port interface for the BusStimulus block.
Table 64. Port Interface for the BusStimulus Block
Direction Type Input Input Input Output Output Unsigned integer 16-bit or 32-bit unsigned integer Boolean 16-bit or 32-bit unsigned integer Boolean
Description Address to access. Write data. Write enable. Read data. Read data valid.
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Bus stimulus files automatically write to any blocks that have processor mapped registers when you simulate a design. Any design with useful register files generates a bus stimulus file that you can use to bring your design out of reset (all registers 0). You can also write your own bus stimulus files with the following format: MemSpace Address WriteData WE ExpReadData Mask where MemSpace specifies the memory space (the format supports multiple memory spaces). Address is the word address. WriteData is the data to write if any. WE performs a write when 1. ExpReadData is the expected read data. The value that is read from a location is checked against this value to allow self checking tests. Mask specifies when the expected read data is checked, only the bits in this mask are checked, to allows you to read, write, or check specified bits in a register. During simulation, any mismatch between the expected read data (as the bus stimulus file describes) and the incoming read data (as the BusStimulus block provides) highlights and DSP Builder issues a warning.
Parameters
Table 65 shows the parameters for the BusStimulusFileReader block.
Table 65. Parameters for the BusStimulusFileReader Block
Parameter Enabled Log File Name Space Width Addr Width Data Width Sample Time
Description Turn on to enable reading of the bus stimulus file data. Specifies the file to store a log of all attempted bus stimulus accesses. Specifies the width of the memory space as described in the bus stimulus filemust be the same as the width specified in the Control block. Specifies the width of the address space as described in the bus stimulus filemust be the same as the width specified in the Control block. Specifies the width of the data as described in the bus stimulus filemust be the same as the width specified in the Control block. Specifies the Simulink sample time.
Stimulus File Name Specifies the file from which to read bus stimulus data.
Port Interface
Table 66 shows the port interface for the BusStimulusFileReader block.
Table 66. Port Interface for the BusStimulusFileReader Block
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Direction Type Output Output Output Output Output Output Output Unsigned integer Unsigned integer Boolean
Description Memory space from file. Address from file. Write signal from file.
16-bit or 32-bit unsigned integer Data from file. 16-bit or 32-bit unsigned integer Expected read data from file. 16-bit or 32-bit unsigned integer Mask value from file. Boolean Boolean Indicates when the readexpected and mask signals should be checked against readdata. Generated signal to indicate when the end of the bus stimulus file is reached.
endofstimulus Output
Parameters
Table 67 shows the parameters for the RegBit block.
Table 67. Parameters for the RegBit Block
Description Specifies the address of the register. Must evaluate to an integer address. Specifies the mode of the memory as viewed from the processor:
Read: processor can only read over specified address range. Write: processor can only write over specified address range. Read/Write: processor can read or write over specified address range. Constant: processor cannot access specified address range. This option continues to reserve space in the memory map.
Specifies the bit location of the memory-mapped register in a processor word (allows different registers to share same address). Specifies the initial state of the register. Text describing the register. The description is propagated to the generated memory map. Specifies the Simulink sample time.
Port Interface
Table 68 shows the port interface for the RegBit block.
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Description Data.
Design Example
The demo_regs, demo_ddc and demo_duc design examples include the RegBit block.
Parameters
Table 69 shows the parameters for the RegField block.
Table 69. Parameters for the RegField Block
Description Specifies the address of the register. Must evaluate to an integer address. Specifies the mode of the memory as viewed from the processor:
Read: processor can only read over specified address range. Write: processor can only write over specified address range. Read/Write: processor can read or write over specified address range. Constant: processor cannot access specified address range. This option continues to reserve space in the memory map.
Most Significant Bit Least Significant Bit Register Output Type Register Output Scale Initial Value Description Modal Behavior Sample Time
Specifies the MSB of the memory-mapped register in a processor word (allows different registers to share same address). Specifies the LSB of the memory-mapped register in a processor word (allows different registers to share same address). Specifies the width and sign of the data type that the register stores. The size should equal (MSB LSB + 1). Specifies the scaling of data type that the register stores. For example. 215 for 15 of the above bits as fractional bits. Specifies the initial state of the register. Text describing the register. The description is propagated to the generated memory map. Turn on this option if you want to enable modal behavior. Specifies the Simulink sample time.
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Port Interface
Table 610 shows the port interface for the RegField block.
Table 610. Port Interface for the RegField Block
Description Data.
Design Example
The demo_regs, demo_agc, demo_ddc, and demo_duc design examples include the RegField block.
Parameters
Table 611 shows the parameters for the RegOut block.
Table 611. Parameters for the RegOut Block
Description Specifies the address of the register. Must evaluate to an integer address. Specifies the mode of the memory as viewed from the processor:
Read: processor can only read over specified address range. Write: processor can only write over specified address range. Read/Write: processor can read or write over specified address range. Constant: processor cannot access specified address range. This option continues to reserve space in the memory map.
Most Significant Bit Least Significant Bit Description Modal Behavior Sample Time
Specifies the MSB of the memory-mapped register in a processor word (allows different registers to share same address). Specifies the LSB of the memory-mapped register in a processor word (allows different registers to share same address). Text describing the register. The description is propagated to the generated memory map. Turn on if you want to enable modal behavior. Specifies the Simulink sample time.
Port Interface
Table 612 shows the port interface for the RegOut block.
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Design Example
The demo_regs design example include the RegOut block.
Parameters
Table 613 shows the parameters for the SharedMem block.
Table 613. Parameters for the SharedMem Block
Description Specifies the address of the memory block. Must evaluate to an integer address. Specifies the mode of the memory as viewed from the processor:
Read: processor can only read over specified address range. Write: processor can only write over specified address range. Read/Write: processor can read or write over specified address range. Constant: processor cannot access specified address range. This option continues to reserve space in the memory map.
Initial Data
Specifies the initialization data. The size of the 1-D array determines the memory size.
Initialize Hardware Turn on when you want to initialize the generated HDL with the specified initial data. Memory Blocks with Initial Data Contents Description Memory Output Type Memory Output Scale Sample Time Text describing the memory block. The description is propagated to the generated memory map. Specifies the data type that the memory block stores. Specifies the scale factor to apply to the data stored in the memory block. Specifies the Simulink sample time.
Port Interface
Table 614 shows the port interface for the SharedMem block.
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Signal Direction Type a wd we rd Input Input Input Output Unsigned integer Any fixed-point type Boolean Any fixed-point type
Design Example
The demo_regs and demo_agc design examples include the SharedMem block.
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7. ModelPrim Library
Absolute Value (Abs) Add Add SLoad (AddSLoad) AND Gate (And) Bit Combine (BitCombine) Bit Extract (BitExtract) Bit Reverse (BitReverse) Channel In (ChannelIn) Channel Out (ChannelOut) Compare Equality (CmpEQ) Compare Greater Than (CmpGE) Compare Less Than (CmpLT) Compare Not Equal (CmpNE) Complex Conjugate (ComplexConjugate) Constant (Const) Convert CORDIC Counter Count Leading Zeros (CLZ) Delay Dual Memory (DualMem) FIFO General Purpose Input (GPIn) General Purpose Output (GPOut) Left Shift (LShift) Look-Up Table (Lut) Loop Maximum Value (Max) Minimum Value (Min) Multiply (Mult) Multiplexer (Mux)
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NAND Gate (Nand) NOR Gate (Nor) NOT Gate (Not) OR Gate (Or) Sample Delay (SampleDelay) Select Sequence Shift Subtract (Sub) Synthesis Information (SynthesisInfo) XNOR Gate (Xnor) XOR Gate (Xor)
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Drive the block with a vector signal. Initialize the block with a vector of values. This option is only available for blocks that you can initialize with a user-specified value.
Vector signals must be of uniform type. Signals associated with a block must either be vectors of identical width, or scalar.
When you use a scalar value with vectors, DSP Builder uses a copy of the single scalar value with each data element in the vector signal. This behavior is analogous to the scalar expansion that occurs with Simulink blocks.
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The outputs of these blocks are potentially a function of any or all of the inputs. Vector width does not necessarily propagate. The SumOfElements block exhibits this behavior.
Complex Support
Some blocks can automatically process complex data, which provides a convenient way to simultaneously generate data and control pathways for the real and imaginary components of such data. For each complex value, two identical block instantiations generate internally, for the real and imaginary components. The complex nature of the data propagates. Strictly real signals expand to provide a value for the imaginary component with complex data. The exact behavior depends on the nature of the port associated with the real signal. The real value is duplicated for control or address signals. The real and imaginary parts of complex data are subject to identical control signals. A zero imaginary value generates for real data signals in a complex data context. Real data values, x, expand, when required, to x + 0i.
Restrictions
Not all primitive blocks support complex data. Data signals are the only signal type permitted to be complex. DSP Builder issues an error message if an attempt is made to drive control or address signals with complex values.
Simulink Complex to Real-Imag and Real-Imag to Complex blocks may manipulate complex signals within DSP Builder advanced blockset designs. Simulink Scope blocks can display signals, but they do not directly support complex data. Attempting to view complex data generates a type propagation error.
Use a Complex to Real-Imag block to convert the complex signal. You can use the complex Simulink function complex(x,y) to generate initialization values. Use this function to ensure DSP Builder always treats data as complex. Simulink automatically converts complex values of form (x + 0i) to real values, which can cause type propagation errors. The complex() function can resolve this problem. Use complex (x,0) to ensure such data is treated as complex.
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Parameters
Table 71 shows the parameters for the Abs block.
Table 71. Parameters for the Abs Block
Description Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Inherit via internal rule with word growth: the number of fractional bits is the maximum of the number of fractional bits in the input data types. The number of integer bits is the maximum of the number of integer bits in the input data types plus one. This additional word growth allows for subtracting the most negative number from 0, which exceeds the maximum positive number that the number of bits of the input can store. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15.
(1) If you use the Abs block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 72 shows the port interface for the Abs block.
Table 72. Port Interface for the Abs Block
Signal Direction Type a q Input Output Any fixed-point type Derived fixed-point type
Design Example
The demo_agc design example includes the Abs block.
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Add
The Add block outputs the sum of the inputs:
q = a + b
If there are two or more inputs, the Add block outputs the sum of the inputs: q = a + b + ... For a single vector input, the Add block outputs the sum of elements: q = an For a single scalar input, the Add block outputs the input value: q=a
Parameters
Table 73 shows the parameters for the Add block.
Table 73. Parameters for the Add Block
Description Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Inherit via internal rule with word growth: the number of fractional bits is the maximum of the number of fractional bits in the input data types. The number of integer bits is the maximum of the number of integer bits in the input data types plus one. This additional word growth allows for subtracting the most negative number from 0, which exceeds the maximum positive number that you can store in the number of bits of the input. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15. Specifies the number of inputs.
(1) If you use the Add block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 74 shows the port interface for the Add block.
Table 74. Port Interface for the Add Block
Description Operand 1
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Signal Direction Type b q Input Output Any fixed-point type Derived fixed-point type
Vector Data Support Yes Yes (scalar output in one input case).
Design Example
The demo_agc, demo_fibonacci, demo_idct8x8, demo_iir, demo_QAM256, demo_regs, and demo_duc design examples include the Add block.
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If the s input is low, output the sum of the first 2 inputs, a + b, else if s is high, then output the value v.
Parameters
Table 75 shows the parameters for the AddSLoad block.
Table 75. Parameters for the AddSLoad Block
Description Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Inherit via internal rule with word growth: the number of fractional bits is the maximum of the number of fractional bits in the input data types. The number of integer bits is the maximum of the number of integer bits in the input data types plus one. This additional word growth allows for subtracting the most negative number from 0, which exceeds the maximum positive number that you can store in the number of bits of the input. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15.
(1) If you use the AddSLoad block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 76 shows the port interface for the AddSLoad block.
Table 76. Port Interface for the AddSLoad Block
Signal Direction Type a b s v q Input Input Output Output Output Any fixed-point type Any fixed-point type Any fixed-point type Any fixed-point type
Design Example
The demo_duc design example includes the AddSLoad block.
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Parameters
Table 77 shows the parameters for the And block.
Table 77. Parameters for the And Block
Description Specifies the number of inputs. Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15.
(1) If you use the And block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 78 shows the port interface for the And block.
Table 78. Port Interface for the And Block
Signal unnamed q
Direction Type Input Output Any fixed-point type Derived fixed-point type
Design Example
The demo_duc design example includes the And block.
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Parameters
Table 79 shows the parameters for the BitCombine block.
Table 79. Parameters for the BitCombine Block
Description Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15.
(1) If you use the BitCombine block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 710 shows the port interface for the BitCombine block.
Table 710. Port Interface for the BitCombine Block
Signal Direction Type i h q Input Input Output Any fixed-point type Any fixed-point type
Design Example
The demo_idct8x8 and demo_QAM256 design examples include the BitCombine block.
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If bit position is a negative number, the bit position is an offset from the MSB instead of LSB.
Parameters
Table 711 shows the parameters for the BitExtract block.
Table 711. Parameters for the BitExtract Block
Description Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Output data type Output scaling value Least Significant Bit Position from Input Word
Note to Table 711:
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15. Specifies the bit position from the input word as the LSB in the output word.
(1) If you use the BitExtract block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 712 shows the port interface for the BitExtract block.
Table 712. Port Interface for the BitExtract Block
Description Operand
Design Example
The demo_agc, demo_fft16_radix2, demo_fft256_radix4, demo_fft_4096_br, demo_fft_8192_br, demo_idct8x8, demo_fft_4096_natural, demo_ifft_8192_natural, demo_QAM256, demo_regs, and demo_duc design examples include the BitExtract block.
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Parameters
The BitReverse block has no parameters.
Port Interface
Table 713 shows the port interface for the BitReverse block.
Table 713. Port Interface for the BitReverse Block
Description Operand
Design Example
The demo_fft16_radix2 and demo_fft256_radix4 design examples include the BitReverse block.
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Channel In (ChannelIn)
The ChannelIn block delineates the input boundary of a synthesizable primitive subsystem. The ChannelIn block passes its input through to the outputs unchanged, with types preserved. This block indicates to DSP Builder that these signals arrive synchronized from their source, so that the synthesis tool can interpret them.
Parameters
Table 714 shows the parameters for the ChannelIn block.
Table 714. Parameters for the ChannelIn Block
Port Interface
Table 715 shows the port interface for the ChannelIn block.
Table 715. Port Interface for the ChannelIn Block
Signal v c
Direction Type Input Input Boolean uint(8) Any fixed-point type Boolean uint(8) Any fixed-point type
Description Valid input signal Channel input signal A number of input data signals Valid signal Channel signal A number of data signals
0, 1, 2, ... Output
Design Example
The demo_agc, demo_fft16_radix2, demo_fft256_radix4, demo_fft_4096_br, demo_fft_8192_br, demo_fibonacci, demo_idct8x8, demo_fft_4096_natural, demo_ifft_8192_natural, demo_iir, demo_AD9856, and demo_duc design examples include the ChannelIn block.
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Parameters
Table 716 shows the parameters for the ChannelOut block.
Table 716. Parameters for the ChannelOut Block
Port Interface
Table 717 shows the port interface for the ChannelOut block.
Table 717. Port Interface for the ChannelOut Block
Signal v c
Direction Type Input Input Boolean 8-bit unsigned integer Any fixed-point type Boolean 8-bit unsigned integer Any fixed-point type
Description Valid output signal Channel output signal A number of output data signals Valid signal Channel signal A number of data signals
0, 1, 2, ... Output
Design Example
The demo_agc, demo_fft16_radix2, demo_fft256_radix4, demo_fft_4096_br, demo_fft_8192_br, demo_fibonacci, demo_idct8x8, demo_fft_4096_natural, demo_ifft_8192_natural, demo_iir, demo_AD9856, and demo_duc design examples include the ChannelOut block.
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Parameters
Table 73 shows the parameters for the ComplexConjugate block.
Table 718. Parameters for the ComplexConjugate Block
Description Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Inherit via internal rule with word growth: the number of fractional bits is the maximum of the number of fractional bits in the input data types. The number of integer bits is the maximum of the number of integer bits in the input data types plus one. This additional word growth allows for subtracting the most negative number from 0, which exceeds the maximum positive number that you can store in the number of bits of the input. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15. Specifies the number of inputs.
Port Interface
Table 719 shows the port interface for the ComplexConjugate block.
Table 719. Port Interface for the ComplexConjugate Block
Signal Direction Type a q Input Output Any fixed-point type Derived fixed-point type
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Parameters
The CmpEQ block has no parameters.
Port Interface
Table 720 shows the port interface for the CmpEQ block.
Table 720. Port Interface for the CmpEQ Block
Signal Direction Type a b q Input Input Output Any fixed-point type Any fixed-point type Boolean
Design Example
The demo_duc, demo_fft_4096_br, demo_fft_8192_br, demo_fft_4096_natural, and demo_ifft_8192_natural design examples include the CmpEQ block.
717
Parameters
The CmpGE block has no parameters.
Port Interface
Table 721 shows the port interface for the CmpGE block.
Table 721. Port Interface for the CmpGE Block
Signal Direction Type a b q Input Input Output Any fixed-point type Any fixed-point type Boolean
Design Example
The demo_agc design example includes the CmpGE block.
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Parameters
The CmpLT block has no parameters.
Port Interface
Table 722 shows the port interface for the CmpLT block.
Table 722. Port Interface for the CmpLT Block
Signal Direction Type a b q Input Input Output Any fixed-point type Any fixed-point type Boolean
719
Parameters
The CmpNE block has no parameters.
Port Interface
Table 723 shows the port interface for the CmpNE block.
Table 723. Port Interface for the CmpNE Block
Signal Direction Type a b q Input Input Output Any fixed-point type Any fixed-point type Boolean
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Constant (Const)
The Const block outputs a specified constant value.
Parameters
Table 724 shows the parameters for the Const block.
Table 724. Parameters for the Const Block
Description Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15. Specifies the constant value.
(1) If you use the Const block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 725 shows the port interface for the Const block.
Table 725. Port Interface for the Const Block
Design Example
The demo_duc, demo_fir_fractional, demo_agc, demo_filters_flow_control, demo_fft_4096_br, demo_fft_8192_br, demo_idct8x8, demo_fft_4096_natural, demo_ifft_8192_natural, demo_iir, demo_regs, and demo_wimax_duc design examples include the Const block.
721
Convert
The Convert block performs a type conversion of the input, and outputs the new data type. You can optionally perform truncation, biased, or unbiased rounding if the output data type is smaller than the input. The LSB must be a value in the width in bits of the input type.
Parameters
Table 726 shows the parameters for the Convert block.
Table 726. Parameters for the Convert Block
Description Determines how the block sets its output data type:
Inherit via internal rulethe number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialogyou can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Booleanthe output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15. Determines the rounding mode:
Truncate: Discard any bits that fall below the new least significant bit. Biased: Add 0.5 LSB and then truncate. This rounds towards infinity. Unbiased: If the discarded bits equal 0.5 LSB of the new value then round towards the even integer, otherwise perform add 0.5 LSB and then truncate. This prevents the rounding operation introducing a DC bias where 0.5 always rounds towards positive infinity.
Saturation
Note to Table 726:
The Convert block allows saturation, which has an optional clip detect output that outputs 1 if any clipping has occurred. Saturation choices are none, symmetric, or asymmetric.
(1) If you use the Convert block in a loop, you must specify the output type for at least one block in the loop.
For example, for an Add or Mult block, you can select the output word-length and fractional part using dialog. Specifying the output type is a casting operation, which does not preserve the numerical value, only the underlying bits. This method never adds hardware to a block just changes the interpretation of the output bits. For example, for a multiplier with both input data-types, sfix16_En15 has output type sfix32_En30. If you select output format sfix32_En28, the output numerical value multiplies by four. For example, 1*1 input gives an output value of 4. If the you select output format sfix32_En31, the output numerical value is divided by two. For example 1*1 input gives an output value of 0.5.
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If you want to change data-type format in a way that preserves the numerical value, use a convert block, which adds the corresponding hardware. Adding a convert block directly after a primitive block lets you specify the data-type to preserve the numerical value. For example, a Mult block followed by a Convert block, with input values 1*1 always give output value 1.
Port Interface
Table 727 shows the port interface for the Convert block.
Table 727. Port Interface for the Convert Block
Signal Direction Type a q Input Output Any fixed-point type Specified fixed-point type
Design Example
The demo_agc, demo_fft_4096_br, demo_fft_8192_br, demo_fft_4096_natural, demo_ifft_8192_natural, demo_fft16_radix2, demo_fft256_radix4, demo_iir, and demo_regs design examples include the Convert block.
723
CORDIC
The CORDIC block performs a coordinate rotation using the coordinate rotation digital computer algorithm. The CORDIC algorithm is a is a simple and efficient algorithm to calculate hyperbolic and trigonometric functions. It calculates the trigonometric functions of sine, cosine, magnitude and phase (arctangent) to any desired precision. A CORDIC algorithm is useful when you do not want to use a hardware multiplier, because the only operations it requires are addition, subtraction, bit shift and lookup. The CORDIC algorithm is generally faster than other approaches when you do not want to use a hardware multiplier, or you want to minimize the number of gates required. Alternatively, when a hardware multiplier is available, table-lookup and power series methods are generally faster than CORDIC. CORDIC is based on rotating the phase of a complex number, by multiplying it by a succession of constant values. The multiplications can all be powers of 2, which you can perform with just shifts and adds in binary arithmetic. Therefore you need no actual multiplier function. During each multiplication, a gain occurs equal to:
where i represents the ith iterative step. The total gain of the successive multiplications has a value of:
where n is the number of iterations. You can calculate this total gain in advance and stored in a table. Additionally:
The CORDIC block implements the these iterative steps using a set of shift-add algorithms to perform a coordinate rotation. The CORDIC block takes four inputs, where the x and y inputs represent the (x, y) coordinates of the input vector, the p input represents the angle input, and the v represents the mode of the CORDIC block. It supports the following modes:
The first mode rotates the input vector by a specified angle. The second mode rotates the input vector to the x-axis while recording the angle required to make that rotation.
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The x and y inputs must have the same width in bits. The input width in bits of the x and y inputs determines the number of stages (iterations) inside the CORDIC block, unless you explicitly specify an output width in bits smaller than the input width in bits in the block parameters. The CORDIC gain is completely ignored to save time and resource. The width in bits of the x and y inputs automatically grows by two bits inside the CORDIC block to account for the gaining factor of the CORDIC algorithm. Hence the x and y outputs are two bits wider than the input and you must handle the extra two bits in your design, if you have not specified the output width in bits explicitly through the block parameters. You can compensate for the CORDIC gain outside the CORDIC block. The p input is the angular value and has a range between and +, which requires at least three integer bits to fully represent the range. The v input determines the mode. You can trade accuracy for size (and efficiency) by specifying a smaller output data width to reduce the number of stages inside the CORDIC block.
Parameters
Table 728 shows the parameters for the CORDIC block.
Table 728. Parameters for the CORDIC Block
Description Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Output scaling value Specifies the output scaling value. For example, 2^-15.
(1) If you use the CORDIC block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 729 shows the port interface for the CORDIC block.
Table 729. Port Interface for the CORDIC Block
Signal Direction Type x y p Input Input Input Any fixed-point type Any fixed-point type Any fixed-point type
Description x coordinate of the input vector. y coordinate of the input vector. Required angle of rotation in the range between and
Input
Yes
Yes
725
Signal Direction Type x y p Output Output Output Any fixed-point type Any fixed-point type Any fixed-point type
Description x coordinate of the output vector. y coordinate of the output vector. Angle through which the. coordinates rotate
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Counter
The Counter block maintains a counter and outputs the counter value each cycle. The input is a counter enable and allows you to implement irregular counters. The counter initializes to the value that you provide, and counts with the modulo, with the step size you provide:
count = _initial_value; while (1) { if (en) count = (count + _step_size) % _modulo}
Parameters
Table 730 shows the parameters for the Counter block.
Table 730. Parameters for the Counter Block
Description Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15. A vector that specifies the counter in the format: [<initial_value> <modulo> <step size>] For example, [0 32 1]
Port Interface
Table 731 shows the port interface for the Counter block.
Table 731. Port Interface for the Counter Block
Design Example
The demo_fft16_radix2, demo_fft256_radix4, demo_fft_4096_br, demo_fft_8192_br, demo_fft_4096_natural, demo_ifft_8192_natural, and helloWorld design examples include the Counter block.
727
Delay
The Delay block outputs a delayed version of the input.
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Parameters
Table 732 shows the parameters for the CLZ block.
Table 732. Parameters for the CLZ Block
Description Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15.
(1) If you use the CLZ block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 733 shows the port interface for the CLZ block.
Table 733. Port Interface for the CLZ Block
Signal Direction Type a q Input Output Any fixed-point type Derived fixed-point type
Description Operand Number of consecutive zero bits in input word starting from the MSB
729
Reading from q1 while writing to interface 1 outputs the new data on q1 (write first behavior). Reading from q2 while writing to interface 1 outputs the old data on q2 (read first behavior).
Turning on DONT_CARE may give a higher fMAX for your design, especially if you implement the memory as a MLAB. When this option is on, the output is not double-registered (and therefore, in the case of MLAB implementation, uses fewer external registers), and you gain an extra half-cycle on the output. The word dont care overlaid on the block symbol indicates the current setting is DONT CARE. The default is off, which outputs old data for read-during-write. f For more information about this option, refer to the Read-During-Write Output Behavior section in the RAM Megafunction User Guide.
Parameters
Table 734 shows the parameters for the DualMem block.
Table 734. Parameters for the DualMem Block
Description Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Output data type Output scaling value Initial contents Use DONT_CARE when reading from and writing to the same address
Note to Table 734:
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15. Specifies the initialization data. The size of the 1-D array determines the memory size. Turn this option on to produce faster hardware ( a higher fMAX) but with uncertain read data in hardware if you are simultaneously reading from and writing to the same address. Ensure that you do not read from or write to the same address at the same time to guarantee valid read data.
(1) If you use the DualMem block in a loop, you must specify the output type for at least one block in the loop.
You can specify the contents of the DualMem block in one of the following ways:
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Use a a single row or column vector to specify table contents. The length of the 1D row or column vector determines the number of addressable entries in the table. If DSP Builder reads vector data from the table, all components of a given vector share the same value. When a look-up table contains vector data, you can provide a matrix to specify the table contents. The number of rows in the matrix determines the number of addressable entries in the table. Each row specifies the vector contents of the corresponding table entry. The number of columns must match the vector length, otherwise DSP Builder issues an error.
Port Interface
Table 735 shows the port interface for the DualMem block.
Table 735. Port Interface for the DualMem Block
Signal Direction Type d a w Input Input Input Any fixed-point type Unsigned integer Boolean
Description Data to write for interface 1 Address to read/write from for interface 1 Write is enabled for interface 1 when 1, read is enabled for interface 1 when 0 Address to read from for interface 2 Data out from interface 1. (Note 1) Data out from interface 2. (Note 1)
a q1 q2
Note:
No Yes Yes
(1) If the address for interface 1 exceeds the memory size, q1 is not defined. If the address for interface 2 exceeds the memory size, q2 is not defined. To write to the same location as DSP Builder reads from with q2, you must provide the same address on both interfaces.
Design Example
The demo_fft16_radix2, demo_fft256_radix4, demo_fft_4096_br, demo_fft_8192_br, demo_fft_4096_natural, demo_ifft_8192_natural, and demo_duc design examples include the DualMem block.
731
Demultiplexer (Demux)
The Demux block deserializes the DSP Builder protocol bus on its inputs to produce a configurable number of output signals without TDM. The Demux block is a primtive version of the ChannelViewer block
Parameters
Table 736 shows the parameters for the Demux block.
Table 736. Parameters for the Demux Block Parameter Number of output channels Number of input channels Description A vector of the channel number you want to see for example [0 1 3]. The number of input channels. The block takes valid, channel, and (vector) data inputs. The channel is the normal channel count, which varies across 0 to NumberOfChannelsPerWire.
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FIFO
The FIFO block models a FIFO memory. DSP Builder writes data through the d input when the write-enable input w is high. After some implementation-specific number of cycles, DSP Builder presents data at output q and the valid output v goes high. DSP Builder holds this data at output q until the read acknowledge input r is set high. The FIFO block wraps the Altera single clock FIFO (SCFIFO) megafunction operating in show-ahead mode. That is, the read input, r, is a read acknowledgement which means the DSP Builder has read the output data, q, from the FIFO buffer, so you can delete it and show the next data output on q. The data you present on q is only valid if the output valid signal, v, is high
Parameters
Table 737 shows the parameters for the FIFO block.
Table 737. Parameters for the FIFO Block Parameter FIFO Setup Description A vector of three non-zero integers in the format: [<depth> <fill_threshold> <full_period>]
depth specifies the maximum number of data values that the FIFO can store. fill_threshold specifies a low-threshold for empty-detection. If the number of data items in the memory is greater than the low-threshold, the t output is 1 (otherwise it is 0). full_period specifies a high-threshold for full-detection If the number of data items is greater than the high-threshold, output f is 1 (otherwise it is 0).
Port Interface
Table 738 shows the port interface for the FIFO block.
Table 738. Port Interface for the FIFO Block Signal w d r v q t f Direction Input Input Input Output Output Output Output Boolean Fixed-point Boolean Boolean Fixed-point Boolean Boolean Type Description Write enable. Data. Read acknowledge. Valid. Data. Fill threshold. Fullness. Vector Data Support Yes Yes Yes Yes Yes Yes Yes Complex Data Support No Yes No No Yes No No
733
Because of differences in latency across different pairs of portsfrom w to v is 3 cycles, from r to t is 1 cycle, from w to t is 1 cycleyou can to set fill_threshold to a low number (<3) and arrive at a state such that output t is high and output v is low. If this situation arises, do not send a read acknowledgement to the FIFO buffer. Ensure that when the v output is low, the r input is also low, otherwise a warning appears in the MATLAB command window. If the read acknowledgement is derived from a feedback from the t output, ensure that the fill_threshold is set to a sufficiently high number (3 or above). Likewise for the f output and the full_period. You may supply vector data to the d input, and vector data on the q output is the result. DSP Builder does not support vector signals on the w or r inputs, and the behavior is unspecified. The v, t, and f outputs are always scalar.
Design Example
The demo_back_pressure design example includes the FIFO block.
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ForLoop
The ForLoop block extends the basic loop, providing a more flexible structure that implements all common loop structuresfor example, triangular loops, parallel loops, and sequential loops. Each ForLoop block manages a single counter with a token-passing scheme that allows you to link these counters in a variety ways. Each ForLoop block has a static loop test parameter, which may be <=, <, > or >=. Loops that count up should use <= or <, depending on whether you consider the limit value, supplied by the limit signal, is within the range of the loop. Loops that count down should use >= or >.
Port Interface
Table 748 shows the port interface for the ForLoop block. The latency of the ForLoop block is non-zero. At loop end detection there are some cycles that may be invalid overhead required to build nested loop structures. The second activation of an inner loop does not necessarily begin immediately after the end of the first activation.
Table 739. Port Interface for the ForLoop Block Signal bs bd ld ls Direction Output Input Output Input Type Description Token-passing inputs and outputs. The four signals ls (loop start), bs (body start), bd (body done) and ld (loop done) pass a control token between different ForLoop blocks, to create a variety of different control structures. When the ls port receives a token, the ForLoop block initializes. The loop counter is set to its initial value (that the i signal specifies). When the bd port receives a token, the step value (s) increments the loop counter. In either case, the new value of the counter is compared with the limit value (l) with the statically-configured loop test. If the loop test passes, the ForLoop block outputs the control token on the bs port to initiate the loop body and the valid signal, v, becomes active. If the loop test fails, the ForLoop block outputs the control token on ld port to indicate that the loop is complete and v becomes inactive. The ForLoop block becomes active when it receives a token on its ls port, and remains active until it finally outputs a token on its ld port. Changing any of the loop parameterization inputs (i, s, or l) while the loop is active, is not supported and produces unpredictable results. c Output The signal c is the count output from the loop. Its value is reliable only when the valid signal, v, is active Vector Data Support Complex Data Support
735
Table 739. Port Interface for the ForLoop Block Signal e Direction Input Type Description Use the enable input, e, to suspend and resume operation of the ForLoop block. When you disable the loop, the valid signal, v, goes low but DSP Builder makes no changes to the internal state of the block. When you re-enable the block, it resumes counting from the state at which you suspended it. Loop parameterization inputs. The signals i, s, and l set the initial value, step and limit value (respectively) of the loop. Use with the loop test parameter, to control the operation of the loop. The loop parameter signals must be held constant while the loop is active, but you may them when the loop is inactive. Different activations of a ForLoop block can have different start or end points, which is useful for creating nested triangular loops, for example. Auxiliary loop outputs: the signals fl and ll are active on the first loop iteration and last loop iteration, respectively. The signal el is active when the ForLoop block is processing an empty loop. Vector Data Support Complex Data Support
i s l
el fl ll
Design Examples
The following design examples demonstrate the ForLoop block:
Rectangular Nested Loop on page 27 Triangular Nested Loop on page 27 Sequential Loops on page 27 Parallel Loops on page 27
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Parameters
Table 740 shows the parameters for the GPIn block.
Table 740. Parameters for the GPIn Block
Port Interface
Table 741 shows the port interface for the GPIn block.
Table 741. Port Interface for the GPIn Block
Signal
Description Operands 1 to n
Design Example
The demo_QAM256 design example includes the GPIn block.
737
Parameters
Table 742 shows the parameters for the GPOut block.
Table 742. Parameters for the GPOut Block
Port Interface
Table 743 shows the port interface for the GPOut block.
Table 743. Port Interface for the GPOut Block
Signal
Description Operands 1 to n
Design Example
The demo_QAM256 design example includes the GPOut block.
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The width of the data type a determines the maximum size of the shift. Shifts of more than the input word width result in an output of 0.
Parameters
Table 744 shows the parameters for the LShift block.
Table 744. Parameters for the LShift Block
Description Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15.
(1) If you use the LShift block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 745 shows the port interface for the LShift block.
Table 745. Port Interface for the LShift Block
Signal Direction Type a b q Input Input Output Any fixed-point type Any fixed-point type Derived fixed-point type
739
The size of the table determines the size of the initialization arrays.
Parameters
Table 746 shows the parameters for the Lut block.
Table 746. Parameters for the Lut Block
Description Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15. Specifies the location of the output values. For example, round([0;254]/17).
(1) If you use the Lut block in a loop, you must specify the output type for at least one block in the loop.
You can specify the contents of the Lut block in one of the following ways:
Specify table contents with a single row or column vector. The length of the 1D row or column vector determines the number of addressable entries in the table. If DSP Builder reads vector data from the table, all components of a given vector share the same value. When a look-up table contains vector data, you can provide a matrix to specify the table contents. The number of rows in the matrix determines the number of addressable entries in the table. Each row specifies the vector contents of the corresponding table entry. The number of columns must match the vector length, otherwise DSP Builder issues an error.
The default initialization of the LUT is a row vector round([0:255]/17). This vector is inconsistent with the default for the DualMem block, which is a column vector [zeros(16, 1)]. The latter form is consistent with the new matrix initialization form in which the number of rows determines the addressable size.
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Port Interface
Table 747 shows the port interface for the Lut block.
Table 747. Port Interface for the Lut Block
Description Operand
Design Example
The demo_agc, demo_fft16_radix2, demo_fft256_radix4, demo_QAM256, and helloWorld design examples include the Lut block.
741
Loop
The Loop block maintains a set of counters that implement the equivalent of a nested for loop in software. The counted values range from 0 to limit values provided with an input signal. When the go signal is asserted on the g input, limit-values are read into the block with the c input. The dimension of the vector determines the number of counters (nested loops). When DSP Builder enables the block with the e input, it presents the counter values as a vector value at the q output each cycle. The valid output is set to 1 to indicate that a valid output is present. There are vectors of flags indicating when first values (output f) and last values (output l) occur. A particular element in these vector outputs is set to 1 when the corresponding loop counter is set at 0 or at count-1 respectively. Use the Loop block to drive datapaths that operate on regular data either from an input port or data stored in a memory. The enable input, and corresponding valid output, facilitate forward flow control. For a two dimensional loop the equivalent C++ code to describe the general loop is:
for (int i = 0; i < c[0]; i++) for (int j = 0; j < c[1]; j++) { q[0] = i; q[1] = j; f[0] = (i==0); f[1] = (j==0); l[0] = (i==(c[0]-1)); l[1] = (j==(c[1]-1)); }
Port Interface
Table 748 shows the port interface for the Loop block.
Table 748. Port Interface for the Loop Block Signal g c e v q f l Direction Input Input Input Output Output Output Output Type Boolean Unsigned Boolean Boolean Boolean Boolean Go. Counter limit values. Enable. Valid. First value flags. Last value flags. Description Vector Data Support Yes Yes Yes Yes Yes Yes Yes Complex Data Support No No No No No No No
Design Examples
The demo_kronecker design example includes the Loop block.
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Parameters
Table 749 shows the parameters for the Max block.
Table 749. Parameters for the Max Block
Description Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15.
(1) If you use the Max block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 750 shows the port interface for the Max block.
Table 750. Port Interface for the Max Block
Signal Direction Type a b q Input Input Output Any fixed-point type Any fixed-point type
743
Parameters
Table 751 shows the parameters for the Min block.
Table 751. Parameters for the Min Block
Description Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15.
(1) If you use the Min block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 752 shows the port interface for the Min block.
Table 752. Port Interface for the Min Block
Signal Direction Type a b q Input Input Output Any fixed-point type Any fixed-point type
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Multiply (Mult)
The Mult block outputs the product of the inputs:
q = a b
Parameters
Table 753 shows the parameters for the Mult block.
Table 753. Parameters for the Mult Block
Description Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15.
(1) If you use the Mult block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 754 shows the port interface for the Mult block.
Table 754. Port Interface for the Mult Block
Signal Direction Type a b q Input Input Output Any fixed-point type Any fixed-point type
Design Example
The demo_regs, demo_agc, demo_idct8x8, demo_iir, demo_AD9856, and demo_duc design examples include the Mult block.
745
Multiplexer (Mux)
The Mux block allows a variable number of inputs and outputs the selected input, or zero if the select value is invalid (outside the number of data signals).
You can make a multiple input multiplexer by combining more than one mux2 blocks in a tree or by using a Select block.
Parameters
Table 755 shows the parameters for the Mux block.
Table 755. Parameters for the Mux Block
Description The input type for s is an unsigned integer of width log2(number of data signals). Boolean is also allowed in the case of two data inputs. Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. 1 Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15.
(1) If you use the Mux block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 756 shows the port interface for the Mux block.
Table 756. Port Interface for the Mux Block
Signal Direction Type s 0 1 q Input Input Input Output Any fixed-point type Any fixed-point type Any fixed-point type
Design Example
The demo_fft_4096_br, demo_fft_8192_br, demo_idct8x8, demo_fft_4096_natural, demo_ifft_8192_natural, demo_AD9856, and demo_duc design examples include the Mux block.
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If the number of inputs is set to 1, then output the logical NAND of all the individual bits of the input word.
Parameters
Table 757 shows the parameters for the Nand block.
Table 757. Parameters for the Nand Block
Description Specifies the number of inputs. Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15.
(1) If you use the Nand block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 757 shows the port interface for the Nand block.
Table 758. Port Interface for the Nand Block
Signal Direction Type a b q Input Input Output Any fixed-point type Any fixed-point type
747
Set the number of inputs to 1, to output the logical NOR of all the individual bits of the input word.
Parameters
Table 759 shows the parameters for the Nor block.
Table 759. Parameters for the Nor Block
Description Specifies the number of inputs. Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15.
(1) If you use the Nor block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 760 shows the port interface for the Nor block.
Table 760. Port Interface for the Nor Block
Signal Direction Type a b q Input Input Output Any fixed-point type Any fixed-point type
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Parameters
Table 761 shows the parameters for the Not block.
Table 761. Parameters for the Not Block
Description Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15.
(1) If you use the Not block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 762 shows the port interface for the Not block.
Table 762. Port Interface for the Not Block
Description Operand
Design Example
The demo_fft_4096_br, demo_fft_8192_br, demo_idct8x8, demo_fft_4096_natural, demo_ifft_8192_natural, and demo_duc design examples include the Not block.
749
OR Gate (Or)
The Or block outputs the logical OR of the input values:
q = a | b
Set the number of inputs to 1, to output the logical OR of all the individual bits of the input word.
Parameters
Table 763 shows the parameters for the Or block.
Table 763. Parameters for the Or Block
Description Specifies the number of inputs. Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15.
(1) If you use the Or block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 764 shows the port interface for the Or block.
Table 764. Port Interface for the Or Block
Signal Direction Type a b q Input Input Output Any fixed-point type Any fixed-point type
Design Example
The demo_fft_4096_br, demo_fft_8192_br, demo_idct8x8, demo_fft_4096_natural, demo_ifft_8192_natural, and demo_duc design examples include the Or block.
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Parameters
Table 765 shows the parameters for the SampleDelay block.
Table 765. Parameters for the SampleDelay Block
Description Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15. Specifies the number of samples to delay.
(1) If you use the SampleDelay block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 766 shows the port interface for the SampleDelay block.
Table 766. Port Interface for the SampleDelay Block
Signal Direction Type a q Input Output Any fixed-point type Derived fixed-point type
Design Example
The demo_agc, demo_fft16_radix2, demo_fft256_radix4, demo_fft_4096_br, demo_fft_8192_br, demo_fibonacci, demo_idct8x8, demo_ifft_4096_natural, demo_ifft_8192_natural, and demo_iir design examples include the SampleDelay block.
751
Select
The Select block outputs one of the data signals (a, b, ...) if its paired select input (0, 1, ...) has a non-zero value.
q = 0 ? a : (1 ? b : d)
If all select inputs are 0, the Select block outputs the default value d. At most one select input should be high at a time.
Parameters
Table 767 shows the parameters for the Select block.
Table 767. Parameters for the Select Block
Description Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15. Specifies the number of non-default data inputs.
(1) If you use the Select block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 768 shows the port interface for the Select block.
Table 768. Port Interface for the Select Block
Signal d
Direction Type Input Any fixed-point type Boolean Any fixed-point type Derived fixed-point type
Design Example
The demo_regs, and demo_agc design examples include the Select block.
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Sequence
The Sequence block outputs a Boolean pulse of configurable duration and phase. The input acts as an enable for this sequence. Usually, this block initializes with an array of booleans of length period. The first step_value entries are zero, and the remaining values are one. A counter steps along this array, one entry at a time, and indexes the array. The output value is the contents of the array. The counter is initialized to initial_value. The counter wraps at step period, back to zero, to index the beginning of the array.
Parameters
Table 769 shows the parameters for the Sequence block.
Table 769. Parameters for the Sequence Block
Description Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15. A vector that specifies the counter in the format: [<initial_value> <step_value> <period>] For example, [0 50 100]
(1) If you use the Sequence block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 770 shows the port interface for the Sequence block.
Table 770. Port Interface for the Sequence Block
Design Example
The demo_fft_4096_br, demo_fft_8192_br, demo_idct8x8, demo_fft_4096_natural, and demo_ifft_8192_natural design examples include the Sequence block.
753
Shift
The Shift block outputs the logical right shifted version of the input value if unsigned, or outputs the arithmetic right shifted version of the input value if signed. The shift is specified by the input b:
q = (a >> b)
The width of the data type b determines the maximum size of the shift. Shifts of more than the input word width result in an output of 0 for non-negative numbers and (0 2-F) for negative numbers (where F is the fraction length).
Parameters
Table 771 shows the parameters for the Shift block.
Table 771. Parameters for the Shift Block
Description Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15.
(1) If you use the Shift block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 772 shows the port interface for the Shift block.
Table 772. Port Interface for the Shift Block
Signal Direction Type a b q Input Input Output Any fixed-point type Unsigned integer Derived fixed-point type
Design Example
The demo_regs, and demo_agc design examples include the Shift block.
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Subtract (Sub)
The Sub block outputs the difference between the inputs:
q = a b.
Parameters
Table 773 shows the parameters for the Sub block.
Table 773. Parameters for the Sub Block
Description Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Inherit via internal rule with word growth: the number of fractional bits is the maximum of the number of fractional bits in the input data types. The number of integer bits is the maximum of the number of integer bits in the input data types plus one. This additional word growth allows for subtracting the most negative number from 0, which exceeds the maximum positive number that you can store in the number of bits of the input. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15.
(1) If you use the Sub block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 774 shows the port interface for the Sub block.
Table 774. Port Interface for the Sub Block
Signal Direction Type a b q Input Input Output Any fixed-point type Any fixed-point type Derived fixed-point type
Design Example
The demo_regs, demo_agc, demo_idct8x8, demo_iir, and demo_AD9856 design examples include the Sub block.
755
Parameters
Table 775 shows the parameters for the SynthesisInfo block.
Table 775. Parameters for the SynthesisInfo Block
Scheduled: This option uses a pipelining and delay distribution algorithm that creates fast hardware implementations from an easily described untimed block diagram. WYYSIWYG: (Default) This option is useful when you want full control over the pipelining in a system. Every primitive that requires registering (for example, adders and multipliers) must be followed immediately by a Delay primitive. If the design provides insufficient delay, an error occurs.
This option is available when the Scheduled synthesis style is selected and allows you to select the type of constraint and to specify its value. The specified value can be a workspace variable or an expression but must evaluate to a positive integer. You can select the following types of constraint:
>: Greater than >=: Greater than or equal to =: Equal to <=: Less than or equal to <: Less than
Port Interface
The SynthesisInfo block has no inputs or outputs.
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Updated Help
After you run a simulation, DSP Builder updates the help pages with specific information about each instance of a block. Table 776 shows some typical help messages that DSP Builder issues for the Synthesis Info block.
Table 776. Messages for the SynthesisInfo Block
Description The latency introduced by the current subsystem. Lists the port interfaces to the current subsystem. Lists the resource utilization for the current subsystem.
Written on Tue Feb 19 11:25:27 2008 Date and time when this file ran.
Design Example
The demo_regs, demo_agc, demo_fft16_radix2, demo_fft256_radix4, demo_fibonacci, demo_idct8x8, demo_iir, demo_QAM256, demo_AD9856 and demo_duc design examples include the SynthesisInfo block.
757
Set the number of inputs to 1, to output the logical XNOR of all the individual bits of the input word.
Parameters
Table 777 shows the parameters for the Xnor block.
Table 777. Parameters for the Xnor Block
Description Specifies the number of inputs. Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15.
(1) If you use the Xnor block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 778 shows the port interface for the Xnor block.
Table 778. Port Interface for the Xnor Block
Signal Direction Type a b q Input Input Output Any fixed-point type Any fixed-point type
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Set the number of inputs to 1, to output the logical XOR of all the individual bits of the input word.
Parameters
Table 779 shows the parameters for the Xor block.
Table 779. Parameters for the Xor Block
Description Specifies the number of inputs. Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. (Note 1) Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15.
(1) If you use the Xor block in a loop, you must specify the output type for at least one block in the loop.
Port Interface
Table 780 shows the port interface for the Xor block.
Table 780. Port Interface for the Xor Block
Signal Direction Type a b q Input Input Output Any fixed-point type Any fixed-point type
8. ModelVectorPrim Library
The ModelPrim library contains the SumOfElements block that specifically operates on vector signals, rather than replicates functionality based on vector widths as do other primitive blocks. Primitive subsystems use this block with ModelPrim library blocks.
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Parameters
Table 81 shows the parameters for the SumOfElements block.
Table 81. Parameters for the SumOfElements Block
Description Determines how the block sets its output data type:
Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types. Word growth occurs if the input data types are not identical. Inherit via internal rule with word growth: the number of fractional bits is the maximum of the number of fractional bits in the input data types. The number of integer bits is the maximum of the number of integer bits in the input data types plus one. This additional word growth allows for subtracting the most negative number from 0, which exceeds the maximum positive number that you can store in the number of bits of the input. Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. Boolean: the output type is Boolean.
Specifies the output data type. For example, sfix(16), uint(8). Specifies the output scaling value. For example, 2^-15. Specifies the number of inputs.
Port Interface
Table 82 shows the port interface for the SumOfElements block.
Table 82. Port Interface for the SumOfElements Block
Signal Direction Type a q Input Output Any fixed-point type Derived fixed-point type
This chapter lists the blocks in each of the libraries in the Altera DSP Builder advanced blockset.
Base
The Base library contains the following blocks:
Avalon-ST Output (AStOutput) Avalon-ST Input (AStInput) Avalon-ST Input FIFO Buffer (AStInputFIFO) Zero-Latency Latch (latch_0L) Single-Cycle Latency Latch (latch_1L) Single-Cycle Latency Latch (latch_1L) Reset-Priority Latch (SRlatch_PS) Set-Priority Latch (SRlatch) Expand Scalar (ExpandScalar) Vector Multiplexer (VectorMux) Tapped Delay Line (TappedDelayLine) Channel Viewer (ChanView) Control Device Edit Params LocalThreshold Run ModelSim Run Quartus II Scale Signals
FFT
The FFT library contains the following blocks in the Common folder:
Complex Multiplier (ComplexMult) Complex Sample Delay (ComplexSampleDelay) Dual Twiddle Memory Negate Negate Parameterizable
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Butterfly I (BFI) Butterfly II (BFII) Bit Reverse Core (BitReverseCore) Twiddle Generator
Filter
The Filter library contains the following blocks:
Decimating CIC Decimating FIR Fractional Rate FIR Interpolating CIC Interpolating FIR Single-Rate FIR
ModelBus
The ModelBus library includes the following blocks:
Bus Slave (BusSlave) Bus Stimulus (BusStimulus) Bus Stimulus File Reader (Bus StimulusFileReader) Register Bit (RegBit) Register Field (RegField) Register Out (RegOut) Shared Memory (SharedMem)
ModelPrim
The ModelPrim library contains the following primitive blocks:
Absolute Value (Abs) Add Add SLoad (AddSLoad) AND Gate (And) Bit Combine (BitCombine) Bit Extract (BitExtract) Bit Reverse (BitReverse) Channel In (ChannelIn) Channel Out (ChannelOut)
93
Complex Conjugate (ComplexConjugate) Compare Equality (CmpEQ) Compare Greater Than (CmpGE) Compare Less Than (CmpLT) Compare Not Equal (CmpNE) Constant (Const) Convert CORDIC Counter Delay Count Leading Zeros (CLZ) Dual Memory (DualMem) FIFO ForLoop General Purpose Input (GPIn) General Purpose Output (GPOut) Left Shift (LShift) Look-Up Table (Lut) Loop Maximum Value (Max) Minimum Value (Min) Multiply (Mult) Multiplexer (Mux) NAND Gate (Nand) NOR Gate (Nor) NOT Gate (Not) OR Gate (Or) Sample Delay (SampleDelay) Select Sequence Shift Subtract (Sub) Synthesis Information (SynthesisInfo) XNOR Gate (Xnor) XOR Gate (Xor)
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ModelVectorPrim
Waveform Synthesis
The Waveform Synthesis library includes the following blocks:
Index
Symbols
.hex file 121 .qip file 121 .xml file 121
A
Abs block 75 Add block 76 Add SLoad block 78 And block 79 AStInput block 23 AStInputFIFO block 23 AStOutput block 21 Automatic testbench Enabling 12 Loading 123 Running from a command 123 Avalon-MM interface Bus clock 120
Complex Mixer block 52 Complex Sample Delay block 43 ComplexMult block 42 Const block 720 Control block 27 Convert block 721 CORDIC block 723 Counter block 726
D
Decimating CIC block 34 Decimating FIR block 37 Delay block 727 Demux block 731 Design Example Opening 21 Design example Running 25 Device block 28 Device family support Advanced blockset 15 Dual Twiddle Memory block 45 DualMem block 729
B
Base Blocks Example designs 24 Library 12 BFI block 48 BFII block 49 Bit Combine block 710 Bit Extract block 711 Bit Reverse Core block 411 Bit Reverse primitive block 712 Bus clock 14 Avalon-MM interface 120 Bus Slave block 61 Bus Stimulus block 62 Bus Stimulus File Reader block 63
E
Edit Params Block 29 Example designs 16-Channel DDC 28 16-Channel DUC 28 2-Antenna DUC for WiMAX 29 2-Channel DUC 29 4,096 point FFT 221 4,096 point IFFT 222 8,192 point FFT 222 8,192 point IFFT 223 Automatic Gain Control 219 Complex Mixer 214 Decimating CIC Filter 210 Decimating FIR Filter 211 Digital Predistortion Forward Path 226 Fibonacci Series 218 Filter Chain with Forward Flow Control 213 Folded 3-stage IIR Filter 225 Folded Color Space Converter 224 Folded Primitive FIR Filter 225 Folded Single-stage IIR Filter 225 Fractional FIR Filter Chain 212 Fractional Rate FIR Filter 211
C
CDelay RAM Block threshold 13 CDualMem Dist RAM threshold 13 Channel In block 713 Channel Out block 714 ChanView block 25 Clock rate 120 CLZ block 728 CmpEQ block 716 CmpGE block 717 CmpLT block 718 CmpNE block 719
Index2
Half Band FIR Filter 211 Hello World 218 Hybrid Direct Form and Transpose Form FIR Filter 226 Interpolating CIC Filter 210 Interpolating FIR Filter 211 Inverse Discrete Cosine Transform 220 Kronecker Tensor Product 26 Local threshold 229 Matrix Initialization of LUT 227 Matrix Initialization of Vector Memories 227 Memory-Mapped Registers 228 Multi-Channel IIR Filter 219 Multiple Coefficient Banks Interpolating FIR Filter 213 NCO 213 NCO, 4 channel, 16 banks 216 NCO, 4 channel, 2 banks 214 NCO, 4 channel, 4 banks 215 NCO, 4 channel, 64 banks 217 NCO, 4 channel, 8 banks, 2 wires 216 Parallel Loops 27 Primitive FIR with Back Pressure 25 Primitive FIR with Forward Pressure 26 Quadrature Amplitude Modulation 220 Radix 2 Streaming FFT 220 Radix 4 Streaming FFT 221 Real Mixer 213 Rectangular Nested Loop 27 Root Raised Cosine FIR Filter 212 Run-time Configurable Decimating and interpolating Half-rate FIR Filter 226 Scale 228 Sequential Loops 27 Single Rate FIR Filter 210 Super-Sample FIR Filter 212 Test CORDIC Using Primitive Blocks 223 Test CORDIC Using the CORDIC Block 224 Triangular Nested Loop 27 Vector Initialization of Sample Delay 228 ExpandScalar block 25
G
Generated files Advanced Blockset model 121 DDC design example 515 Fibonacci design example 47 NCO design example 310 GPIn block 736 GPOut block 737
H
Hard multiplier threshold 13 Hardware generation Enabling 12 Host Interface Example designs 24 How to Contact Altera Info1
I
Interpolating CIC block 315 Interpolating FIR block 318
L
latch_0 block 23 latch_1 block 24 Latency parameter Displaying for a ModelIP block 19 Displaying for a primitive subsystem 15 Reading 19 Library Base Blocks 12 FFT Blockset 15 ModelBus 18 ModelIP 18 Filters 18 Waveform Synthesis 18 ModelPrim 15 LocalThreshold block 213 Loop block 741 LShift block 738 Lut block 739
F
FFT Blockset Library 15 FIFO block 732 Filters Example designs 22 Library 18 Fixed point types 119 ForLoop block 734 Fractional Rate FIR block 311
M
Max block 742 Memory and multiplier thresholds 12 Memory mapped interface 117 Memory-Mapped bus interface Address and bus width 12 Min block 743 ModelBus Example designs 24 Library 18, 18 ModelIP Library 18
Index3
Protocol 110 ModelPrim Example designs 23 Library 15 M-RAM threshold 13 Mult block 744 Multichannel systems 113 Mux2 block 745
Register Out block 67 Run ModelSim block 214 Run Quartus II block 214
S
Sample Delay block 750 Sample rate 119 Scale block 215 Select block 751 Sequence block 752 Shared Memory block 68 Shift block 753 Signals block 217 Single Rate FIR block 323 SRlatch block 24 SRlatch_PS block 24 Standard blockset interoperability 11 Sub block 754 SynthesisInfo block 755 System clock 14
N
Nand block 746 NCO block 56 Negate block 46 Negate Parameterizable block 47 Nor block 747 Not block 748
O
Or block 749
P
Platforms Example designs 22 Primitive blocks Example designs 23 Output data type 16 Synthesis styles 17
T
TappedDelayLine block 25 Time-division multiplexing 112 Tutorials ModelIP 31 Primitive Library 41 System 51 Twiddle Generator block 412 Typographic Conventions Info1
R
Real Mixer block 54 Reference designs 24 1-Antenna WiMAX DDC 234 1-Antenna WiMAX DUC 235 1-Carrier, 2-Antenna W-CDMA DDC 230 1-Carrier, 2-Antenna W-CDMA DUC 231 2-Antenna WiMAX DDC 234 2-Antenna WiMAX DUC 235 4-Carrier, 2-Antenna W-CDMA DDC 229 4-Carrier, 2-Antenna W-CDMA DUC 230 4-Carrier, 2-Antenna W-CDMA DUC at 307.2 MHz with Total Rate Change 40 233 4-Carrier, 2-Antenna WDCMA DUC at 368.64 MHz with Total Rate Change 32 231 4-Carrier, 2-Antenna WDCMA DUC at 368.64 MHz with Total Rate Change 48 232 Single-Channel 10-MHz LTE Transmitter 236 Register Bit block 65 Register Field block 66
V
Vectorized inputs 113 VectorMux block 25
W
Walkthrough ModelIP tutorial 31 Primitive Library tutorial 41 System tutorial 51 Waveform Synthesis Example designs 23 Library 18
X
Xnor block 757 Xor block 758
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Index4
Additional Information
Typographic Conventions
The following table shows the typographic conventions that this document uses.
Visual Cue Bold Type with Initial Capital Letters bold type Meaning Indicates command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box. For GUI elements, capitalization matches the GUI. Indicates directory names, project names, disk drive names, file names, file name extensions, dialog box options, software utility names, and other GUI labels. For example, \qdesigns directory, d: drive, and chiptrip.gdf file. Indicates document titles. For example, AN 519: Stratix IV Design Guidelines. Indicates variables. For example, n + 1. Variable names are enclosed in angle brackets (< >). For example, <file name> and <project name>.pof file. Initial Capital Letters Subheading Title
Courier type
Indicates keyboard keys and menu names. For example, Delete key and the Options menu. Quotation marks indicate references to sections within a document and titles of Quartus II Help topics. For example, Typographic Conventions. Indicates signal, port, register, bit, block, and primitive names. For example, data1, tdi, and input. Active-low signals are denoted by suffix n. For example, resetn. Indicates command line commands and anything that must be typed exactly as it appears. For example, c:\qdesigns\tutorial\chiptrip.gdf. Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword SUBDESIGN), and logic function names (for example, TRI).
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Info2
Visual Cue 1., 2., 3., and a., b., c., and so on.
Meaning Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets indicate a list of items when the sequence of the items is not important. The hand points to information that requires special attention. A caution calls attention to a condition or possible situation that can damage or destroy the product or your work. A warning calls attention to a condition or possible situation that can cause you injury. The angled arrow instructs you to press Enter. The feet direct you to more information about a particular topic.
1 c w r f