II B.Tech II Semester (R07) Supply Examinations, Dec- 2009,CSE SET-1 1.

(a) Distinguish between tightly coupled microprocessors and loosely coupled Microprocessors. (b) Describe Von Neumann and Harward architectures. [8+8M] 2. Explain common addressing modes with suitable flow diagrams. Also explain the merits and demerits of each, in detail. [16M] 3. (a) Differentiate between micro programmed and hard wired control units with merits and demerits of each. (b) Discuss about the design considerations of micro instruction sequencing technique. [8+8M] 4. (a) What is the use of fast multiplication circuits. Write about array multipliers. (b) Explain booths algorithm with its theoretical basis [8+8M] 5. Explain the following with applications for each: (a) ROM (b) PROM (c) EPROM (d) EEPROM [4+4+4+4M]

6. What are the different modes of data transfer? Explain each mode in detail [16M] 7. Explain the following in related with Vector Processing (a) Super Computers (b) Vector operations (c) Matrix multiplication (d) Memory interleaving [4+4+4+4M] 8. (a) Discuss in detail about serial arbitration procedure (Daisy Chain). (b) What are the different physical forms available to establish an interconnection network ? Give the summary of those. [8+8M] SET-2
1. (a) Explain about error detecting and correcting codes. What is their

relevance? (b) Explain about sign magnitude and 2s complement approaches for representing the

fixed point numbers. Why 2s complement is preferable. [8+8M] 2. Design a circuit to increment, decrement and complement and clear a 4 bit register using RS flip-flops. Explain the control logic. [16M] 3. (a) How the address of next microinstruction is known while executing a microprogram. (b) Discuss about branch control logic in microinstruction sequencing with variable address format. [8+8M] 4. (a) Multiply 10111 with 10011 using booths algorithm. (b) Represent two n-bit unsigned numbers multiplications with a series of n/2bit multiplications. [8+8M] 5. (a) What is a virtual memory technique? Explain different virtual memory techniques. (b) What is the need of Replacement Algorithms for a Cache Memory? Explain any two Cache Replacement Strategies. [8+8M] 6. Explain the following: (a) Asynchronous Serial Transfer (b) Asynchronous Communication Interface [8+8M] 7. (a) What is pipeline? Explain space-time diagram for Pipeline. (b) Explain pipeline for floating point addition and subtraction. [8+8M] 8 (a) What is cache coherence? Explain different solutions to the cache coherence problem. (b) Explain multiport memory organization with a neat sketch. [8+8M] SET-3
1(a) What is meant by normalization in floating point representation? Why do

need it? What normalization is used in IEEE 754 standard? (b) Explain about NaN and de-normalized numbers in IEEE 754 standards. [10+6M] 2. (a) Design a circuit transferring data from a 4bit register which uses D flipflops to another register which employs RS flip-flops. (b) What are register transfer logic languages? Explain few RTL statement for branching with their actual functioning. [8+8M] 3. (a) How do you map micro-operation to a micro instruction address.

(b) Hardwired control unit is faster than microprogammed control unit. Justify this statement. [8+8M] 4. (a) Explain booths algorithm with its theoretical basis. (b) Draw a flow chart which explains multiplication of two signed magnitude fixed point numbers and give an example for the working of the method. [8+8M] 5. (a) Compare and contrast Asynchronous DRAM and Synchronous DRAM. (b) Elaborate on address translation in virtual memories. [8+8M] 6. (a) What is Direct Memory Access? Explain the working of DMA. (b) What is parallel priority interrupt method? Explain with neat sketch. [8+8M] 7. Write short notes on the following: (a) RISC pipeline (b) Vector processing (c) Array processors. [6+5+5M] 8. (a) What is the functioning of cross bar switch network? Explain with a neat sketch. (b) How many switch points are there in a cross bar switch network that connect p Processors to m Memory modules [12+4M] SET-4 1. (a) Describe briefly about Von Neumann and Harward architectures. (b) Distinguish between error detection and correction codes. What do you understand by odd parity and even parity? What is odd function and even function? To calculate odd and even parity values which functions can be used? Calculate Odd and even parity values for all hexadecimal digits 0-9 and A-F. [6+10M] 2. Design a circuit to implement the following RTL instructions. Mention about control logic. Assume A,B are 4-bit registers using JK flip-flops. [16M] A A + B B A + B 3. (a) Why do we need some bits of current microinstruction to generate address of the next microinstruction? Support with a live example. (b) Discuss about functioning of micro programmed control unit. [8+8M] 4. (a) Explain how we can identify arithmetic overflow is occurred while adding/subtracting two signed numbers. Draw the circuit for performing addition/subtraction of two 4 bit numbers that checks the over flow. (b) Explain restoring method of division with two 4 bit numbers. [8+8M] 5. (a) Explain the operation of a static RAM cell.

(b) Explain the internal organization of 1M1 dynamic memory chip. (c) How should you build 64K8 memory module using 16K1 static memory chips. [4+6+6M] 6. What are the different kinds of I/O Communication techniques? What are the relative advantages and disadvantages? Compare and contrast all techniques. [16M] 7. (a) What is Flynns classification? Categorize the different streams in it. (b) Explain SIMD array processor organization. [8+8M] 8. (a) Explain the working of a five dimensional hpercube network with a neat sketch. (b) Draw a diagram showing the structure of four-dimensional Hypercube network. List all the parts available from node 7 to node 9 that use a minimum number of intermediate nodes. [8+8M] II B.Tech II Semester (R07) Regular/supply Examinations, Apr- 2010,CSE

Set-1

1. a) List and explain different interconnection structures used in multiprocessors? b) Perform the arithmetic operations (+42)+(-13) and (-42)-(-13) in binary using 2s complement representation for negative numbers. (8+8M) 2. a) Explain how Z = (X-Y) / (X+Y) is evaluated in a stack based computer. b) Explain the properties of Reduced Instruction Set Computers. (8+8M) 3. What are the design goals while designing the Control Unit? Explain the Hardwired control and Micro programmed control. Mention their advantages and disadvantages. (16M) 4. a) Explain Booths algorithm from its theoretical basis. b) Multiply 10101 with 10011 using Booths algorithm. (8+8M) 5. Explain the following memories with their applications. a) ROM b) PROM c) EPROM d) EEPROM (4+4+4+4M) 6. List and explain different I/O communication techniques. Also mention their advantages and disadvantages. (16M) 7. a) What is meant by pipelining? Explain. b) Explain the following with related to the instruction pipeline

i) . Pipeline conflicts ii). Hardware interlocks iii). Pre-fetch target instruction iv). Branch target buffer (8+8M) 8. a) Explain the characteristics of multiprocessors. b) Explain the need for interprocessor synchronization. (8+8M)

Set-2
1. a) Explain about various buses such as internal, external, I/O, system, address and data bus. b) Perform the arithmetic operations (+70)+(+80) and (-70)+(-80) in binary using 2s complement representation for negative numbers. (10+6M) 2. Write short notes on the following: a) Register transfer language b) Instruction formats c) Addressing modes d) Reduced Instruction Set Computer (4+4+4+4M) 3. a) Explain why hardwired control unit is faster than micro programmed control unit. b) What are micro-subroutines? Explain. (8+8M) 4. a) Draw a flow chart which explains multiplication of two signed magnitude fixed point numbers. b) Multiply 10101 and 10111 with the above procedure. (8+8M) 5. What is Cache memory? Explain the different mapping techniques used in the usage of Cache memory. (16M) 6. What is Direct Memory Access (DMA)? What is the need for DMA? Explain the working of DMA. Also mention its advantages. (16M) 7. a) What is meant by instruction pipeline? Explain b) Explain the pipeline for floating point addition and subtraction. (8+8M) 8. a) List and explain different interconnection structures used in multiprocessors? b) Explain system bus structure for multiprocessors with a neat sketch. Set-3 1. a) List and explain different types of computers with examples. Also mention their

merits and demerits. b) What is meant by odd parity and even parity? c) Distinguish between error detection and correction codes. (8+3+5M) 2. What is Register Transfer Language? Explain few RTL statements for branching from their actual functioning. (16M) 3. Define and explain the following a) Micro operation b) Microinstruction c) Micro program d) Microcode (4+4+4+4M) 4. a) How many bits are needed to store the result of addition, subtraction, multiplication of two n-bit unsigned numbers? Prove. b) What is overflow and underflow? What are the reasons for overflow and underflow? (8+8M) 5. With suitable examples, explain two-way set associative mapping and fourway set associative mapping. (16M) 6. Explain the following a) Input-Output Processor b) Direct Memory Access c) Interconnected (PCI) bus (6+5+5M) 7. a) What is meant by arithmetic pipeline? Explain. b) Explain about three segment instruction pipeline. (8+8M) 8. a) Explain multi port memory organization with a neat sketch. b) What is cache coherence? Explain its importance. (8+8M) SET-4 1. a) List and explain different performance measures used to represent a computer system performance. b) Explain about sign magnitude and 2s complement approaches for representing the fixed point numbers. Explain why 2s complement approach is preferable. (8+8M) 2. a) List and explain few arithmetic, logic and shift micro operations. b) What is an interrupt? Explain different types of interrupts. (8+8M) 3. a) Explain the difference between hardwired control and micro programmed control. Is it possible to have a hardwired control associated with a central memory?

b) What is microinstruction? How do we reduce number of microinstructions? (8+8M) 4. With neat flowcharts and examples, explain how two IEEE 754 flowing point numbers can be added, subtracted and multiplied. Assume single precision numbers. (16M) 5. a) Compare and contrast asynchronous DRAM and synchronous DRAM. b) Compare and contrast direct and associative mapping techniques. (8+8M) 6. Explain different standard serial communication protocols like RS232, USB, IEEE 1394. (16M) 7. Explain the flowing a) RISC pipeline b) Vector processing c) Array processor (6+5+5M) 8. What is cache coherence? Explain its importance in shared memory multiprocessor systems? (16M) III B.Tech I Semester Regular Examinations Nov2009,EEE

Set No. 1
1. (a) Write the algorithm for multiplying two floating point numbers. (b) Multiply 0.45x1049 and 0.50x1049 (c) Add 0.147x103 and 0.789x103[6+5+5] 2. (a) Construct a common bus system with multiplexers for four registers. (b) Discuss the type of instruction formats with examples.[7+9] 3. (a) Write the micro-operation for the following instructions (i) BSA (ii) BUN (iii) LDA (b) What is interrupt cycle? Draw the flow chart which shows how computer Handles the interrupt.[6+10] 4. (a) how is an instruction mapped to a microinstruction address. (b) Give the implementation of conditional branching with multiplexers.[8+8] 5. (a) Explain briefly about dynamic random access memory with a neat diagram. (b) What is the difference between static memory cell and a dynamic memory cell? Which of these can be none destructively read out?[8+8] 6. (a) in how many ways data can be transferred from I/O units to or from memory? Explain. (b) Explain Daisy chaining method. [10+6]

7. (a) what is meant by pipeline hazard? Explain delay due to data dependency with An example. (b) Compare different types of parallel computers.[10+6] 8. (a) Discuss the difference between tightly coupled and loosely coupled Multi processors. (b) What is the purpose of system bus controller? Explain how the system can be Designed to distinguish between references to local memory and references to Common shared memory?[6+10] Set-2 1. (a) Write the steps in subtraction of unsigned numbers. (b) Illustrate the layered view of a computer system with a diagram.[7+9] 2. How are register reference instructions recognized by the program control? Illustrate With a flow chart. Give some example for register reference instructions.[16] 3. (a) how is a 64-word stack implemented. Write the micro operations of PUSH and POP operations. (b) Convert ABCDE+*-/ into reverse polish notation. (c) Convert A+B*(C*D+E*(F+G)) into reverse polish notation.[6+5+5] 4. Give the detailed design of micro programmed control unit. Explain.[16] 5. (a) Write the types of ROM? Give Applications of ROM. (b) Illustrate fully associative mapping with a neat diagram.[8+8] 6. (a) what is meant by Software Polling? (b) Illustrate asynchronous read with the help of Timing Diagram[7+9]. 7. (a) what are the operations in a three segmented pipeline? Give an example that uses Delayed load with the three segment pipeline. (b) Consider the multiplication of two 40 x 40 matrices using a vector processor. How many product terms are there in each inner product?[8+8] 8. (a) Draw the diagram of a three dimensional hypercube. List all the paths available from node 2 to 7. (b) How can the cache coherence problem be solved using cache write back policy?[8+8] SET-3 1. (a) Multiply the following numbers represented in twos complement form

(i) 0011011 x 1011011 (ii) 101101 x 110011 (b) Represent (0.625) decimal in binary floating point form (c) Illustrate the long hand division of binary integers 1011 by 11.[6+4+6] 2. (a) Draw the diagram of a bus system for four registers. Use three state buffers and a decoder instead of multiplexers. (b) Illustrate logic micro operations with examples.[8+8] 3. (a) What are the characteristics of RISC processor? Discuss briefly. (b) What is a subroutine? Write the differences between subroutine and program.[8+8] 4. (a) Give the format of micro instruction. Explain the use of each field in it. (b) Explain the difference between hardwired control and micro programmed Control[8+8] 5. (a) What are the design decisions made in the design of cache memory system? (b) Compare and contrast the methods of mapping memory to a cache. [8+8] 6. (a) Give the configuration of the DMA interface and its connection to the CPU Through buses? Explain how the DMA interface functions. [16] 7. (a) Show how instruction cycle in a CPU can be processed with a four segment Pipeline. (b)Write the pipeline conflicts that cause the instruction pipeline to deviate from its normal operation. [8+8] 8. (a) Describe the following terminology associated with multiprocessors i) Mutual exclusion ii) critical section iii) hardware lock iv) Semaphore (b) Construct the diagram for an 8x8 omega switching network. Show the switch setting required to connect input 3 to output 1. [8+8] Set -4 1. (a) Represent decimal number 8620 in i) Self complementary code ii) weighted code iii) EBCDIC (b)Perform the arithmetic operation (+42) + (-13) and (-42)-(-13) in binary using signed Twos complement representation for negative numbers. (c) Represent the number (+46.5)10 as floating point binary number with 24bits. The Normalized fraction mantissa has 16-bits.[6+4+6] 2. (a) Draw the diagram of 4-bit adder sub tractor circuit. Explain Briefly.

(b) What is the difference between a direct and indirect address instruction? How many References to memory are needed for each type of instruction to bring the operand Into a processor register. [8+8] 3. Briefly explain the use of overlapped register widows in RISC processor with an Example.[16] 4. (a) Explain how the mapping from an instruction address can be done by means of read Only memory? (b) Write briefly about symbolic micro instruction with examples. [8+8] 5. (a) How can the virtual address translation be made faster? Illustrate with a block Diagram. (b) Define Hit Ratio. How are the hit ratio and cache size related? Doe the hit ration Increases with cache bits. [8+8] 6. (a) Write the steps for data transfer in program control data transfer. (b) Describe the types of bus arbitration techniques. [8+8] 7. (a) Write Flynns classification of parallel computer. (b) Write the classification of parallel computers based on mode of accessing memory. [8+8] 8. What is cache coherence? Why is it important in shared memory multiprocessor? Systems? How can the problem be resolved with a snoopy cache controller? [16]

III B. Tech I Semester Supplementary Examinations, MAY 2010,EEE 1. (a) What are the different types of Computers? Illustrate the layered view of a computer system with a diagram. [10 M] (b) Convert the hexadecimal number F3A7C2 to binary and octal. [6 M] 2. (a) What is a three state buffer? [3 M] (b) Construct a bus system with three state buffers. [9 M] (c) Explain the memory operation in the following, R2M [AR], M[AR]R3 [4 M] 3. (a)What are memory reference instructions? Write the sequence of micro operations needed to execute these instructions. [10 M] (b) Illustrate with a neat flow chart, how a interrupt is handled by a computer [6 M]

4. (a) Draw the block diagram for control memory. Explain how next micro instruction address is selected [10 M] (b) How is mapping between instruction codes to microinstruction address done? [6 M] 5. (a) What is the relation between address and memory space in a virtual memory system? [6 M] (b) Show the organization of memory table in a paged system with a neat diagram. Explain briefly. [10 M] 6. (a) Draw the block diagram of asynchronous communication interface. Illustrate its function as transmitter & receiver. [8 M] (b) Describe daisy chaining priority interrupt with a diagram. [8 M] 7. (a) Write the pipeline conflicts that cause the instruction pipeline to deviate from its normal operation. [8 M] (b) What are the operations in a three segmented pipeline? Give an example that uses delayed load with the three segment pipeline. [8 M] 8. Describe any four interconnection structures with neat diagram. [16 M] Set-2 1. (a) Draw the diagram of functional unit. Explain its working in detail.[10 M] (b) Write short notes on error detection codes. [6 M] 2. (a) Design a 4 bit binary adder. [6 M] (b) Illustrate the following logic micro operations i) Selective set ii) selective complement iii) selective clear iv) Mask v) Clear [5x2=10 M] 3. (a) Discuss data manipulation and transfer instructions with examples.[8 M] (b) What are the characteristics of RISC? How is a procedure call and return handled by RISC? [8 M] 4. (a) Give the format for micro instruction. Write the micro operations for SUB, READ, WRITE, ADD, XOR, and INCPC. [8 M] (b) What are the basic components of a micro programmed control unit? Explain with a diagram. [8 M] 5. (a) Define and explain (i) Write through into cache (ii) Write back into cache [3+3+2 M] (iii) Hit ratio (b) How is a virtual address mapped into physical address? _ _ [8 M 6. (a) Describe the types of bus arbitration techniques. [8 M] (b) Write short notes on simplex, half duplex, full duplex transmission of data. [8 m] 7. (a)Write the classification of parallel computers based on mode of accessing memory. [8 m]

(b)Show how instruction cycle in a CPU can be processed with a four segment pipeline. [8 m] 8. (a) What are the characteristics of Multi Processors? [6 M] (b) Write about Crossbar switch and Multi Stage Switching network.[10 M] Set-3 1. (a) Illustrate the different bus structures with neat diagram. [8 m] (b) Perform the arithmetic operations (+42) (-13) in binary using signed 2s Complement representation. [8 m] 2. (a) Draw the diagram of 4bit arithmetic circuit for arithmetic operations. Give the function table. [8 M] (b) Give the symbolic notation for shift micro operations. Explain with examples. [8 M] 3. (a) What is a register stack? What are the sequence of micro operation performed to implement push and pop operations? [8 M] (b) Illustrate three and two address instructions with examples. [8 M] 4. What are the components of a control unit? Describe the design of control unit with a neat diagram. [16 M] 5. (a) Write short notes on RAM and ROM chips. [8 M] (b) Illustrate fully associative mapping with a neat diagram. [8 M] 6. (a) Draw the block diagram of DMA controller. Explain how data is transferred. [10 M] (b) Compare Isolated I/O with memory mapped I/O. [6 M] 7. Describe the following (i) Delayed Branch [6 M] (ii) Memory interleaving. [5 M] (iii) Pipeline conflicts. [5 M] 8. (a) What is meant by inter process communication? Explain how inter process synchronization is done using semaphores. [8 M] (b) What is meant by cache coherence? Discuss the various schemes used to solve the cache coherence problem. [8 M] SET-4 1. (a) Write the steps in 2s complement subtraction. [6 M] (b) Perform the subtraction with the following unsigned binary numbers by taking the 2s complement representation of the subtrahend. (a) 11010 10000 c) 11001- 1010 (b) 11010 1101 d) 10101- 01111 e) 1111111-111000 [5x2=10 M] 2. (a) List Logic Micro Operations. Give examples [8 M] (b) Give the design of arithmetic logic shift unit. Discuss briefly. [8 M] 3. (a) What is a memory stack? What are the sequence of micro operations performed to implement push and pop operations? [8 M]

(b) What are the types of instructions formats? Illustrate with examples. [8 M] 4. (a) What is meant by address sequencing? How is it done? [8 M] (b) What are the microinstructions needed for fetch and decode routine? Explain. [8 M] 5. (a) Explain the match logic of each word in associate memory with a neat diagram. [8 M] (b) Explain set associative mapping with example. [8 M] 6. (a)Give the truth table of a priority encoder. Explain its implementation. [8 M] (b) Illustrate the different modes of data transfer to and from peripherals. [8 M] 7. (a) What is meant by pipeline hazard? Explain delay due to data dependency with an example. [10 M] (b) Write the applications of vector processing. [6 M] 8. (a)Draw the diagram of a three dimensional hypercube. List all the paths available from node 3 to 7. [8 M] (b) How can the cache coherence problem be solved using cache write back policy? [8 M]