Introduction to Layout in FreePDK 45nm:

(Adapted from http://www.eda.ncsu.edu/wiki/Tutorial:Layout_Tutorial#1 and http://www.eda.ncsu.edu/wiki/Tutorial:Layout_Tutorial2 - Please reference these tutorials for any issues you might have before contacting a TA)
1. Introduction
This is a guide for layout on FreePDK 45nm. It is recommended that you read through this document first before attempting the steps.

2. Setting Calibre
If you followed the Cadence setup tutorial correctly you should be all set up to proceed with layout, DRC, LVS, and Parasitic Extraction for your circuits. Now you can start Cadence normally and proceed with this tutorial.

3. Create a new library

In the Library Manager, create a new library called mylib. Select File->New->Library. This will open new dialog window, in which you need to enter the name and directory for your library. By default, the library will be created in the current directory. After you fill out the form, it should look something like this:

Figure 1: New Library

Click OK. Next, you will see a window asking you what technology you would like to attach to this library. Select "Attach to an existing technology library" and click OK. In the next window, select "NCSU_TechLib_FreePDK45". You should see the library "mylib" appear in the Library Manager.

Create New Layout View

Next, select the library you just created in the Library Manager and select File->New->Cell View.... We will create a layout view of an inverter cell. Simply type in "inv" under cell-name and "layout" under view. Click OK or hit "Enter". Note that the "Application" is automatically set to "Layout L", the layout editor.

Figure 2: New File Click Ok. You may see a warning about upgrading the license. Simply click Ok to ignore this warning. After you hit "OK", the Virtuoso screen will appear as shown below. In addition, the LSW window (Layer Selection Window), which shows various mask layers, will automatically pop up.

Figure 3: Virtuoso screen

4. Laying out an Inverter

Some tips before you start: You may notice that you might not be able to view all the hierarchy in the layout. To fix this hit E in the layout window to get the Display Editor and set the maximum display level to 32 (from 0). Another thing that you might want to do is turn off the gravity. Gravity will basically bring your cursor to the closest edge which can be annoying at times. To turn the gravity off hit Shift-E in the layout window and uncheck the Gravity On box.

NOTE: The NMOS and PMOS layout models (pcells) dont work so you will need to draw all the transistor layouts yourself!
Figure 4 shown a completed inverter in FreePDK45. Create the metal1 and poly for an inverter, as shown in Figure 5. Note the little rectangles which indicate the pins (you can ignore them for now).

Figure 4: A completed sample inverter layout.

Figure 5: The metals and poly.

Figure 6: The Nwell and Pwell and implant

Using this approach, you should be able to figure out that the NMOS uses the following layers: pwell, active, nimplant, poly, metal1, contact, and text. The PMOS is like it, except that it uses layers pimplant and nwell instead of pwell and nimplant. Note also the letters "drw", "net", and "pin" next to each entry in the LSW. These are the purposes of a shape. The purpose is used to indicate special functionality of a shape.

5. DRC
To perform a Design Rule Check (DRC), choose Calibre->Run DRC. The DRC form appears, as shown below. Go to the Rules tab, and change the DRC Rules File to /$PDK_DIR/ncsu_basekit/techifle/calibre/calibleDRC.rul to point at the calibre rules file.. Now, load the calibreDRC.rul file. Then click "Run DRC".

Figure 7: DRC dialog window

Viewing DRC Errors (Please refer to the DRC_Rules pdf file that was also uploaded to T-Square to understand the DRC rules in more detail)
You can learn about the errors by clicking on the rule in the Results Viewing Environment (RVE) window that pops up after DRC is complete.

Figure 8: DRC RVE

Keep modifying your layout until there are no errors. You will know that there are no errors when there are no red boxes in the RVE. Alternatively, you can look in the file inv.drc.summary. When the layout is "DRC Clean", the last line of this file should read "TOTAL DRC Results Generated: 0". Lastly, we need to create pins so that the nodes in our layout have names that are humanreadable. Create these pins by selecting Create->Pin. You should see a dialog box appear, like the one below. Type the names vdd!, gnd!, in, and out in the Terminal Names text-box as shown below. Select Display Pin Name. Leave all other options as they are.

Figure 9: Create Shape Pin Next, click the Display Pin Name Option button. You will see another dialog box appear:

Figure 10: Pin Name Display

Figure 11: The inverter DRC Clean

6. LVS
LVS checks your layout against your schematic. To perform a layout-vs.-schematic (LVS), choose Calibre->Run LVS.... The LVS form appears, as shown below.

Figure 12: LVS dialog box There are a number of options you need to set and know what they are. Rules: Go to the Rules tab, and change the LVS Rules File to /$PDK_DIR/ncsu_basekit/techifle/calibre/calibleLVS.rul to point at the calibre rules file. Inputs Select "Hierarchial", "Layout vs Netlist" Under the Layout tab Files : nand2.calibre.gds(what names you did save as: nand2 would be changed) Top Cell: nand2 Layout Netlist: nand2.sp These options are already be filled in by the tool, leave them as is Format: select "GDSII" and select the option "Export from layout viewer" (This is very important) Under the Netlist tab
Files: nand2.src.net Top Cell:nand2

These options are already be filled in by the tool, leave them as it is Format: select "SPICE" and select the option "Export from schematic viewer" (This is very important) Outputs Under the Report/SVDB LVS Report File: nand2.lvs.report This option is already be filled in by the tool, leave it as is svdb directory: svdb_nand2 Select "View Report after LVS Finishes"

Perform an LVS Check without Errors

Set the LVS form with the options shown above. Then click the Run LVS button. If LVS runs successfully, with out any error, then you will see the below window with a smilie :) Click on the "Transcript" tab in Calibre Interactive - LVS to see the log file.

Figure 13: LVS Report without errors

Extract Parasitics
Next, fix the layout of the inv gate and save the design. Now were going to extract the parasitic wire capacitances and resistances from the layout. To perform a Parasitic Extraction(PEX), choose Calibre->Run PEX.... The PEX form appears, as shown below.

Figure 14: PEX dialog box

Extract with Parasitic Capacitances and Resistances

There are a number of options you need to set and know what they are. For options not mentioned below, leave them as it is. We will use them in future if required. Rules: Calibre-PEX Rules File and Calibre-PEX Run Directory are already filled in by the tool, you may change the path for rules. Change the path of the PEX Rules File to the following /$PDK_DIR/ncsu_basekit/techifle/calibre/caliblexRC.rul. Make sure where you want to simulate the files. Directory should be same folder where you saved the layout file. Inputs
Under the Layout tab Files : inv.calibre.gds Top Cell: inv

These options are already be filled in by the tool, leave them as is Format: select "GDSII" and select the option "Export from layout viewer" (This is very important) Under the Netlist tab
Files: inv.src.net Top Cell:inv

These options are already be filled in by the tool, leave them as is Format: select "SPICE" and select the option "Export from schematic viewer" (This is very important) Outputs Extraction Type: Select Transistor Level, R + C + CC, No Inductance Under the Netlist tab File: inv.pex.netlist This option is already be filled in by the tool, leave it as is Format: HSPICE Use Names From: SCHEMATIC select "View netlist after PEX finishes" Under the Nets tab Extract parasitics for: Select "All Nets" Under the Reports tab PEX Report File: inv.pex.report This option is already be filled in by the tool, leave it as is Select "Generate PEX Report" and "View Report after PEX finishes" Under the SVDB tab SVDB Directory: svdb_inv Select "Generate cross-reference data for RVE" and "Start RVE after PEX"

Figure 15: PEX Report without errors