MC14008B

4-Bit Full Adder

The MC14008B 4bit full adder is constructed with MOS
Pchannel and Nchannel enhancement mode devices in a single
monolithic structure. This device consists of four full adders with fast
internal lookahead carry output. It is useful in binary addition and
other arithmetic applications. The fast parallel carry output bit allows
highspeed operation when used with other adders in a system.

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LookAhead Carry Output

Diode Protection on All Inputs
All Outputs Buffered
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Lowpower TTL Loads or One Lowpower
Schottky TTL Load Over the Rated Temperature Range
PinforPin Replacement for CD4008B

MARKING
DIAGRAMS
16
PDIP16
P SUFFIX
CASE 648

MC14008BCP
AWLYYWW
1
16

SOIC16
D SUFFIX
CASE 751B

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)

Parameter

Value

Unit

0.5 to +18.0

0.5 to VDD + 0.5

Input or Output Current

(DC or Transient) per Pin

10

mA

PD

Power Dissipation,
per Package (Note 3.)

500

mW

TA

Ambient Temperature Range

55 to +125

Tstg

Storage Temperature Range

65 to +150

TL

Lead Temperature
(8Second Soldering)

260

Symbol
VDD
Vin, Vout
Iin, Iout

DC Supply Voltage Range

Input or Output Voltage Range
(DC or Transient)

2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.

Semiconductor Components Industries, LLC, 2000

March, 2000 Rev. 3

14008B
AWLYWW
1
16

SOEIAJ16
F SUFFIX
CASE 966

MC14008B
AWLYWW
1

A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

ORDERING INFORMATION
Device

Package

Shipping

MC14008BCP

PDIP16

2000/Box

MC14008BDR2

SOIC16

2500/Tape & Reel

SOEIAJ16

See Note 1.

MC14008BF

1. For ordering information on the EIAJ version of

the SOIC packages, please contact your local
ON Semiconductor representative.

Publication Order Number:

MC14008B/D

MC14008B
TRUTH TABLE
(One Stage)
Cin

Cout

0
0
0
0

0
0
1
1

0
1
0
1

0
0
0
1

0
1
1
0

1
1
1
1

0
0
1
1

0
1
0
1

0
1
1
1

1
0
0
1

PIN ASSIGNMENT
A4

16

VDD

B3

15

B4

A3

14

Cout

B2

13

S4

A2

12

S3

B1

11

S2

A1

10

S1

VSS

Cin

BLOCK DIAGRAM

HIGHSPEED
PARALLEL CARRY
B4 15
A4

B3

A3

B2

A2

B1

A1

Cin

14 Cout

ADDER
4

13 S4

C4
ADDER
3

12 S3

C3
ADDER
2

11 S2

C2
ADDER
1

10 S1
VDD = PIN 16
VSS = PIN 8

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2

MC14008B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Characteristic

Symbol

55_C

25_C

125_C

VDD
Vdc

Min

Max

Min

Typ (4.)

Max

Min

Max

Unit

Output Voltage
Vin = VDD or 0

0 Level

VOL

5.0
10
15

0.05
0.05
0.05

0
0
0

0.05
0.05
0.05

0.05
0.05
0.05

Vdc

Vin = 0 or VDD

1 Level

VOH

5.0
10
15

4.95
9.95
14.95

4.95
9.95
14.95

5.0
10
15

4.95
9.95
14.95

Vdc

Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)

VIL

5.0
10
15

1.5
3.0
4.0

2.25
4.50
6.75

1.5
3.0
4.0

1.5
3.0
4.0

(VO = 0.5 or 4.5 Vdc) 1 Level

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

VIH

5.0
10
15

3.5
7.0
11

3.5
7.0
11

2.75
5.50
8.25

3.5
7.0
11

5.0
5.0
10
15

3.0
0.64
1.6
4.2

2.4
0.51
1.3
3.4

4.2
0.88
2.25
8.8

1.7
0.36
0.9
2.4

IOL

5.0
10
15

0.64
1.6
4.2

0.51
1.3
3.4

0.88
2.25
8.8

0.36
0.9
2.4

mAdc

Input Current

Iin

15

0.1

0.00001

0.1

1.0

Adc

Input Capacitance
(Vin = 0)

Cin

5.0

7.5

pF

Quiescent Current
(Per Package)

IDD

5.0
10
15

5.0
10
20

0.005
0.010
0.015

5.0
10
20

150
300
600

Adc

IT

5.0
10
15

Output Drive Current

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)

Vdc

IOH

Source

Sink

Total Supply Current (5.) (6.)

(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)

Vdc

mAdc

IT = (1.7 A/kHz) f + IDD

IT = (3.4 A/kHz) f + IDD
IT = (5.0 A/kHz) f + IDD

4. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
5. The formulas given are for the typical characteristics only at 25_C.
6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL 50) Vfk

where: IT is in A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.005.

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3

Adc

MC14008B

SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)

Characteristic

Symbol

Output Rise and Fall Time

tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns

Min

Typ (8.)

Max

5.0
10
15

100
50
40

200
100
80

Unit
ns

tTLH,
tTHL

Propagation Delay Time

Sum in to Sum Out
tPLH, tPHL = (1.7 ns/pF) CL + 315 ns
tPLH, tPHL = (0.66 ns/pF) CL + 127 ns
tPLH, tPHL = (0.5 ns/pF) CL + 90 ns
Sum In to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 220 ns
tPLH, tPHL = (0.66 ns/pF) CL + 112 ns
tPLH, tPHL = (0.5 ns/pF) CL + 85 ns
Carry In to Sum Out
tPLH, tPHL = (1.7 ns/pF) CL + 290 ns
tPLH, tPHL = (0.66 ns/pF) CL + 122 ns
tPLH, tPHL = (0.5 ns/pF) CL + 90 ns
Carry In to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 85 ns
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns
tPLH, tPHL = (0.5 ns/pF) CL + 30 ns

VDD
Vdc

tPLH, tPHL

ns

5.0
10
15

400
160
115

800
320
230

5.0
10
15

305
145
110

610
290
220

5.0
10
15

375
155
115

750
310
230

5.0
10
15

170
75
55

340
150
110

7. The formulas given are for the typical characteristics only at 25_C.
8. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.

VDD = VGS

Vout

VDD = VGS

16
B4
A4
B3
A3
B2
A2

S4

B1
A1
Cin

S1

16

S3
S2
IOH

Cout
VSS

Vout

EXTERNAL
POWER
SUPPLY

B4
A4
B3
A3
B2
A2

S4

B1
A1
Cin

S1

Figure 1. Typical Source Current

Characteristics Test Circuit

S3
S2
IOL

Cout
VSS

EXTERNAL
POWER
SUPPLY

Figure 2. Typical Sink Current

Characteristics Test Circuit

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4

MC14008B
VDD
16

20 ns

Vin

20 ns

90%
10%

VDD
VSS

PULSE
GENERATOR

B4
A4
B3
A3
B2
A2

S4

B1
A1
Cin

S1

S3
S2
CL
CL
CL

Cout

CL
CL

VSS
IDD

500 F

Figure 3. Dynamic Power Dissipation Test Circuit and Waveform

VDD
16
B4
A4
B3
A3
B2
A2
B1
A1

PULSE
GENERATOR

Cin
8

S4
S3
S2
CL

S1
CL
CL

Cout

CL
CL

VSS
IDD

20 ns
Cin

20 ns
VDD

90%
50%
10%

VSS
tPHL

tPLH
VOH

90%
50%
10%

S1 S4

VOL

tTHL

tTLH
VOH

Cout

50%
VOL
tPLH

tPHL

Figure 4. Switching Time Test Circuit and Waveforms

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5

MC14008B
Cout

B4

S4

A4
B3

S3

A3
B2

S2

A2
B1

S1

A1
Cin

Figure 5. Logic Diagram

TYPICAL APPLICATION
WORD A + B INPUTS
A1

Cin

S1

B4

CHIP
1

Cout

S4

A1

Cin

S1

B4

CHIP
2

Cout

S4

A1

Cin

S1

B4

CHIP
3

Cout

S4

A1

Cin

B4

CHIP
4

S1

SUM OUTPUTS
Calculation of 16bit adder speed:
tP total = tP (Sum to Carry) + tP (Carry to Sum) + 2 tP (Carry to Carry)
The guaranteed 16bit adder speed at 10 V, 25C, CL = 50 pF is:
tp total = 290 + 310 + 300 = 900 ns

Figure 6. Using the MC14008B in a 16Bit Adder Configuration

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6

Cout

S4

MC14008B
PACKAGE DIMENSIONS

PDIP16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 64808
ISSUE R

A
16

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.

DIM
A
B
C
D
F
G
H
J
K
L
M
S

S
T

SEATING
PLANE

H
G

16 PL

0.25 (0.010)

T A

16

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

B
1

8 PL

0.25 (0.010)

X 45 _

C
SEATING
PLANE

M
D

16 PL

0.25 (0.010)

MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01

SOIC16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B05
ISSUE J

INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040

T B

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7

DIM
A
B
C
D
F
G
J
K
M
P
R

MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50

INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019

MC14008B
PACKAGE DIMENSIONS

SOEIAJ16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 96601
ISSUE O

16

LE

Q1
M_

E HE
1

DETAIL P

Z
D
e

VIEW P

A1

b
0.13 (0.005)

0.10 (0.004)

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z

MILLIMETERS
MIN
MAX

2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90

0.78

INCHES
MIN
MAX

0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035

0.031

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are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be
validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
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8

MC14008B/D